ASSOCIATION CONNECTING

ELECTRONICS INDUSTRIES

IPC-MC-790

Guidelines for Multichip

Module Technology
Utilization

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IPC-MC-790
July 1992 A standard developed by IPC

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 IPC-MC-790
ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES

Guidelines for Multichip

Module Technology
Utilization

Developed by the IPC Multichip Module Subcommittee of the Hybrid and

Related Technologies Committee of IPC

About this document

This document published by IPC is for informational purposes and can serve
as a baseline for selecting an appropriate MCM technology. It is not intended
to be a standard and in fact, this document is expected to evole with significant
technological developments.
This document reports on work which has been done by a variety of individuals
and organizations concerned with increasing system performance and reliability
through multichip module technology. You, as the reader, are invited to review
the content of this document and communicate your comments and ideas for
additional details that may serve the industry to the appropriate trade associ-
ations or technical societies. In this way, the infrastructure necessary to
implement this new philosophy for packaging will make its way forward.
Thanks to Chairman Phil Marcoux, ISHM and IPC are in the process of a
detailed update program. It is expected that the result of this effort will culminate
in a hardbound version that will provide an excellent reference tool. IPC will also
consider future review of the MC-790 as more information becomes available.
You are invited to participate in any of the revision or update processes.

Users of this standard are encouraged to participate in the

development of future revisions.

Contact:
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IPC
2215 Sanders Road
Northbrook, Illinois
60062-6135
Tel 847 509.9700
Fax 847 509.9798
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 IPC-MC-790 July 1992

Acknowledgment
Any Standard involving a complex technology draws material from a vast number of sources. While the principal members
of the IPC Multichip Module Subcommittee of the Hybrid and Related Technologies Committee are shown below, it is not
possible to include all of those who assisted in the evolution of this standard. To each of them, the members of the IPC
extend their gratitude.

Hybrid and Related Multichip Module Technical Liaison of the

Technologies Committee Subcommittee IPC Board of Directors
Chairman Chairman
Robert Lomerson Phil Marcoux William Miller
General Dynamics PPM Associates Wm. Miller & Assoc.

Multichip Module Subcommittee

P.J. Amick, Mc Donnell Douglas F.J. Dance, Burndy Corporation K.S. Hill, Hughes Aircraft Co.
Elec. Sys Co. M.J.Di Franza, Mitre Corp. P.E. Hinton, Hinton ‘‘PWB’’
R. Anderson, NCR Corp. D. Dinella Engineering
E.M. Aoki, Hewlett Packard R.R. Douglas, Douglas & Assoc. S. Ho, Western Digital Corp.
Laboratories J.T. Hoback, Amoco Chemical
F. Durso, Mac Dermid & Assoc.
A.K. Arora, University of Maryland Company
R.E. Egloff, Acheson Colloids Co.
J. Bakszt, Ericsson Telecom D.L. Holland, Lockheed Sanders Inc.
R. Eldridge, Amphenol
S. Banks, Sanwa Electric Corp. S.T. Holzinger, Rogers Corp.
J.A. Emerson
P. Barela, Jet Propulsion Lab M. Hook, U.S. Navy
G.P. Evans, Indium Corp. of America
M.G. Bevan, Johns Hopkins A.S. Hoover, Alpha Metals Inc.
J.W. Evans, NASA HQ
University S.R. Hudson
M.S. Fan, Paramax Systems Corp.
P. Boudreau, Hughes Aircraft Co. L. Hymes, Plexus Corp.
P. Farris, Motorola Inc.
C. Bradshaw, Memorex Telex Corp. E. Ichkhan, Hughes Aircraft Co.
Dr. R.J. Fedor, Gould Inc.
B.J. Bremmer W.I. Jacobi, William Jacobi & Assoc.
G.M. Ferrari, Tech Circuits Inc.
C.P. Brooks, AMP Inc. D. Jacobus, Control Data Corp.
J. Fjelstad, Elf Technologies
M.P. Burdzy, Loctite Corp. M. Jagernauth, Northern Telecom
D.H. Frailey, Metcal Inc.
J.S. Burg, 3M Co. M.W. Jawitz, Litton Guidance &
D. Fritz, Mac Dermid Inc.
J. Burgess, Amoco Chemical Co. Control Systems
V. Gandhi, Teradyne Connections

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E.S. Cain, Tribotech C.F. Johnson, Hercules Inc.
Systems
D. Caissie, Teradyne Connections J.R. Jones, Pacific Missile Test Center
L.E. Gates, Hughes Aircraft Co.
Systems R.A. Jones, IBM Corp.
M. Gibbel, Jet Propulsion Lab
T. Canning, Rockwell International J.A. Kelly, Motorola Inc.
G. Ginsberg, Component Data
A. Cash, Northrop Corp. G.W. Kenealey, Control Data Corp.
Associates
E. Cassinelli P.J. Kenney, Acheson Colloids Co.
P. Goldman, Kalmus & Associates
D.D. Chang, AT&T Bell Laboratories Inc. W.G. Kenyon, E I DuPont De
M. Clawson, Jet Propulsion Lab C. Gonzalez, SCI Manufacturing Inc. Nemours & Co.
C. Cleveland, Boeing Aerospace & B.W. Gray, Bull HN Information D.H. Knapke, U.S. Air Force
Electronics Systems G. Kotecki, Northrop Corp.
C.A. Connett, 3M Co. F. Gray, Texas Instruments Inc. J.J. Kozuch, 4DI Inc.
Z.F. Crawley, Rhone Poulenc Inc. W.J. Green, Methode Electronics Inc. J.J. Kreuzpaintner, Martin-Marietta
L.A. Crouch M.I. Gurian, Advanced Systems Inc. Corp.
D. Currie, Teledyne Systems Co. B. Hamilton, Flex Products Inc. F. Kuwako, Taiwan Copper Foil Co
D. Currier, Ambitech Inc. Ltd.
F. Harwath, Molex Inc.

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 July 1992 IPC-MC-790

P. Lall, University of Maryland W. Olssen, Lockheed Engineering Dr. L. Schoenberg, AT&T Bell
J.F. Legein, Raytheon Co. W.A. Ortloff, Hughes Aircraft Co. Laboratories
J.D. Leibowitz, Shireline Composites K. Osaka, Shin-Kobe Electric L. Scholten, Optrotech Inc.
Inc. Machinery M.L. Seltzer, Delco Systems
T. Li, Martin-Marietta Corp. Dr. A.G. Osborne, Alliant Tech Operations
R.B. Lomerson, General Dynamics Systems Inc. L.E. Smith, AT&T Bell Laboratories
B. Mahler, Ohmega Technologies Inc. C. Pagel, U.S. Navy G.A. Smith, Trace Laboratories—East
P. Marcoux, PPM Associates R.E. Park Jr., Raytheon Co. V. Solberg, SCI Systems Inc.
S.R. Martell, Sonoscan Inc. S.T. Partel Jr., Motorola Inc. P.S. Speicher, U.S. Air Force
J.C. Mather, Rockwell International C. Payne, Intergraph Corp. T.K. Stewart, Speedy Circuits
J.M. Mc Creary, IBM Corp. S. Pirayesh, Compeq International J. Svensson, Ericsson Telecom
Corp. E.M. Sworzyn, Teledyne Systems Co.
G.T. Mc Kenna, Symbol
Technologies Inc. D. Pommer, I-Pak G. Theroux, Honeywell Inc.
S. Meeks Jr., Lexmark International/ R. Prasad, Intel Corp. R.T. Thompson, Loctite Corp.
IBM Corp. V.L. Quattrini H. Thrasher, Shipley Co. Inc.
G. Messner, AMP-AKZO Corp. J.T. Rates, Chip Supply Inc. R.T. Traskos, Rogers Corp.
G. Monzani, Cisel Spa C.T. Ray D. Trobough, Tektronix Inc.
J.J. Moran, Vitro Corp. R.S. Reylek, 3M Co. D.B. Tuckerman, Chip Inc.
J.H. Morton, IBM Corp. B.C. Rietdorf, Magnavox Electronic J.L. Vargo, Allen-Bradley Co.
G.C. Munie, AT&T Bell Laboratories Systems Co.
F.W. Verdi, AT&T Bell Laboratories
R. Nataraj, Pycon Inc. P.B. Rose, Martin-Marietta
N. Virmani, Paramax Systems
Electronics
F.G. Neatrour, E-Systems Inc. D.L. Wasler, Jet Propulsion Lab
R. Savage, NASA/Goddard Space
T.D. Newton, Norplex/Oak T.M. White, Boeing Aerospace &
Flight Cntr.
L.J. Nielsen, Raytheon Co. Electronics
M.A. Savrin, Kulicke & Soffa
C.K. Noddings, Microelectronics & Industries Inc. Dr. A. Wilson, Texas Instruments
Computer S. Witzman, Northern Telecom Ltd.
D. Scaff, Jet Propulsion Lab

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S.M. Nolan A.D. Wolfrum, Shipley Co. Inc.
R.A. Schenkel, Landis & Gyr
T.E. Noll, Teradyne Connections J. Wynschenk, Enthone-Omi Inc.
D.P. Schnorr, General Electric Co.
Systems

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 IPC-MC-790 July 1992

Table of Contents
Section 1 Technology Overview 5.4 Land Patterns .............................................. 63
1.0 INTRODUCTION ........................................ 1 5.5 Vias ............................................................. 63
1.1 Multichip Module Classification .................. 3 5.6 Resistors ...................................................... 63
1.2 Materials Data............................................... 6 5.7 Integrated Circuit Die (Chips) ................... 68
1.3 Advantages and Disadvantages of 5.8 Dielectrics ................................................... 68
Multichip Modules ....................................... 6 5.9 Substrates .................................................... 68
1.4 Design Cycle................................................. 6
Section 6 Wire Bond Technology
1.5 Assembly Options....................................... 10
6.0 INTRODUCTION ...................................... 73
1.6 Substrate (Interconnect Carrier) ................. 11
6.1 Design for Wire Bonding ........................... 73
1.7 Thermal Issue.............................................. 11
6.2 Components ................................................ 74
Section 2 Multichip Module General Design
6.3 Wire Bonding.............................................. 75
Considerations
2.0 INTRODUCTION ...................................... 13 Section 7 Tape Automated Bonding (TAB)
Technology
2.1 Materials ..................................................... 13
7.0 INTRODUCTION ..................................... 80
2.2 Components ................................................ 19
7.1 Inner Lead Bonding (ILB) ......................... 80
2.3 Multichip Module Design Layout.............. 22
7.2 Outer Lead Bonding (OLB) ....................... 81
2.4 Packaging and Higher-Level Assembly..... 26
2.5 Electrical Design Guidelines ..................... 29 Section 8 Flip Chip Bonding Attachment Techniques
8.0 INTRODUCTION ..................................... 87
Section 3 MCM-C Design Considerations
(Ceramic/Glass Based Materials) 8.1 Design for Flip Chip .................................. 87
3.0 INTRODUCTION ...................................... 32 8.2 Thermal Considerations.............................. 88
3.1 Layout ......................................................... 32 8.3 Interconnection ........................................... 89
3.2 Conductor Pattern ....................................... 32 8.4 Alternative to Flip-Chips............................ 89
3.3 Conductor Routing ..................................... 32
Section 9 Design for Test, Modification, and Repair
3.4 Land Patterns .............................................. 35 9.0 INTRODUCTION ..................................... 91
3.5 Wire Bonds ................................................. 35
9.1 Design for Test ........................................... 91
3.6 Vias ............................................................. 36
9.2 Design for Modification and Repair .......... 92
3.7 Resistors ...................................................... 36
9.3 Minimizing Rework/Repair ........................ 93
3.8 Substrate Requirements .............................. 40
Section 10 Environmental Protection
Section 4 MCM-L Design Considerations
(Organic Based Materials) 10.0 INTRODUCTION ..................................... 94
4.0 INTRODUCTION ...................................... 44 10.1 Conformal Coating ..................................... 94
4.1 Design Layout............................................. 44 10.2 Encapsulation .............................................. 96
4.2 Conductor Pattern ....................................... 45 10.3 Plastic Packaging ........................................ 97
4.3 Land Pattern................................................ 49 10.4 Laminated Modules (Smart Cards) ............ 98
4.4 Holes ........................................................... 54 10.5 Metal Enclosures ........................................ 98
4.5 Resistors ...................................................... 56 Section 11 Reliability Engineering Guidelines
4.6 Substrate Materials .................................... 57 11.0 INTRODUCTION ................................... 104
Section 5 MCM-D Design Considerations (Deposited 11.1 Reliability Data......................................... 104
Dielectric Films on Various Base Materials) 11.2 Reliability Definitions............................... 104
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5.0 INTRODUCTION ...................................... 61 11.3 Constant Failure Rate ............................... 105

5.1 Layout ......................................................... 61 11.4 Failure Rate of Multiple-Element
5.2 Conductor Pattern ....................................... 62 Systems ..................................................... 106
5.3 Conductor Routing ..................................... 62 11.5 Accelerated Life Testing .......................... 106

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11.6 Failure Mechanisms in MCMs................. 107 Figure 3–10 Nominal dimensions for chip mounting lands
(see Table 3–2)............................................... 37
11.7 Construction Analysis............................... 108
Figure 3–11 Wire bond land sizes and locations ............... 38
11.8 Other Reliability Tests.............................. 108
Figure 3–12 Nominal via window dimensions .................... 38
Section 12 Applications Figure 3–13 Illustration of various multilayer via designs .. 38
12.0 INTRODUCTION .................................... 109 Figure 3–14 Routing conductors through multiple
12.1 Current Applications................................. 109 dielectric layers............................................... 39
Figure 3–15 Use of a blind through-hole land.................... 39
Section 13 Reference Documents Figure 3–16 Preferred thick-film resistor configurations .... 39
13.0 REFERENCE DOCUMENTS ................. 120 Figure 3–17 Thick-film screened resistor size and
13.1 Institute for Interconnecting and location ........................................................... 39
Packaging Electronic Circuits (IPC) ........ 120 Figure 3–18 Thick-film resistor length/width/power ............ 40
13.2 Electronic Industries Association (EIA) .. 120 Figure 3–19 Preferred layout for matched thick-film
resistors .......................................................... 40
13.3 Department of Defense (DoD)................. 121
Figure 3–20 Preferred layout for trimming of thick-film
13.4 American National Standards Institute resistors .......................................................... 41
(ANSI)....................................................... 121
Figure 4–1 Etched conductor characteristics ................... 46
13.5 American Society for Testing Materials
Figure 4–2 Conductor thickness and width for internal
(ASTM)..................................................... 121
and external layers (inches) ........................... 48
Section 14 Terms and Definitions Figure 4–3 Conductor spacing optimization between
lands ............................................................... 50
14.0 Terms and Definitions .............................. 122
Figure 4–4 Large conductive layers with isothermal
conductors ...................................................... 50
Figures Figure 4–5 Examples of modified land shapes ................ 51
Figure 4–6 External annular ring ...................................... 51
Figure 1–1 Typical pin count per integrated circuit ............ 2
Figure 4–7 Internal annular ring ....................................... 51
Figure 1–2 Forecast system clock speed increase
1987–92............................................................ 3 Figure 4–8 Typical thermal relief in planes....................... 52
Figure 1–3 Price/density relationships................................ 4 Figure 4–9 Clearance area in planes, mm [in]
conductors ...................................................... 52
Figure 1–4 Interconnection density vs. line technology ..... 5
Figure 4–10 Solder resist windows..................................... 53
Figure 1–5 Expansion of Packaging Materials ................... 8
Figure 4–11 Chip resistor ................................................... 53
Figure 1–6 Conductivity of Packaging Materials ................ 8
Figure 4–12 Land patterns for rectangular chip resistors,
Figure 1–7 Methods of 3D die integration ........................ 10 mm [in]............................................................ 54
Figure 1–8 Eight-Layer MCM-L ........................................ 12 Figure 4–13 Solder fillet formation...................................... 54
Figure 2–1 Resistor paste stability ................................... 23 Figure 4–14 Etched resistor shape..................................... 57
Figure 2–2 Inductance/wire length relationships .............. 23 Figure 4–15 Dielectric layer thickness measurement......... 59
Figure 2–3 Example of total thermal resistance Figure 5–1 Sequence of events for MCM layout.............. 62
calculation ...................................................... 31
Figure 5–2 Orientation for conductor-resistor patterns..... 62
Figure 2–4 Thermal resistance during heat spreading ... 31
Figure 5–3 Land and conductor geometries..................... 63
Figure 3–1 Sequence of events for MCM layout.............. 32
Figure 5–4 Nominal thin-film conductor and land
Figure 3–2 Final configuration of MCM-C using wire dimensions (see Table 5-3) ............................ 64
bonding ........................................................... 33
Figure 5–5 Nominal dimensions for chip mounting
Figure 3–3 Orientation for conductor-resistor patterns..... 34 lands (see Table 5-4)...................................... 65
Figure 3–4 Land and conductor geometries..................... 34 Figure 5–6 Exit land/alignment/misalignment
Figure 3–5 Conductor interconnects external to the considerations................................................. 65
dielectric.......................................................... 35 Figure 5–7 Recommended approach for identifying
Figure 3–6 Spacing between adjacent conductors exit leads/pins for standard packages............ 66
running over a dielectric edge........................ 35 Figure 5–8 Nominal thin-film resistor design dimension
Figure 3–7 Preferred parallel conductor design running (see Table 5-5) ............................................... 67
over a dielectric edge ..................................... 35 Figure 5–9 Nominal thin-film resistor dimensions
showing resistor-to-conductor spacing
Figure 3–8 Overlap between top and bottom conductors
(see Table 5-5) ............................................... 67
over a dielectric edge ..................................... 35
Figure 5–10 SiO2 on silicon MCM-D substrate .................. 69
Figure 3–9 Examples of die bonds and wire bonds in
multilayer designs........................................... 35 Figure 5–11 BCB on silicon MCM-D .................................. 70
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 IPC-MC-790 July 1992

Figure 5–12 Polyimide MCM-D on copper (or aluminum) Figure 12–13 Rockwell 5-million-instruction-per-second
base ................................................................ 70 dual processor on a silicon substrate,
Figure 5–13 Polyimide MCM-D on ceramic........................ 71 25-micrometer lines, and four metalization
layers. ........................................................... 115
Figure 6–1 Wire bonding guidelines ................................. 73
Figure 12–14 An example of an inexpensive MCM-L ........ 116
Figure 6–2 Ball bonding layout features........................... 73
Figure 12–15 An example of an MCM-C, which is
Figure 6–3 Mechanics of ultrasonic wire bonding ............ 77 termed by some ‘‘a conventional thick-film
Figure 6–4 Hydrogen torch flame-off shown with hybrid’’ — Fujitsu .......................................... 116
electrostatic ball for application ...................... 78 Figure 12–16 ADC574P converter ...................................... 117
Figure 6–5 Typical ball bonding cycle .............................. 79 Figure 12–17 Advanced packaging systems ...................... 118
Figure 7–1 Excising of leaded die from tape carrier ........ 80 Figure 12–18 T.I. ................................................................. 118
Figure 7–2 TAB mounting options .................................... 82 Figure 12–19 Irvine Sensors Corp...................................... 119
Figure 7–3 Solder reflow................................................... 82
Figure 7–4 Single point TAB bonding wedge ................... 83
Tables
Figure 7–5 Laser augmented thermosonic TAB
bonding tool .................................................... 84 Table 1–1 Characterization of Selected MCM Market
Figure 7–6 Trapezoidal trench TAB lead bonding tool ..... 84 Segments ............................................................ 1
Figure 7–7 Deep narrow groove waffle pattern TAB Table 1–2 Multichip Interconnect Attributes by
bonding tool tip ............................................... 85 Classification Multichip Modules ......................... 7
Figure 7–8 In-line and cross TAB lead bonding tool ........ 86 Table 1–3 General Multichip Material Properties................. 7
Figure 7–9 In-line and cross TAB lead bonding tool ........ 86 Table 1–4 End Use Environments ....................................... 9
Figure 8–1 Typical flip chip ............................................... 87 Table 2–1 Conductor System Attributes ............................ 15
Figure 8–2 The IBM ‘‘Thermal Conduction Module’’ ........ 88 Table 2–2 Film Resistor Characteristics ............................ 16
Figure 8–3 Beam leaded IC wafer.................................... 89 Table 2–3 Dielectric Comparisons ..................................... 16
Figure 8–4 Individual beam-leaded IC.............................. 89 Table 2–4 Typical Solder Systems..................................... 17
Figure 8–5 Beams welded to substrate............................ 89 Table 2–5 Properties of Adhesives .................................... 19
Figure 8–6 Micro SMT package–cross sectional view ..... 90 Table 2–6 Derating Guidelines........................................... 21
Figure 8–7 Micro SMT package–added metallized cap ... 90 Table 2–7 Ceramic As-Fired Dimensions .......................... 25
Figure 10–1 Plastic molded multichip............................... 100 Table 2–8 Dimensional Tolerance...................................... 25
Figure 10–2 Multichip IC exploded view........................... 100 Table 2–9 Typical Materials Thermal Conductivity ............ 27
Figure 10–3 Matrix of substrates ...................................... 101 Table 3–1 Dimensional Constraints for Thick-Film
Figure 11–1 Exponential failure rate distribution .............. 105 Conductors and Lands...................................... 34
Figure 11–2 Typical ‘‘bathtub’’ failure curve for Table 3–2 Chip Mounting Lands ........................................ 36
electrical components................................... 105 Table 3–3 Interconnection Technique Substrate
Figure 12–1 Technology life chart..................................... 109 Temperatures .................................................... 38
Figure 12–2 DEC multichip module .................................. 110 Table 3–4 Nonphysical Substrate Selection Criteria ......... 41
Figure 12–3 Dow............................................................... 112 Table 3–5 Physical Characteristics of Substrates ............. 42
Figure 12–4 MCC.............................................................. 112 Table 4–1 Typical Values to Be Added or Subtracted
Figure 12–5 Unistructure—A flexible leaded component from the Desired Nominal Conductor Width..... 47
packs two megabytes of memory into the Table 4–2 Electrical Conductor Spacing............................ 49
area of one 256K chip. ................................. 113
Table 4–3 Conductor Width Tolerances mm [in]................ 49
Figure 12–6 Advanced packaging system........................ 113
Table 4–4 Minimum Standard Fabrication Allowance........ 50
Figure 12–7 Memory module—NEC................................. 114
Table 4–5 Annular Rings (Minimum) ................................. 51
Figure 12–8 AT&T ............................................................. 114
Table 4–6 Minimum Hole Location Tolerances.................. 54
Figure 12–9 Prototype fiber optic transmitter ................... 114
Table 4–7 Plated-Through Hole Aspect Ratios.................. 55
Figure 12–10 Z-systems. MCM designed for avionics
computer, with diffused components in Table 4–8 Minimum Plated-Through Hole ......................... 55
silicon substrate and PGA package. ............ 115 Table 4–9 Minimum Drilled Hole Size................................ 55
Figure 12–11 Polycon silicon-on-silicon MCM designed Table 4–10 Minimum Drilled Hole Size for Buried Vias ...... 56
for military application, using BCB dielectric
Table 4–11 Minimum Drilled Hole Size................................ 56
and aluminum metalization........................... 115
Table 4–12 Clad Laminate Maximum Operating
Figure 12–12 Simple MCM utilizing four chips and
Temperatures .................................................... 58
TAB technology. Package sealing is
accomplished with seam or laser welding.... 115 Table 4–13 Guide to Laminate Thickness ........................... 59
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Table 4–14 Copper Foil/Film Requirements ........................ 60 Table 10–4 Electrical Properties of Encapsulating
Table 4–15 Metal Core Substrates ...................................... 60 and Coating Materials ....................................... 99

Table 5–1 MCM-D Material and Conductor Fabrication Table 10–5 Sealing Method Hermeticity ............................ 101
Options .............................................................. 61 Table 10–6 Mechanical Properties of Enclosure
Table 5–2 Electrical Characteristics................................... 62 Materials.......................................................... 102

Table 5–3 Dimensional Constraints for Thin-film Table 10–7 Thermal Properties of Enclosure Materials .... 102
Conductors and Lands...................................... 63 Table 10–8 Physical Properties of Materials ..................... 102
Table 5–4 Chip Mounting Lands ........................................ 64 Table 10–9 Viable Package Materials ............................... 103
Table 5–5 Nominal Dimensions for Thin-Film Resistors ... 66 Table 11–1 MCM Circuit Element Base Failure Rates
Table 5–6 Properties of Dielectric Substrate Materials ..... 69 (%/1000 hr) ..................................................... 107

Table 6–1 Aluminum and Gold Wire Sizes and Ratings ... 74 Table 11–2 Statistical Factors for a 90% Lower
Confidence Limit ............................................. 107
Table 6–2 Wire Bonding Comparisons .............................. 76
Table 11–3 Comparative Failure Rates for Various
Table 9–1 Typical Functional Test Status .......................... 92 Bonding Techniques (%/1000 hr).................... 108
Table 10–1 Coating Thickness............................................. 94 Table 12–1 Chip-mounting Specs of Four Major
Table 10–2 Thermal Properties of Encapsulating................ 97 Mainframes ...................................................... 111
Table 10–3 Mechanical Properties of Encapsulating and
Coating Materials .............................................. 98
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 IPC-MC-790 July 1992

Foreword

The developments over the past 8–10 years reflected in this manufacture a single module an a 10.2 cm [4 in] substrate,
document have resulted in a variety of new materials, or four modules on a 5.1 cm [2 in] substrate. Perhaps the
structures, and interconnect methodologies. This ‘‘smorgas- answer is the latter when cost is compared to performance
bord’’ of MCM technology is shown in Figure F–1. The requirements for the system. This process of system parti-
selection of the elements that make up a structure to meet tioning may require an iteration or two following the initial
the systems level needs initially appears to be a difficult technology selection in order to develop accurate costs as
problem in the current environment. However, the choices the process of developing a module-based system
available should be viewed as part of the beauty of this progresses.
technology.
Following the development of system requirements and
Initially, system requirements should be developed on a partitioning, a specific module can be synthesized which
hierarchal basis. A simple high-level breakdown of a sys- meets the systems needs through a balancing of module
tem is shown in Figure F–2. System requirements for cost, attributes related to cost, performance, and reliability. At
reliability and performance must be clearly understood in this point, IPC-MC-790 can become a useful tool in under-
the context of the application and system environment. In standing the various module options and the relationship of
this way, requirements are logically developed and an these attributes to a potential structure. this is done through
understanding of their interrelationships can be inferred or the use of comparisons of interconnect and substrate prop-
modeled. erties, manufacturing costs and other criteria for MCM-L,
MCM-D, and MCM-C as defined in section 1 of the docu-
The complexity of an MCM structure demands the devel-
ment. Table F–1 shows these various module attributes and
opment of requirements for the structure from system level
their relative weights for these general categories.
considerations. The next step is to work with system parti-
tioning concepts that make sense in terms of system cost The selection of a general category is initially made
and performance. For example, the designer should ques- through comparing system requirements to module
tion whether it makes sense to use single chip packaging, attributes. This should be done in a quantitative fashion

MCM

Substrates Dielectric Interconnect Metalization Enclosure

Silicon Polyimide Flip-chip AI Alumina

Low K Ceramics BVBs HDI Cu AIN
AIN Silicon Wirebond Kovar
dioxide
Alumina Tab Metal Matrix
Composite
BeO Micro SMT
SIC
Glass
Organic
IPC-790-f-1

Figure F–1 MCM options

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 July 1992 IPC-MC-790

Data
Handling
System

Cost Performance Reliability

Access
Volume Weight Power Capacity Time

IPC-790-f-2

Figure F–2 Electronic system packaging hierarchy

Table F–1 Multichip Module Parameter Complexities

Thick-film Thin-film MCM-D
Parameter MCM-Circuits circuits MCM-L circuits
Performance Medium High Medium
Design flexibility, digital Medium High Medium
Analog High High Low
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Plastics Low Low Medium

Power dissipation High High Low
Frequency limit Medium High Medium
Voltage Swing Medium Medium Low
Size Small Smallest Small
Package density Medium High Medium
Reliability High High High
Circuit development time (prior to prototype) 1- 2 month 2-3 month 1 month
1:1 design transfer from bench Yes Yes Yes
Turnaround time for design change 2 weeks 4 weeks 2 weeks
Part cost, low quantity High Impractical Medium
High quantity Medium Medium Low
Cost of developing one circuit Medium High Low
Capital outlay Low Medium Low
Production setup and tooling costs Low Medium Low

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 July 1992 IPC-MC-790

Section One
Technology Overview

1.0 INTRODUCTION There is an important drive to increase density in order to

Electronic packaging continues to focus on the ever make the product smaller. Space restrictions exist in end-
increasing need for higher electrical speed and higher inter- use environments ranging from aircraft to laptop computers
connection density. In existing packaging concepts using and hand-held TVs. Another driver is the potential cost
printed board assemblies and individually packaged inte- reduction available from reduction in material usage, or
grated circuits, performance may be sacrificed because of even from less real estate being employed, as may be the
the signal path length needed to interconnect the semicon- case in telephone exchanges. Table 1–1 shows MCM selec-
ductors contained in the various packages. tion according to various market segments.

In contrast to the above, improvements in speed, reliability, The heart of electronic performance capability is the inte-
and density accompany the use of unpackaged integrated grated circuit and the increasing levels of integration being
circuit chips on fine line interconnection substrates. A func- achieved. To capitalize on IC capability, we have already
tional, packaged module exhibiting these attributes will be seen the move to surface mount packages with fine pitch
called a ‘‘Multichip Module’’ (MCM), and is the subject of I/O. For the same reason, direct attach, such as TAB, Flip-
this document. A variety of materials and techniques may Chip, and Chip-On-Board, are also becoming important
be employed in creating an MCM. In section 2.0, various interconnection techniques.
approaches are categorized, and the reader is led through a Observations indicate that when single I/C chip mounting
decision-making process to assist in the selection of the is used, a trend exists toward one package per 6.45 sq. cm.
proper MCM technology for a given set of technical [1 sq. in] of substrate compared to 0.2 to 0.5 per 6.45 per
requirements. Later sections provide detailed information sq. cm. [1 sq. in] for packaged I/Cs. Under these circum-
regarding each technology type. stances, the I/O count of the package becomes the major
The balance of this introduction discusses the drivers determinant of the interconnect density required. Figure
toward use of MCM’s, and the type of problems which 1–1 shows just how these individual IC chip I/Os are
may be resolved via MCM technology. The following key expected to increase.
point should be assimilated: total cost is minimized when While not totally separate from the density considerations,
the best technological choice is made for packaging and the issue of system speed presents some major challenges
interconnection.
Table 1–1 Characterization of Selected MCM Market Segments
Segment Drivers Personality Price Elasticity
Electronic T&M Precision Industrial Moderate
Logic Analysis Precision, Miniaturization Industrial High
Global Positioning & Miniaturization Military Moderate
Surveillance Miniaturization Commercial High
Communications Satellites Miniaturization Commercial Low
Telephone Miniaturization Commercial Very High
Smart Sensors
Weapons Systems Miniaturization Military Moderate, Low
Automotive Control Miniaturization Consumer Very High
Robotics Miniaturization Industrial Moderate
Computing Systems
Strategic/Tactical Speed Military Low
Mgmt. Info. Sys. Speed Commercial Moderate
Scientific Models Speed Industrial Low
Academic
Government
Image Processing Speed, Miniaturization Industrial Moderate
Engineering Workstations Speed Industrial Very High
Laptops/Notebooks Miniaturization Consumer Very High

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 IPC-MC-790 July 1992

Number of I/O Pins

IC 1200
G
LO SO
R I/Os
S
1000 I NG OCE
AD RO
PR
LE MIC

80486
80386

100 90
RY I/Os
MEMO
16M
80286
4M
1M DRAM

1980 1985 1990 1995 2000

IPC-790-1-1

Figure 1–1 Typical pin count per integrated circuit

to interconnect structures. Figure 1–2 shows a forecast of (X) axis is interconnect density, which is defined as total
how clock frequencies will develop during the early part of possible wiring trace length of all signal layers, per square
the 1990s: note the increasing proportion of systems with inch of substrate. Present practice, substantiated by several
operating frequencies at a level where the electrical perfor- empirical studies, indicates that actual wiring efficiency is
mance of the interconnect becomes critical. approximately 50% of theoretical. The plotting scale for
As new generations of electronic products emerge, they both axes is logarithmic. Certain areas of the graph are
surpass the capability of existing packaging and intercon- annotated to indicate the price/density relationship for
nection technology and infrastructure. This movement is selected technologies. The technologies covered range
occurring at all levels: at the IC, at the IC package, at the from single sided printed boards (low cost, low density
hybrid, the board, the connector, and even the cable which capability) in the lower left hand corner of the plot, to ICs.
ties all the systems together. Interconnection density multichip modules, and wafer scale integration (high cost,
becomes the measure of successfully managing perfor- high density capability) in the upper right hand corner.
mance and interconnect requirements. In addition, some trend lines have been inserted in the fig-
Interconnect substrate capability continues to be challenged ure to indicate price history and anticipated future trends.
by the combined effects of two interrelated movements: 1) In the mid 80s, the prices of substrates were increasing as
use of digital circuitry at the expense of analog circuitry; the square of the interconnection density. But, the plot also
and 2) continued technical progress in semiconductor pro- shows that, in response to an ‘‘experience curve’’ and gen-
cessing, which enables production of denser IC devices eral market dynamics, the Price/Density relationship is
having progressively higher interconnection demands. constantly changing. As a result, it is expected that at some
The gap between printed boards and semiconductor tech- future time, arbitrarily marked in the plot as the ‘‘1992
nology (wafer scale integration) is greater than one order of price line,’’ substrate prices will increase only linearly with
magnitude in interconnection density capability, although density. There are indications that when such a pricing state
the development of ‘‘fine-pitch’’ printed boards and assem- is reached sometime in the future the interconnections at
bly technology has narrowed the gap somewhat. higher density levels may be more economical than low
density interconnects.
Comparison of technology capability is presented in Figure
1–3. This generalized plot approximately relates price and The previous plots and discussion indicate a void in inter-
density for a wide variety of interconnect technologies, and connection density capability between present printed wir-
deserves additional discussion. Along the vertical (Y) axis, ing board technology and wafer scale integration. All
price information is normalized to cost-per-square-inch of viable efforts at filling this void utilize unpackaged inte-
interconnect substrate. The variable along the horizontal grated circuits. This avoids the space inefficiencies of
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 July 1992 IPC-MC-790

Forecast System Clock Speed Increase 1987–92

% of designs
70
1987
60 1989
1992
50

40

30

20

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10

20 or less 20-50 50-100 100 or more

Clock frequency MHz
IPC-790-1-2

Figure 1–2 Forecast system clock speed increase 1987–92

fanout and relatively bulky leads which accompany single If careful attention is paid to technical/design issues in
chip packages. The acronym ‘‘MULTICHIP MODULE’’ is combination with achievement of interconnection ‘‘density
appropriate for all technical approaches for 1) interconnect- matching,’’ many benefits may be realized, including the
ing multiple bare integrated circuits for efficient operation, following:
and for 2) interfacing to the outside world through a ‘‘next • Reduced electrical losses, resulting in improved speed
level assembly’’. With this as background, a multichip capability; fewer components (as might be needed for
module may be defined as follows: decoupling).
• Lowest cost for the required performance.
‘‘LOGICAL FUNCTIONAL BLOCKS GROUPED TO • Reduced size and weight.
MAXIMIZE INTERCONNECT WITHIN A COMPACT • Potential for reduced I/O.
ASSEMBLY, YET MINIMIZE INTERCONNECT TO
THE NEXT LEVEL.’’ It is important to recognize that several forms of multichip
technology have been in existence for a number of years,
and new approaches have been introduced recently. Among
Technologists have emphasized the applicability of Rent’s these are the following:
rule, which relates IC chip I/O count to the number of • Thick film hybrid microelectronics
functions on the chip. However, the use of Rent’s rule for • Thin film hybrid microelectronics
multichip modules or wafer scale integration is not appro- • Co-fired multilayer ceramic module
priate. Consider, for example, a television. If all the elec-
• Chip-on-board (COB)
tronics required for the TV’s operation were contained in
• Silicon-on-silicon
one MCM, only a few I/O would be required, including 1)
power cord, 2) antenna, 3) video signal out, 4) audio signal • Wafer-scale integration
out, 5) adjustment controls (e.g., on-off-volume). Other Their relative position on a density capability plot is shown
examples include the personal computer, cellular phone, in Figure 1–4.
camcorder, etc. Proper utilization of MCM technology
1.1 Multichip Module Classification Traditionally the
should reduce the need for fine-pitch package I/O.
differences among printed board assemblies, hybrid circuits
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