The Bipolar Junction Transistor (BJT)

Introduction

T
he transistor, derived from transfer resistor, is a three
terminal device whose resistance between two terminals is
controlled by the third. The term bipolar reflects the fact that
there are two types of carriers, holes and electrons which form
the currents in the transistor. If only one carrier is employed (electron
or hole), it is considered a unipolar device like field effect transistor
(FET).
The transistor is constructed with three doped semiconductor
regions separated by two pn junctions. The three regions are called
Emitter (E), Base (B), and Collector (C).
Physical representations of the two types of BJTs are shown in
Figure (1–1). One type consists of two n -regions separated by a p-region
(npn), and the other type consists of two p-regions separated by an n-
region (pnp).

Figure (1-1) Transistor Basic Structure

The outer layers have widths much greater than the sandwiched p–
or n–type layer. The doping of the sandwiched layer is also considerably
less than that of the outer layers (typically, 10:1 or less).
This lower doping level decreases the conductivity of the base
(increases the resistance) due to the limited number of “free” carriers.
Figure (1-2) shows the schematic symbols for the npn and pnp
transistors

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 Figure (1-2) standard transistor symbol

Transistor operation

Objective: understanding the basic operation of the transistor and its

naming

In order for the transistor to operate properly as an amplifier, the

two pn junctions must be correctly biased with external voltages. The
basic operation of the transistor will now be described using the npn
transistor. The operation of the pnp transistor is the same as for the
npn except that the roles of the electrons and holes, the bias voltage
polarities and current directions are all reversed.
Figure (1-3) shows both the pnp and npn transistors with the proper
DC biasing. Notice that in both cases the base-emitter junction is
forward biased and the base-collector is reverse biased

Figure (1-3) transistor forward reverse bias

Before the transistor is biased there are two depletion regions.

What is happens inside the transistor when it is forward and reverse
bias is the forward biased from the base to emitter narrows the BE
depletion region as shown in figure (1-4). This will result in a heavy flow

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of majority carriers (electrons) from the emitter to the base as
indicated by the wide arrow.

The base region is slightly doped and very thin so that it has a very
limited number of holes. Thus, only small percentage of all the electrons
flowing across the BE junction combine with the available holes. These
relatively few recombined electrons will form the small base current
(IB).

The reverse biased from base to collector widens the BC depletion

region as shown in figure (1-4). Consider the similarity between this
situation and that of the reversed biased diode. Recall that the flow of
majority carriers is zero, resulting in only a minority carriers flow. The
free electrons move through the collector region, into the external
circuit, and then return into the emitter region along with the base
current, as indicated. The emitter current is slightly greater than the
collector current because of the small base current that splits off from
the total current injected into the base region from the emitter.

Transistor currents

Applying Kirchhoff’s current law to the transistor of figure (1-4) we

obtain

𝐼𝐸 = 𝐼𝐵 + 𝐼𝐶
The collector current comprises two components

𝐼𝐶 = 𝐼𝐶 𝑚𝑎𝑗𝑜𝑟𝑖𝑡𝑦 + 𝐼𝐶𝑂 𝑚𝑖𝑛𝑜𝑟𝑖𝑡𝑦

Those for a pnp transistor notice that the arrow on the emitter
inside the transistor symbols points in the direction of conventional
current (holes current).

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 Figure (1-4) transistor operation

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Transistor Categories
Manufacturers generally classify bipolar junction transistors into
three broad categories:
1- General-Purpose/Small-Signal Transistors:- General-
purpose/small-signal transistors are generally used for low- or
medium-power amplifiers or switching circuits. Figure (1-5) show
small signal transistors.

Figure (1-5) Small Signal Transistors

2- Power Transistors: - Power transistors are used to handle large

currents (typically more than 1 A) and/or large voltages.

Figure (1-6) Examples of Power Transistors

3- RF Transistors: - RF transistors are designed to operate at

extremely high frequencies and are commonly used for various
purposes in communications systems and other high frequency
applications. Figure (1-7) show examples of RF transistors.

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 Figure (1-7) show examples of RF transistors

The DMM Diode Test Position

A digital multimeter can be used as a fast and simple way to check a

transistor. For this test, you can view the transistor as two diodes
connected as shown in Figure (1-8) for both npn and pnp transistors.

An ohmmeter or the resistance scales of DMM can be used to check

the state of the transistor. A good diode will show an extremely high
resistance (or open) with reverse bias and a very low resistance with
forward bias.
A defective open diode will show an extremely high resistance (or
open) for both forward and reverse bias.
A defective shorted or resistive diode will show zero or a very low
resistance for both forward and reverse bias.

Many digital multimeters (DMMs) have a diode test position that

provides a convenient way to test a transistor. In Figure (1-8a), the red
(positive) lead of the meter is connected to the base of an npn
transistor and the black (negative) lead is connected to the emitter to
forward-bias the base-emitter junction.
If the junction is good, you will get a reading of between
approximately 0.6 V and 0.8 V, with 0.7 V being typical for forward bias.
In Figure (1-8b), the leads are switched to reverse-bias the base-
emitter junction, as shown. If the transistor is working properly, you
will typically get an OL indication. The process just described is
repeated for the base-collector junction as shown in Figure (1-8c) and
(d).
For a pnp transistor, the polarity of the meter leads are reversed
for each test.

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Figure (1-8) Typical DMM test of a properly functioning npn transistor. Leads
are reversed for a pnp transistor.

Transistor configurations

Objective: shows the transistor connection configurations and the

difference between them
As we have seen, the bipolar transistor is a three-terminal device.
Three basic single transistor amplifier configurations can be formed;
depending on which of the three transistor terminals is used as signal
ground (i.e. which terminal is common to both the input and
the output side of the configuration). These three basic
configurations are appropriately called common emitter, common
collector (emitter follower), and common base. Figure (1-9)
shows the three basic configurations for npn transistor.

Figure (1-9) transistor configuration

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Common Emitter Configuration

Figure (1–10) shows a common-emitter configuration for pnp and

npn transistors. The common-emitter (CE) configuration has the
emitter as the common terminal, or ground, to an ac signal. VBB forward-
biases the base-emitter junction, and VCC reverse-biases the base-
collector junction. This configuration is the most frequently
encountered transistor configuration.

Figure (1-10) Common Emitter Configuration

DC Beta (βDC)

The common-emitter, forward-current, amplification factor

(or dc current gain) is the ratio of the dc collector current (IC) to the
dc base current (IB) and is designated DC Beta (βDC)
𝐼𝐶 𝐼𝐸
𝛽𝐷𝐶 = ≅
𝐼𝐵 𝐼𝐵

Typical values of 𝛽𝐷𝐶 range from less than 20 to 200 or higher. 𝛽𝐷𝐶 is
usually designated as an equivalent hybrid (h) parameter, ℎ𝐹𝐸 , on
transistor datasheets
𝛽𝐷𝐶 = ℎ𝐹𝐸
Example Determine the dc current gain 𝛽𝐷𝐶 and the emitter current 𝐼𝐸
for a transistor where 𝐼𝐵 = 50µ𝐴 and 𝐼𝐶 = 3.65 𝑚𝐴.

Two sets of characteristics are necessary to describe fully the

behavior of the common-emitter configuration: one for the output or

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collector-emitter circuit and the other for the input or base-emitter
circuit. Both are shown in Fig. (1-11).

Figure (1-11) Characteristics of a silicon transistor in the common-emitter

configuration: (a) collector characteristics; (b) base characteristics.

When the base-emitter junction is forward-biased, it is like a

forward-biased diode and has a nominal forward voltage drop of
transistor in the “on” or active region the base-to emitter voltage is 0.7
V
𝑉𝐵𝐸 = 0.7 𝑉 𝑓𝑜𝑟 𝑠𝑖𝑙𝑖𝑐𝑜𝑛 𝑎nd 0.3V for ge𝑟𝑚𝑎𝑛𝑖𝑢𝑚

There are three basic regions as indicated in the figure (1-11a). These
regions are
1- The Active region: the collector-base junction is reverse-biased,
while the base-emitter junction is forward-biased.
2- The Saturation region: the collector-base and base-emitter
junctions are forward-biased. When the base-emitter junction
becomes forward-biased and IB is increased, IC also increases and
VCE decreases as a result of more drop across the collector
resistor (VCE =VCC-ICRC). This is illustrated in Figure (1–12).
When VCE reaches its saturation value, VCE(sat), the base-
collector junction becomes forward-biased and IC can increase no
further even with a continued increase in IB. VCE(sat) for a
transistor occurs somewhere below the knee of the collector
curves, and it is usually only a few tenths of a volt.

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 Figure (1–12)

3- The cutoff region: the collector-base and base-emitter junctions

of a transistor are both reverse-biased. When IB=0, the
transistor is in the cutoff region of its operation. This is shown
in Figure (1–13). With the base lead open, resulting in a base
current of zero. Under this
condition, there is a very small
amount of collector leakage
current, ICEO, due mainly to
thermally produced carriers.
Because ICEO is extremely
small, it will usually be
neglected in circuit analysis so
that
Figure (1–13)

VCE = VCC

DC Bias

Bias establishes the dc operating point (Q-point) for proper linear

operation of an amplifier. The dc
operation of a transistor circuit can be
described graphically using a dc load
line. This is a straight line drawn on
the characteristic curves from the
saturation value where IC=IC(sat) on the
y-axis to the cutoff value where
VCE=VCC on the x-axis, as shown in
Figure (1–14).
Figure (1–14) DC load line

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 The load line is determined by the external circuit (VCC and RC), not
the transistor itself, which is described by the characteristic curves.
The region along the load line
including all points between
saturation and cutoff is generally
known as the linear region of the
transistor’s operation. As long as
the transistor is operated in this
region, the output voltage is
ideally a linear reproduction of
the input. Figure (1–15) shows an
example of the linear operation of
a transistor.
Figure (1–15)

If an amplifier is not biased with correct dc voltages on the input

and output, it can go into saturation or cutoff when an input signal is
applied. Figure (1–16) shows the effects of improper dc biasing of an
inverting amplifier.

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 Figure (1–16) Graphical load line illustration of a transistor being driven into
saturation and/or cutoff

We will now investigate how the network parameters define the

possible range of Q-points and how the actual Q-point is determined

BJT AC Equivalent Circuit

Now we begin to examine the AC response of the BJT transistor by

reviewing the models must frequently used to represent the transistor
in the sinusoidal AC domain.
One of our first concerns in the sinusoidal AC analysis of transistor
networks is the magnitude of the input signal. It will determine wither
small-signal or large-signal techniques should be applied.

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There are three modules commonly used in the small-signal AC analysis
of transistor networks
1- The re model
2- The hybrid π model
3- The hybrid equivalent model
A model is a combination of circuit elements, properly chosen, that
best approximates the actual behavior of a semiconductor device
under specific operating conditions.

It is important as you progress through the modifications of the

network to define the ac equivalent that the parameters of interest
such as Zi, Zo, Ii and Io as defined by Fig. (1-17) be carried through
properly.

Figure (1-17) Defining the

important parameters of any system

The re transistor Model for common emitter configuration

The equivalent circuit for the common-emitter configuration will be

constructed using the device characteristics and a number of
approximations. Starting with the input side, we find the applied voltage
Vi is equal to the voltage Vbe with the input current being the base
current Ib as shown in Fig. (1-18).

Figure (1-18) Finding the input equivalent

circuit for a BJT transistor.

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The characteristics for the input side appear as forward-biased diode.
For the equivalent circuit, therefore, the input side is simply a single
diode with a current Ie, as shown in Fig. (1-19).

Figure (1-19) Equivalent circuit for the input side

of a BJT transistor.

However, we must now add a component to the network that will

establish the current Ie of Fig. (1-19) using the output characteristics.
If we assume β is constant then the entire characteristics at the
output section can be replaced by a controlled source whose magnitude
is (βIb) and the equivalent network for the common-emitter
configuration becomes as shown in figure (1-20).

Figure (1-20) BJT equivalent circuit.

The equivalent model of Fig. (1-20) can be awkward to work with due to
the direct connection between input and output networks. It can be
improved by
1- replacing the diode by its equivalent resistance
26 𝑚𝑉
𝑟𝐷 = 𝑟𝑒 =
𝐼𝐸
2- the impedance seen by the base of the network is

(1 + 𝛽)𝑟𝑒

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The collector output current is still linked to the input current by 𝛽 as
shown

Figure (1-21) Improved BJT equivalent

circuit

We now have a good representation for the input circuit, but aside from
the collector output current being defined by the level of beta and IB,
we do not have a good representation for the output impedance of the
device. In any event, an output impedance can now be defined that will
appear as a resistor in parallel with the output as shown in the
equivalent circuit of Fig. (1-22) .

Figure (1-22) re model for the

common-emitter transistor
configuration including effects
of ro.

Biasing Configurations

Fixed-Bias (Base Bias) Circuits

This method of biasing is common in switching circuits. Figure (1–23)

shows a base-biased transistor. The
analysis of this circuit for the linear
region shows that it is directly
dependent on βDC. Starting with
Kirchhoff’s voltage law around the
base circuit,
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝑉𝐶𝐶 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 ⇒ 𝐼𝐵 =
𝑅𝐵

Figure (1–23)

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Kirchhoff’s voltage law applied around the collector circuit in Figure (1–
23) gives the following equation:
𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐶 = 𝛽𝐼𝐵 = 𝛽 [ ]
𝑅𝐵
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶

Load-Line Analysis

The network of Figure (1-23) establishes an output equation that

relates the variables IC and VCE in the following manner:
𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸
The output characteristics of the transistor also relate the same
two variables IC and VCE . We must now superimpose the straight line
defined by the output equation on the characteristics. The most direct
method of plotting the output equation on the output characteristics is
to use the fact that a straight line is defined by two points. If we
choose IC =0 mA and by substituting it in the output equation then
𝑉𝐶𝐶 = 0𝑅𝐶 + 𝑉𝐶𝐸
𝑉𝐶𝐸(𝑜𝑓𝑓) = 𝑉𝐶𝐶 ⃒𝐼𝑐=0
If we now choose VCE = 0 V then
𝑉𝐶𝐶
𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 0 ⇒ 𝐼𝐶(𝑠𝑎𝑡) =
𝑅𝐶
By joining the two points the straight line established by the output
equation can be drawn. The resulting line on the graph of Figure (1-24)
is called the load line since it is
defined by the load resistor RC

Figure (1-24) fixed bias load line

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AC equivalent circuit for Fixed-Bias (Base Bias) Amplifier

The first configuration to be analyzed in detail is the common-emitter

fixed-bias network of Fig. (1-25) . Note that the input signal Vi is
applied to the base of the transistor, whereas the output Vo is off the
collector. In addition, recognize that the input current Ii is not the
base current, but the source current, and the output current Io is the
collector current.

The ac equivalent of a fixed bias network is obtained by:

1. Setting all dc sources to zero and replacing them by a short-
circuit equivalent.
2. Replacing all capacitors by a short-circuit equivalent.
3. Substituting the re model for the common emitter configuration.

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4. Redrawing the network in a more convenient and logical form.
5. Place the important network parameters Zi, Zo, Ii and Io on the
redrawn network.

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Emitter-Stabilized Bias Circuit

The dc bias network of Figure (1-27) contains an emitter resistor to

improve the stability level over that of the fixed-bias configuration. To
calculate IB, you can write Kirchhoff’s voltage law (KVL) around the base
circuit
𝑉𝐶𝐶 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸
𝐼𝐸 = 𝐼𝐵 + 𝐼𝐶
𝐼𝐸 = 𝐼𝐵 + 𝛽𝐼𝐵 → 𝐼𝐸 = 𝐼𝐵 (1 + 𝛽)
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + (1 + 𝛽)𝑅𝐸

Figure (1-27) Emitter-Stabilized

There is an interesting result that can be derived from 𝐼𝐵 equation if

the equation is used to sketch a series network that would result in the
same equation we will note that the emitter resistor, which is part of
the collector emitter loop, “appears as”(1 + 𝛽)𝑅𝐸 in the base–emitter
loop.
𝑅𝑖 = (1 + 𝛽)𝑅𝐸
Writing Kirchhoff’s voltage law for the collector-emitter loop in the
clockwise direction will result in
𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 + 𝐼𝐸 𝑅𝐸
Substituting 𝐼𝐸 ≅ 𝐼𝐶 resulting in
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐸 (𝑅𝐸 + 𝑅𝐶 )
The single-subscript voltage VE is the voltage from emitter to
ground and is determined by
𝑉𝐸 = 𝐼𝐸 𝑉𝐸
While the voltage from collector to ground can be determined from
𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
𝑉𝐶 = 𝑉𝐶𝐸 + 𝑉𝐸
Or
𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
The voltage at the base with respect to ground can be determined
from
𝑉𝐵 = 𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵
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 𝑉𝐵 = 𝑉𝐵𝐸 + 𝑉𝐸
Load-Line Analysis

The collector–emitter loop equation that defines the load line is the
following
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐸 (𝑅𝐸 + 𝑅𝐶 )
The collector saturation level or maximum collector current for an
emitter-bias design can be determined by apply a short circuit between
the collector–emitter terminals (VCE=0) gives
VCC
IC(sat) =
RC + RE
The maximum collector-emitter voltage can be determined by
applying (IC=0) gives
VCE(off) = VCC

The resulting load line for the emitter

bias design is shown in figure (1-28)

Figure (1-28) Emitter bias load line

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AC Analysis of Emitter-Stabilized Bias Amplifier Circuit

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VOLTAGE-DIVIDER BIAS

In the previous bias configurations the bias current ICQ and voltage
VCEQ were a function of the current gain (β) of the transistor.
However, since β is temperature sensitive, especially for silicon
transistors, and the actual value of beta is usually not well defined, it
would be desirable to develop a bias circuit that is independent of the
transistor beta. The voltage-divider bias configuration of Figure (1-19)
is such a network. A dc bias voltage at the base of the transistor can be
developed by a resistive voltage divider
that consists of R1 and R2, as shown in
Figure (1–31).
There are two methods that can be
applied to analyze the voltage divider
configuration.
1. the exact method
2. the approximate method

Figure (1–31).

Exact Analysis

The input side of the network of Figure (1-30) can be redrawn as

shown in Figure (1-31) for the d analysis. Apply

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 Thevenin’s theorem to the circuit left of point B, with VCC replaced
by a short to ground and the transistor disconnected from the circuit.
The voltage at point B with respect to ground is

Figure (1-31)

𝑅2
𝐸𝑇ℎ = 𝑉𝐶𝐶 [ ]
𝑅1 + 𝑅2

And the resistance is

𝑅1 𝑅2
𝑅𝑇ℎ = [ ]
𝑅1 + 𝑅2

The Thévenin network is then redrawn

as shown in Figure (1-32), and IBQ can be
determined by first applying Kirchhoff’s
voltage law

𝐸𝑇ℎ = 𝐼𝐵 𝑅𝑇ℎ + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸

Figure (1-32) Inserting the Thévenin equivalent

Substituting 𝐼𝐸 = (1 + 𝛽)𝐼𝐵 and solving for IB yields

𝐸𝑇ℎ − 𝑉𝐵𝐸
𝐼𝐵 = [ ]
𝑅𝑇ℎ + (1 + 𝛽)𝑅𝐸
The remaining quantities of the network can be found in the same
manner as developed for the emitter-bias configuration. That is,
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐸 (𝑅𝐸 + 𝑅𝐶 )

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Approximate Analysis

The input section of the voltage-divider configuration can be

represented by the network of Figure (1-33).
The reflected resistance between base and emitter is defined by

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 𝑅𝑖 = (1 + 𝛽)𝑅𝐸

Figure (1-33)

If 𝑅𝑖 is much larger than the resistance 𝑅2 (𝑅𝑖 ≥ 10𝑅2 ), the loading

effect of the base current can be ignored so the current IB will be much
smaller than I2 (current always seeks the path of least resistance) and I2
will be approximately equal to I1. If we accept the approximation that IB
is essentially zero amperes compared to I1 or I2, then I1=I2 and R1 and R2
can be considered series components. The voltage across R2, which is
actually the base voltage, can be determined using the voltage-divider
rule
𝑉𝐶𝐶 𝑅2
𝑉𝐵 = [ ]
𝑅1 + 𝑅2

And the complete analysis will be as following

𝑉𝐸 = 𝑉𝐵 − 𝑉𝐵𝐸
𝐼𝐸 = 𝑉𝐸 ⁄𝑅𝐸
𝐼𝐶𝑄 ≅ 𝐼𝐸

The collector-to-emitter voltage is determined by

𝑉𝐶𝐸𝑄 = 𝑉𝐶𝐶 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )
Note that the Q-point (as determined by ICQ and VCEQ) is independent
of the value of β
Load-Line Analysis

The similarities with the output circuit of the emitter-biased

configuration result in the same intersections for the load line of the
voltage-divider configuration. The load line will therefore have the same
appearance as that of Figure (1-28), with
𝑉𝐶𝐶
𝐼𝐶(𝑠𝑎𝑡) = ( )
𝑅𝐶 + 𝑅𝐸
𝑉𝐶𝐸(𝑜𝑓𝑓) = 𝑉𝐶𝐶

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AC Analysis of Voltage Divider Configuration

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Collector Feedback Bias

An improved level of stability can also be obtained by introducing a

feedback path from collector to base as shown in Figure (1-36). The
negative feedback creates an “offsetting” effect that tends to keep
the Q-point stable. If IC tries to increase, it drops more voltage across
RC, thereby causing VC to decrease.

Figure (1-36) dc bias circuit with voltage

feedback.

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 When VC decreases, there is a decrease in voltage across RB, which
decreases IB. The decrease in IB produces less IC which, in turn, drops
less voltage across RC and thus offsets the decrease in VC. Writing
Kirchhoff’s voltage law around the base–emitter loop will result in
𝑉𝐶𝐶 = 𝐼𝐶′ 𝑅𝐶 + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸

𝐼𝐶′ = 𝐼𝐶 + 𝐼𝐵 ≅ 𝐼𝐶 ≅ 𝛽𝐼𝐵 ≅ 𝐼𝐸

Gathering terms, we have

𝑉𝐶𝐶 = 𝑉𝐵𝐸 + 𝐼𝐵 𝑅𝐵 + 𝛽𝐼𝐵 (𝑅𝐶 + 𝑅𝐸 )

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 = ( )
𝑅𝐵 + 𝛽(𝑅𝐶 + 𝑅𝐸 )

The feedback path results in a reflection of the resistance RC back

to the input circuit, much like the reflection of RE.
Applying Kirchhoff’s voltage law around the collector–emitter loop
for the network of Figure (1-34) will result in
𝑉𝐶𝐶 = 𝐼𝐶′ 𝑅𝐶 + 𝑉𝐶𝐸 + 𝐼𝐸 𝑅𝐸
𝐼𝐶′ ≅ 𝐼𝐶 ≅ 𝐼𝐸
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )
Which is exactly as obtained for the emitter-bias and voltage-
divider bias configurations.

Load line analysis

Continuing with the approximation 𝐼𝐶′ ≅ 𝐼𝐶 ≅ 𝐼𝐸 will result in the same

load line defined for the voltage-divider and emitter-biased
configurations. The load line will therefore have the same appearance as
that of Figure (1-28), with
𝑉𝐶𝐶
𝐼𝐶(𝑠𝑎𝑡) = ( )
𝑅𝐶 + 𝑅𝐸
𝑉𝐶𝐸(𝑜𝑓𝑓) = 𝑉𝐶𝐶

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AC Analysis of Collector Feedback Configuration

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Common-Collector Configuration

The second transistor configuration is the common-collector

configuration. The common-collector (CC) amplifier is usually referred
to as an emitter-follower (EF). The common-collector configuration is
used primarily for impedance-matching purposes since it has a high
input impedance and low output impedance.
The input current is the same for both the common-emitter and
common collector characteristics. The horizontal voltage axis for the
common-collector configuration is obtained by simply changing the sign
of the collector-to-emitter voltage of the common-emitter
characteristics. Finally, there is an almost unnoticeable change in the
vertical scale of IC of the common-emitter characteristics if IC is
replaced by IE for the common-collector characteristics (since α=1). For
the input circuit of the common-collector configuration the common-
emitter base characteristics are sufficient for obtaining the required
information.
Emitter Follower Biasing

An emitter-follower circuit with

voltage-divider bias is shown in Figure (1–
39). Notice that the input signal is
capacitively coupled to the base, the
output signal is capacitively coupled from
the emitter, and the collector is at ac
ground.

Figure (1–39) Emitter-follower with voltage-divider bias.

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AC Analysis of Common Collector Configuration

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Common Base Configuration

In figure (1-44) the npn transistor is shown in common base (CB)

configuration. The common base terminology derived from the fact that
the base is common to both the input and output sides of the
configuration. In addition, the base is usually the terminal closest to, or
at, ground potential.

Figure (1-44) common base configuration for npn

transistor

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To fully describe the behavior of the common base amplifier of figure
(1-44) requires two sets of characteristics one for the deriving point or
input parameters and the other for the output side.

The input set for the common base amplifier as shown in figure (1-45)
relates an input current (IE) to input voltage (VBE) for various levels of
output voltage (VCB).

The effect of (VCB) in the input characteristics is because the

increasing of (VCB) will increase the width of the depletion region at the
output junction diode. This decrease in the depletion region will less
chance for recombination within the base region so that (IE and also IC)
will increase.

Figure (1-45) input characteristics for npn

transistor

The curves of figure (1-46) are known as the

output or collector characteristics. There are three basic regions as
indicated in the figure. These regions are

4- The Active region: the collector-base junction is reverse-biased,

while the base-emitter junction is forward-biased.
5- The Saturation region: the collector-base and base-emitter
junctions are forward-biased
6- The cutoff region: the
collector-base and base-
emitter junctions of a
transistor are both reverse-
biased

Figure (1-46) collector characteristics

for npn transistor

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When IE =0 the collector current is simply that due to the reverse
saturation current ICO The notation most frequently used for ICO on
data and specification sheets is ICBO . Note in Fig. (1-28) that as IE
increases above zero, IC increases to a magnitude essentially equal to
that of IE
𝐼𝐶 ≅ 𝐼𝐸
As inferred by its name, the cutoff region is defined as that region
where Ic=0 A. The ratio of the dc collector current (IC) to the dc
emitter current (IE) is the dc alpha 𝛼𝐷𝐶
𝑰𝑪
𝜶𝑫𝑪 =
𝑰𝑬

Typically, values of 𝛼𝐷𝐶 range from 0.95 to 0.99 or greater, but

𝛼𝐷𝐶 is always less than 1.

Common base biasing

A typical common base biasing configuration appears in figure (1-47).

Note that two supplies are used in this configuration and the base is
the common terminal between the input emitter terminal and the output
collector terminal.

Figure (1-47) common base

configuration

Applying KVL for the input loop will result in

𝑉𝐸𝐸 = 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸
𝑉𝐸𝐸 − 𝑉𝐵𝐸
𝐼𝐸 = ( )
𝑅𝐸
Applying KVL to the entire outside perimeter of the network of
figure (1-29) will result in
𝑉𝐶𝐶 + 𝑉𝐸𝐸 = 𝐼𝐸 𝑅𝐸 + 𝑉𝐶𝐸 + 𝐼𝐶 𝑅𝐶
𝑉𝐶𝐸 = 𝑉𝐶𝐶 + 𝑉𝐸𝐸 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )

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VCB can be found by applying KVL to the output loop
𝑉𝐶𝐵 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶

AC Analysis of Common Base Configuration

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Miscellaneous Bias Configurations

There are a number of BJT bias configurations that do not match

the basic mold of those analyzed in the previous sections.

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Transistor Datasheet

A partial datasheet for the 2N3904 npn transistor is shown in Figure

(1–50). Most specification sheets are broken down into maximum
ratings, thermal characteristics, and electrical characteristics.
The electrical characteristics are further broken down into “on,” “off,”
and small-signal characteristics. The “on” and “off” characteristics
refer to dc limits, while the small signal characteristics include the
parameters of importance to ac operation.
Notice that the maximum collector-emitter voltage (VCEO) is 40 V. The
CEO subscript indicates that the voltage is measured from collector (C)
to emitter (E) with the base open (O). In the text, we use VCE(max) for
this parameter. VCEsat varies with IC and VCE (0.2v-0.3v)
Also notice that the maximum collector current (ICmax) is 200 mA.
The maximum collector dissipation PCmax is 625mW. The derate factor
under the maximum rating specifies that the maximum rating must be
decreased 5 mW for every 1°rise in temperature above 25°C.
The 𝛽𝐷𝐶 (hFE) is specified for several values of IC. As you can see, hFE
varies with IC as we previously discussed. The collector-emitter
saturation voltage, VCE(sat) is 0.2 V maximum for IC(sat) 10 mA and increases
with the current.
Limit of operation
0 ≤ 𝐼𝐶 ≤ 200 𝑚𝐴
0.2 − 0.3 ≤ 𝑉𝐶𝐸 ≤ 40𝑉
𝐼𝐶 𝑉𝐶𝐸 ≤ 625 𝑚𝑊

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53
Figure (1-50) Partial datasheet. For a complete 2N3904 datasheet, go to
http://www.fairchildsemi.com/ds/2N%2F2N3904.pdf.Copyright

College of Electronics Engineering - Communication Engineering Dept.

Fairchild Semiconductor Corporation. Used by permission
Design Operations

The design process is one where a current and/or voltage may be

specified and the elements required to establish the designated levels
must be determined. The path toward a solution is less defined and in
fact may require a number of basic assumptions that do not have to be
made when simply analyzing a network. If the transistor and supplies
are specified, the design process will simply determine the required
resistors for a particular design. Once the theoretical values of the
resistors are determined, the nearest standard commercial values are
normally chosen and any variations due to not using the exact resistance
values are accepted as part of the design.
One of the important and useful assumption is that the voltage from
emitter to ground is typically around one-fourth to one-tenth of the
supply voltage.
1 1
𝑉𝐸 ≤ ( → ) 𝑉𝐶𝐶
4 10

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Multiple BJT Networks

Two or more amplifiers can be connected in a cascaded arrangement

with the output of one amplifier driving the input of the next. Each
amplifier in a cascaded arrangement is known as a stage. The basic
purpose of a multistage arrangement is to increase the overall voltage
gain.
Capacitively (or RC) Coupled Multistage Amplifier

As shown in figure (1-51) the collector output of the first stage is

fed directly into the base of the next stage using coupling capacitor
(CC). Capacitive coupling prevents the dc bias of one stage from
affecting that of the other but allows the ac signal to pass without
attenuation because XC=0 at the frequency of operation. The same
coupling can be used between any combinations of networks.
Substituting an open circuit equivalent for CC and other capacitors of
the network will result in tow voltage divider biasing networks so the
introduced methods of analysis can be used.

Figure (1-51) two-stage

common-emitter amplifier

Direct-Coupled Multistage Amplifiers

A basic two-stage, direct-coupled amplifier is shown in Figure (1-52).

Notice that there are no coupling or bypass
capacitors in this circuit.

Figure (1-52) A basic two-stage direct-coupled

amplifier.

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 Because of the direct coupling, this type of amplifier has a better
low-frequency response than the capacitively coupled type in which the
reactance of coupling and bypass capacitors at very low frequencies may
become excessive. The increased reactance of capacitors at lower
frequencies produces gain reduction in capacitively coupled amplifiers.
Direct-coupled amplifiers can be used to amplify low frequencies all
the way down to dc (0 Hz) without loss of voltage gain because there
are no capacitive reactances in the circuit. The disadvantage of direct-
coupled amplifiers, on the other hand, is that small changes in the dc
bias voltages from temperature effects or power-supply variation are
amplified by the succeeding stages, which can result in a significant
drift in the dc levels throughout the circuit.

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The Darlington Pair

One way to boost input resistance is to use a Darlington pair, as

shown in Figure (1-53). The collectors of two transistors are connected,
and the emitter of the first drives the base of the second.

Figure (1-53) Darlington Pair

This configuration achieves multiplication as

shown in the following steps. The emitter current
of the first transistor is
𝐼𝐸1 = 𝛽1 𝐼𝐵1
This emitter current becomes the base current for the second
transistor, producing a second emitter current of
𝐼𝐸2 = 𝛽2 𝐼𝐸1 = 𝛽1 𝛽2 𝐼𝐵1
Therefore, the effective current gain of the Darlington pair is
𝛽𝐷 = 𝛽1 𝛽2
As you have seen, 𝛽 is a major factor in determining the input
resistance of an amplifier so that the Darlington pair has a very high
input impedance which equal
𝑅𝑖𝑛 = (1 + 𝛽𝐷 )𝑅𝐸
Applying the analysis similar to what we do for the previous circuits
will result in the following equations for the base current (if there is RB
and Vcc in the circuit
𝑉𝐶𝐶 − 𝑉𝐵𝐸1 − 𝑉𝐵𝐸2
𝐼𝐵1 =
𝑅𝐵 + (1 + 𝛽𝐷 )𝑅𝐸
The currents
𝐼𝐶2 = 𝐼𝐸2 = 𝛽𝐷 𝐼𝐵1

And the DC voltage at the emitter terminal is

𝑉𝐸2 = 𝐼𝐸2 𝑅𝐸

The collector voltage of this configuration is

𝑉𝐶2 = 𝑉𝐶𝐶

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AC Analysis of Darlington Pairs

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Transistor Switching Networks

The second major application area is switching applications. When

used as an electronic switch, a BJT is normally operated alternately in
cutoff and saturation. Many digital circuits use the BJT as a switch and
inverter. The network of Figure (1-56) can be employed as an inverter in
computer logic circuitry.

Figure (1-56)

Proper design for the inversion process requires that the operating
point switch from cutoff to saturation along the load line depicted in
Figure (1-57).

Figure (1-57).

For our purpose we will assume

𝑤ℎ𝑒𝑛 𝐼𝐵 = 0𝜇𝐴 𝐼𝐶 = 𝐼𝐶𝐸𝑂 = 0𝑚𝐴
𝑉𝐶𝐸(𝑠𝑎𝑡) = 0𝑉

When 𝑉𝑖 = 5𝑉, the transistor will be “on”and the design must ensure
that the network is heavily saturated this required
𝐼𝐵 > 50𝜇𝐴
The saturation level for the collector current for the circuit of
Figure (1-32) is defined by
𝑉𝐶𝐶
𝐼𝐶(𝑠𝑎𝑡) =
𝑅𝐶
For the saturation level we must therefore ensure that the following
condition is satisfied

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 𝐼𝐶(𝑠𝑎𝑡)
𝐼𝐵 >
𝛽𝐷𝐶
For the network of Figure (1-32)
𝑉𝑖 − 𝑉𝐵𝐸 5 − 0.7
𝐼𝐵 = = = 63 𝜇𝐴
𝑅𝐵 86 𝐾
𝑉𝐶𝐶 5
𝐼𝐶(𝑠𝑎𝑡) = = ≅ 6.1 𝑚𝐴
𝑅𝐶 0.82 𝐾
Testing the condition
𝐼𝐶(𝑠𝑎𝑡)
𝐼𝐵 >
𝛽𝐷𝐶

6.1 𝑚𝐴
63 𝜇𝐴 > = 48.8 𝜇𝐴
125
For 𝑉𝑖 = 0𝑉 , 𝐼𝐵 = 0, 𝐼𝐶 = 0 , 𝑉𝑅𝐶 = 0 then 𝑉𝐶 = 5𝑉

Figure (1-58) illustrates the basic operation of a BJT as a switching

device. In part (a), the transistor is in the cutoff region because the
base-emitter junction is not forward-biased. In this condition, there is,
ideally, an open between collector and emitter, as indicated by the
switch equivalent. The cutoff condition will result in a resistance level
of the following magnitude:
𝑉𝐶𝐶
𝑅𝑐𝑢𝑡𝑜𝑓𝑓 =
𝐼𝐶𝐸𝑂

In part (b), the transistor is in the saturation region because the

base emitter junction and the base-collector junction are forward-
biased and the base current is made large enough to cause the collector
current to reach its saturation value. In this condition, there is, ideally,
a short between collector and emitter, as indicated by the switch
equivalent. Actually, a small voltage drop across the transistor of up to
a few tenths of a volt normally occurs, which is the saturation voltage,
VCE(sat). The result is a resistance level between the two terminals
determined by
𝑉𝐶𝐸(𝑠𝑎𝑡)
𝑅𝑠𝑎𝑡 =
𝐼𝐶(𝑠𝑎𝑡)

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 Figure (1-58)
Switching action of an
ideal transistor

Example 4.32 page 213

Maximum Transistor Ratings

A BJT, like any other electronic device, has limitations on its

operation. These limitations are stated in the form of maximum ratings
and are normally specified on the manufacturer’s datasheet. One must
simply be sure that IC ,VCE, and their product (VCE×IC ) fall into the range
appearing in the following equations
𝐼𝐶𝐸𝑂 ≤ 𝐼𝐶 ≤ 𝐼𝐶𝑚𝑎𝑥
𝑉𝐶𝐸𝑠𝑎𝑡 ≤ 𝑉𝐶𝐸 ≤ 𝑉𝐶𝐸𝑚𝑎𝑥
𝑉𝐶𝐸 𝐼𝐶 ≤ 𝑃𝐶𝑚𝑎𝑥

Bias Stabilization

The stability of a system is a measure of the sensitivity of a

network to variations in its parameters. In any amplifier employing a
transistor the collector current IC is sensitive to each of the following
parameters:
 𝜷: Increases with increase in temperature
 |𝑽𝑩𝑬 |: decreases about 2.5 mV per degree Celsius (°C) increase
in temperature.
 ICO (reverse saturation current): doubles in value for every
10°C increase in temperature.
Any or all of these factors can cause the bias point to drift from
the designed point of operation.

Stability Factors, S(ICO), S(VBE), and S(β):

S(ICO) : The rate of change of the collector current (IC) with

respect to the leakage current (ICO) at a constant input voltage (VBE)
and amplification factor (β).

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 ∆𝐼𝐶
𝑆(𝐼𝐶𝑂 ) =
∆𝐼𝐶𝑂

As you see before IC is comprised of two components: the majority

and minority carriers. The minority current component is called the
leakage current and is given the symbol ICO .

IC = ICMajorty + ICOMinority

IC = βIB + (1 + β)ICO

The derivative of above equation to IC give us:

∂IB ∂ICO
1=β + ( 1 + β)
∂IC ∂IC

𝛛𝐈𝐂 ( 𝟏 + 𝛃)
𝐒𝐈𝐂𝐎 = =
𝛛𝐈𝐂𝐎 𝟏 − 𝛃(𝛛𝐈𝐁 ⁄𝛛𝐈𝐂 )

The last equation can be used for calculating the stability factor
(𝐒𝐈𝐂𝐎 ) for any biasing configuration.

S(VBE) : The rate of change of the collector current (IC) with respect
to the input voltage (VBE) at a constant leakage current (ICO) and
amplification factor (β).

∆𝐼𝐶
𝑆(𝑉𝐵𝐸 ) =
∆𝑉𝐵𝐸

S(VBE) : The rate of change of the collector current (IC) with respect
to the amplification factor (β) at a constant input voltage (VBE)
leakage current (ICO) and.

∆𝐼𝐶 IC1
𝑆(𝛽) = = S
∆𝛽 β1 β2 ICO2

Networks that are quite stable and relatively insensitive to

temperature variations have low stability factors. The higher the
stability factor, the more sensitive is the network to variations in that
parameter.

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 The total change in the collector current due to the three stability
factors can be determined using the following equation:

∑𝛛𝐈𝐂 = 𝐒𝐈𝐂𝐎𝐨 × 𝛛𝐈𝐂𝐎 + 𝐒𝐕𝐁𝐄𝐨 × 𝛛𝐕𝐁𝐄 + 𝐒𝛃 × 𝛛𝛃

For the fixed bias configuration shown in figure (1-37)

Applying KVL for the input circuit

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
∂IB
=0
∂IC
So
𝛛𝐈𝐂
𝐒𝐈𝐂𝐎 = =𝟏+𝛃
𝛛𝐈𝐂𝐎

Figure (1-37)

𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐶 = 𝛽𝐼𝐵 = 𝛽
𝑅𝐵
∆𝑰𝑪 −𝜷
𝑺(𝑽𝑩𝑬 ) = =
∆𝑽𝑩𝑬 𝑹𝑩

∆𝑰𝑪 𝐈𝐂𝟏 𝐈𝐂𝟏 𝐈𝐂𝟏

𝑺(𝜷) = = 𝐒𝐈𝐂𝐎𝟐 = 𝛃𝟐 =
∆𝜷 𝛃𝟏 𝛃𝟐 𝛃𝟏 𝛃𝟐 𝛃𝟏

For emitter bias configuration

𝑉𝐶𝐶 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸
𝐼𝐸 = 𝐼𝐵 + 𝐼𝐶

𝑉𝐶𝐶 = 𝐼𝐵 (𝑅𝐵 + 𝑅𝐸 ) + 𝑉𝐵𝐸 + 𝐼𝐶 𝑅𝐸

𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝐼𝐶 𝑅𝐸
𝐼𝐵 =
𝑅𝐵 + 𝑅𝐸

∂IB −𝑅𝐸
=
∂IC 𝑅𝐵 + 𝑅 𝐸
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 𝛛𝐈𝐂 (𝟏 + 𝛃) (𝟏 + 𝛃)
𝐒𝐈𝐂𝐎 = = =
𝛛𝐈𝐂𝐎 𝟏 − 𝛃(𝛛𝐈𝐁 ⁄𝛛𝐈𝐂 ) 𝟏 + 𝛃 ( 𝑹𝑬 )
𝑹𝑩 + 𝑹𝑬

𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝐼𝐶 𝑅𝐸
𝐼𝐶 = 𝛽𝐼𝐵 = 𝛽
𝑅𝐵 + 𝑅𝐸

∆𝑰𝑪 −𝜷
𝑺(𝑽𝑩𝑬 ) = =
∆𝑽𝑩𝑬 𝑹𝑩 + (𝟏 + 𝜷)𝑹𝑬

𝛛𝐈𝐂 (𝟏 + 𝜷𝟐 ) (𝟏 + 𝜷𝟐 )
𝐒𝐈𝐂𝐎𝟐 = = =
𝛛𝐈𝐂𝐎𝟐 𝟏 − 𝜷𝟐 (𝛛𝐈𝐁 ⁄𝛛𝐈𝐂 ) 𝟏 + 𝜷 ( 𝑹𝑬 )
𝟐 𝑹 +𝑹
𝑩 𝑬

∆𝑰𝑪 𝐈𝐂𝟏
𝑺(𝜷) = = 𝐒
∆𝜷 𝛃𝟏 𝛃𝟐 𝐈𝐂𝐎𝟐
H.W Derive the expressions of (𝐒𝐈𝐂𝐎 ) for voltage divider bias
configuration.

For collector feedback biasing circuit

𝑉𝐶𝐶 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + (𝐼𝑐 + 𝐼𝐵 )𝑅𝐶

𝑉𝐶𝐶 = 𝐼𝐵 (𝑅𝐵 + 𝑅𝑐 ) + 𝑉𝐵𝐸 + 𝐼𝐶 𝑅𝐶

𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝐼𝐶 𝑅𝐶
𝐼𝐵 =
𝑅𝐵 + 𝑅𝐶

∂IB −𝑅𝐶
=
∂IC 𝑅𝐵 + 𝑅𝐶

𝛛𝐈𝐂 (𝟏 + 𝛃) (𝟏 + 𝛃)
𝐒𝐈𝐂𝐎 = = =
𝛛𝐈𝐂𝐎 𝟏 − 𝛃(𝛛𝐈𝐁 ⁄𝛛𝐈𝐂 ) 𝟏 + 𝛃 ( 𝑹𝑪 )
𝑹𝑩 + 𝑹𝑪

𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝐼𝐶 𝑅𝐶
𝐼𝐶 = 𝛽𝐼𝐵 = 𝛽
𝑅𝐵 + 𝑅𝐶

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 ∆𝑰𝑪 −𝜷
𝑺(𝑽𝑩𝑬 ) = =
∆𝑽𝑩𝑬 𝑹𝑩 + (𝟏 + 𝜷)𝑹𝑪

𝛛𝐈𝐂 (𝟏 + 𝛃𝟐 ) (𝟏 + 𝛃𝟐 )
𝐒𝐈𝐂𝐎𝟐 = = =
𝛛𝐈𝐂𝐎 𝟏 − 𝛃𝟐 (𝛛𝐈𝐁 ⁄𝛛𝐈𝐂 ) 𝟏 + 𝛃 ( 𝑹𝑪 )
𝟐 𝑹 +𝑹
𝑩 𝑪

∆𝑰𝑪 𝐈𝐂𝟏
𝑺(𝜷) = = 𝐒
∆𝜷 𝛃𝟏 𝛃𝟐 𝐈𝐂𝐎𝟐

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 The Field Effect Transistor (FET)
The field-effect transistor (FET) is a three-terminal device used for a
variety of applications that match, to a large extent, those of the BJT
transistor. The BJT transistor is a current-controlled device, whereas
the FET transistor is a voltage-controlled device. The FET is a unipolar
device depending solely on either electron (n-channel) or hole (p-
channel) conduction.
The most important characteristics of the FET is
1- Its high input impedance. FETs are more temperature stable than
BJTs.
2- FETs are usually smaller than BJTs, making them particularly
useful in integrated-circuit (IC) chips.
There are three types of FETs:

n-Channel
JFET
P-Channel
n-Channel
FET

MOSFET
P-Channel
n-Channel
EMOSFET
P-Channel
MOSFETs are further broken down into depletion type and
enhancement type.
The Junction Field Effect Transistor (JFET)

Construction and Characteristics of JFETS

Figure (2-1) shows the basic structure of an n-channel JFET
(junction field-effect transistor). Wire leads are connected to each end
of the n-channel; the drain is at the upper end, and the source is at the
lower end. Two p-type regions are diffused in the n-type material to
form a channel, and both p-type regions are connected to the gate lead.

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 The result is a depletion region at
each junction, as shown in Figure (2-1)
that resembles the same region of a
diode under no-bias conditions. Recall
also that a depletion region is void of
free carriers and is therefore unable to
support conduction.

Figure (2-1) Junction field-effect transistor

Basic Operation of JFET

To illustrate the operation of a JFET, Figure (2–2) shows dc bias
voltages applied to an n-channel device. VDD provides a drain-to-source
voltage and supplies current from drain to source. VGG sets the
reverse-bias voltage between the gate and the source, as shown. The
JFET is always operated with the gate-source pn junction reverse-
biased. Reverse biasing of the gate-source junction with a negative
gate voltage produces a depletion region along the pn junction, which
extends into the n channel and thus increases its resistance by
restricting the channel width.
The channel width and thus the channel resistance can be controlled
by varying the gate voltage, thereby
controlling the amount of drain current,
ID. Figure (2–3) illustrates this concept.
The white areas represent the depletion
region created by the reverse bias. It is
wider toward the drain end of the channel
because the reverse-bias voltage between
the gate and the drain is greater than that
between the gate and the source.
Figure (2-2) A biased n-channel JFET.

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 Figure (2-3) Effects of VGS on channel width, resistance, and drain current
(VGG =VGS).

JFET Symbols
The schematic symbols for both n-channel and p-channel JFETs are
shown in Figure (2–4). Notice that the arrow on the gate points “in” for
n channel and “out” for p channel.

Figure (2-4) JFET schematic

symbols

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JFET Characteristics and Parameters
Drain Characteristic Curve
Consider the case when the gate-to-source voltage is zero (VGS=0
V). As VDD (and thus VDS) is increased from 0 V, ID will increase
proportionally, as shown in the graph of Figure (2–5b) between points A
and B .In this area, the channel resistance is essentially constant
because the depletion region is not large enough to have significant
effect. This is called the Ohmic region because VDS and ID are related
by Ohm’s law. At point B in Figure (2–5b), the curve levels off and
enters the active region where ID becomes essentially constant. As
VDS increases from point B to point C, the reverse-bias voltage from
gate to drain (VGD) produces a depletion region large enough to offset
the increase in VDS, thus keeping ID relatively constant.
Pinch-Off Voltage: For VGS 0 V, the value of VDS at which ID
becomes essentially constant (point B on the curve in Figure 2–5(b)) is
the pinch-off voltage, VP. For a given JFET, VP has a fixed value. As you
can see, a continued increase in VDS above the pinch-off voltage
produces an almost constant drain current. This value of drain current
is IDSS (Drain to Source current with gate Shorted) and is always
specified on JFET datasheets. IDSS is the maximum drain current that
a specific JFET can produce regardless of the external circuit, and it is
always specified for the condition, VGS 0 V.

Figure (2-5)The drain characteristic curve of a JFET for VGS 0 showing pinch-
off voltage.

Breakdown: As shown in the graph in Figure 2–5(b), breakdown occurs at

point C when ID begins to increase very rapidly with any further
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increase in VDS. Breakdown can result in irreversible damage to the
device, so JFETs are always operated below breakdown and within the
active region (constant current) (between points B and C on the graph).
The JFET action that produces the drain characteristic curve to the
point of breakdown for VGS = 0 V is illustrated in Figure 2–6.

Figure 2-6 JFET action that produces the characteristic curve for VGS 0 V.

VGS Controls ID
Let’s connect a bias voltage, VGG, from gate to source as shown in
Figure 2–7(a). As VGS is set to increasingly more negative values by
adjusting VGG, a family of drain characteristic curves is produced, as
shown in Figure 2–7(b). Notice that ID decreases as the magnitude of
VGS is increased to larger negative values because of the narrowing of
the channel. Also notice that, for each increase in VGS, the JFET
reaches pinch-off (where constant current begins) at values of VDS
less than VP. The term pinch-off is not the same as pinch-off voltage,
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Vp. Therefore, the amount of drain current is controlled by VGS, as
illustrated in Figure 2–8.

Figure 2-7 Pinch-off occurs at a lower VDS as VGS is increased to more

negative values.

Cutoff Voltage
The value of VGS that makes ID approximately zero is the cutoff
voltage, VGS(off), as shown in Figure 2–8(d). The JFET must be
operated between VGS 0 V and VGS(off). For this range of gate-to
source voltages, ID will vary from a maximum of IDSS to a minimum of
almost zero

Figure 2-8 VGS controls ID.

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 As you have seen, for an n-channel JFET, the more negative VGS is,
the smaller ID becomes in the active region. When VGS has a
sufficiently large negative value, ID is reduced to zero. This cutoff
effect is caused by the widening of the depletion region to a point
where it completely closes the channel, as shown in Figure 2–9.

Figure 2-9 JFET at cutoff

Comparison of Pinch-Off Voltage and Cutoff Voltage

As you have seen, there is a difference between pinch-off and
cutoff voltages. There is also a connection. The pinch-off voltage VP is
the value of VDS at which the drain current becomes constant and equal
to IDSS and is always measured at VGS=0 V. However, pinch-off occurs
for VDS values less than VP when VGS is nonzero. So, although VP is a
constant, the minimum value of VDS at which ID becomes constant
varies with VGS. VGS(off) and VP are always equal in magnitude but
opposite in sign. A datasheet usually will give either VGS(off) or VP, but
not both. However, when you know one, you have the other. For example,
if VGS(off)=-5 V then VP = +5 V, as shown in Figure 2–7(b).

Transfer Characteristic
You have learned that a range of VGS values from zero to VGS(off)
controls the amount of drain current. For an n-channel JFET, VGS(off)
is negative, and for a p-channel JFET, VGS(off)is positive. Because VGS
does control ID, the relationship between these two quantities is very
important. The relationship between ID and VGS is defined by
Shockley’s equation

𝑽𝑮𝑺 𝟐
𝑰𝑫 = 𝑰𝑫𝑺𝑺 (𝟏 − )
𝑽𝑷

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The squared term in the equation results in a nonlinear relationship
between I D and VGS , producing a curve that grows exponentially with
decreasing magnitude of V GS .
Figure 2–12 is a general transfer characteristic curve that
illustrates graphically the relationship between VGS and ID. This curve
is also known as a trans-conductance curve.

Figure 2-12 JFET universal transfer

characteristic curve (n-channel).

Notice that the bottom end of the curve is at a point on the VGS axis
equal to VGS(off ), and the top end of the curve is at a point on the ID
axis equal to IDSS. This curve shows that

𝐼𝐷 = 0 𝑤ℎ𝑒𝑛 𝑉𝐺𝑆 = 𝑉𝐺𝑆(𝑜𝑓𝑓)

𝐼𝐷𝑆𝑆
𝐼𝐷 = 𝑤ℎ𝑒𝑛 𝑉𝐺𝑆 = 0.5 𝑉𝐺𝑆(𝑜𝑓𝑓)
4

𝐼𝐷𝑆𝑆
𝐼𝐷 = 𝑤ℎ𝑒𝑛 𝑉𝐺𝑆 = 0.3 𝑉𝐺𝑆(𝑜𝑓𝑓)
2

𝐼𝐷 = 𝐼𝐷𝑆𝑆 𝑤ℎ𝑒𝑛 𝑉𝐺𝑆 = 0

The transfer characteristic curve can also be developed from the

drain characteristic curves by plotting values of ID for the values of
VGS taken from the family of drain curves at pinch-off, as illustrated in
Figure 2–13 for a specific set of curves. Each point on the transfer
characteristic curve corresponds to specific values of VGS and ID on
the drain curves.

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 Figure 2-13 Example of the development of an n-channel JFET transfer
characteristic curve (blue) from the JFET drain characteristic curves (green)

FET Datasheet
JFET Forward Trans-conductance
The forward trans-conductance (transfer conductance), gm, is the
change in drain current for a given change in gate-to-source voltage
with the drain-to-source voltage constant. It is expressed as a ratio
and has the unit of siemens (S).
∆𝐼𝐷
𝑔𝑚 =
∆𝑉𝐺𝑆
𝑔𝑚 is an important factor in determining the voltage gain of a FET
amplifier.
Because the transfer characteristic curve for a JFET is nonlinear,
𝑔𝑚 varies in value depending on the location on the curve as set by VGS.
The value for 𝑔𝑚 is greater near the top of the curve (near VGS = 0)
than it is near the bottom (near VGS(off)), as illustrated in Figure 2–14.
A datasheet normally gives the value of 𝑔𝑚 measured at VGS=0 V
(𝑔𝑚0 ). Given 𝑔𝑚0 , you can calculate an approximate value for 𝑔𝑚 at any
point on the transfer characteristic curve using the following formula:

𝑽𝑮𝑺 𝑰𝑫
𝒈𝒎 = 𝒈𝒎𝟎 (𝟏 − ) = 𝒈𝒎𝟎 (√ )
𝑽𝑮𝑺(𝒐𝒇𝒇) 𝑰𝑫𝑺𝑺
H.W
𝟐𝑰𝑫𝑺𝑺
𝒈𝒎𝟎 =
|𝑽𝑮𝑺(𝒐𝒇𝒇) |
On specification sheets, gm is often provided as 𝒈𝒇𝒔 or 𝒚𝒇𝒔

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Figure 2-14 𝒈𝒎 varies depending
on the bias point (VGS).

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Maximum Ratings
The maximum rating list usually appears at the beginning of the
specification sheet, with the maximum voltages between specific
terminals, maximum current levels, and the maximum power dissipation
level of the device. The specified maximum levels for VDS , VDG and
VGS must not be exceeded at any point in the design operation of the
device. Any good design will try to avoid these levels by a good margin
of safety. Although normally designed to operate with IG=0 mA, if
forced to accept a gate current, it could withstand 10 mA ( IGF )
before damage would occur.

Thermal Characteristics
The total device dissipation at 25°C (room temperature) is the
maximum power the device can dissipate under normal operating
conditions and is defined by
𝑃𝐷 = 𝑉𝐷𝑆 𝐼𝐷

Electrical Characteristics
The electrical characteristics include the level of VP in the “off”
characteristics and IDSS in the “on” characteristics. In this case
VP=VGS(off) has a range from -0.5 V to -6.0 V and IDSS from 1 mA to
5 mA.

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 Figure 2-15 JFET partial datasheet

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Metal Oxide Semiconductor Field Effect Transistor
(MOSFET)
The MOSFET (metal oxide semiconductor field-effect transistor) is
another category of field-effect transistor. The MOSFET, different
from the JFET, has no pn junction structure; instead, the gate of the
MOSFET is insulated from the channel by a silicon dioxide (SiO2) layer.
The two basic types of MOSFETs are enhancement (E) and depletion
(D). These devices are generally operated in the depletion mode so
it is called D-MOSFET.

Basic Structure of MOSFET

Figure 2–16 illustrates the basic structure of the both n-channel
and p-channel MOSFET. We will use the n-channel device to describe
the basic structure and operation.
 A slab of p-type material is formed from a silicon base and is
referred to as the substrate. In some cases the substrate is
internally connected to the source terminal.
 The source and drain terminals are connected through metallic
contacts to n-doped regions linked by an n-channel.
 The gate is also connected to a metal contact surface but remains
insulated from the n-channel by a very thin silicon dioxide (SiO2)
layer.

Figure 2-16 the basic structure of MOSFETs.

Basic Operation and Characteristics of MOSFET

The MOSFET can be operated in either of two modes—the depletion
mode or the enhancement mode—and is sometimes called a
depletion/enhancement MOSFET.
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 1- Depletion Mode The n-channel MOSFET operates in the depletion
mode when a negative gate-to-source voltage is applied. With a
negative gate voltage, the negative charges on the gate repel
conduction electrons from the channel, leaving positive ions in
their place. Thereby, the n channel is depleted of some of its
electrons, thus decreasing the channel conductivity. The resulting
current with VGS = 0 V continues to be labeled IDSS , as shown
in Figure 2-18 .
The greater the negative voltage on the gate, the greater the
depletion of n-channel electrons. At a sufficiently negative gate-
to-source voltage, VGS(off ), the channel is totally depleted and
the drain current is zero as shown in figure (2-18). The resulting
levels of drain current and the plotting of the transfer curve
proceed exactly as described for the JFET. This depletion mode
is illustrated in Figure 2–17(a).
2- Enhancement Mode With a positive gate voltage, more conduction
electrons are attracted into the channel, thus increasing
(enhancing) the channel conductivity, as illustrated in Figure 2–
17(b). As VGS continues to increase in the positive direction,
Figure 2-18 reveals that the drain current will increase at a rapid
rate.

Figure 2-17 Operation of n-channel D-MOSFET

It is particularly interesting and helpful that Shockley’s equation

will continue to be applicable for the depletion-type MOSFET
characteristics in both the depletion and enhancement regions.

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 𝑽𝑮𝑺 𝟐
𝑰𝑫 = 𝑰𝑫𝑺𝑺 (𝟏 − )
𝑽𝑷

For both regions, it is simply necessary that the proper sign be

included with VGS in the equation and the sign be carefully
monitored in the mathematical operations.
The fact that Shockley’s equation is also applicable to depletion-
type MOSFETs (D-MOSFETs) results in the same equation for gm.
𝑽𝑮𝑺 𝑰𝑫
𝒈𝒎 = 𝒈𝒎𝟎 (𝟏 − ) = 𝒈𝒎𝟎 (√ )
𝑽𝑮𝑺(𝒐𝒇𝒇) 𝑰𝑫𝑺𝑺
𝟐𝑰𝑫𝑺𝑺
𝒈𝒎𝟎 =
|𝑽𝑮𝑺(𝒐𝒇𝒇) |

Figure 2-18 Drain and transfer characteristics for an n-channel depletion-type

MOSFET

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P-Channel Depletion-Type MOSFET

Figure 2-19 p-Channel depletion-type MOSFET with IDSS =6 mA and V P =

+6V

MOSFET Symbols: The schematic symbols for both the n-channel

and the p-channel depletion MOSFETs are shown in Figure 2–20. The
substrate, indicated by the arrow, is normally (but not always)
connected internally to the source. Sometimes, there is a separate
substrate pin.

Figure 2-20 D-MOSFET schematic

symbols.

Enhancement MOSFET (E-MOSFET)

The E-MOSFET operates only in the enhancement mode and has no
depletion mode.
Basic Construction
Figure (2-21a) illustrates the basic structure of the both n-channel
EMOSFET. We will use the n-channel device to describe the basic
structure and operation.
 A slab of p-type material is formed from a silicon base and is again
referred to as the substrate.
 The source and drain terminals are again connected through
metallic contacts to n-doped regions, but note in figure (2-21) the
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 absence of a channel between the two n-doped regions and the
substrate extends completely to the SiO2 layer. This is the
primary difference between the construction of depletion-type
and enhancement-type MOSFETs.
 The SiO2 layer is still present to isolate the gate metallic
platform from the region between the drain and source, but now it
is simply separated from a section of the p-type material.

Basic Operation and Characteristics of EMOSFET

If VGS is set at 0 V and a voltage applied between the drain and the
source of the device of Figure 2-21a, the absence of an n-channel
will result in a current of effectively 0A,quite different from the
depletion-type MOSFET and JFET,
where ID=IDSS.

(a)Basic Structure (b) EMOSFET Operation

Figure 2-21 Representation of the basic E-MOSFET construction and operation

(n-channel)

If both VDS and V GS have been set at some positive voltage

greater than 0 V the electrons in the p-substrate will be attracted to
the positive gate and accumulate in the region near the surface of the
SiO2 layer. The SiO2 layer and its insulating qualities will prevent the
negative carriers from being absorbed at the gate terminal. As VGS
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increases in magnitude, the concentration of electrons near the SiO2
surface increases until eventually the induced n-type region can support
a measurable flow between drain and source. The level of VGS that
results in the significant increase in drain current is called the
threshold voltage and is given the symbol VT. On specification sheets it
is referred to as VGS(Th). As VGS is increased beyond the threshold
level, the density of free carriers in the induced channel will increase,
resulting in an increased level of drain current. Figure 2–22 shows the
general transfer characteristic curves for both types of E-MOSFETs.

Figure 2-22 E-MOSFET

general transfer
characteristic curves.

The equation for the parabolic transfer characteristic curve of the

E-MOSFET differs from that of the JFET and the D-MOSFET because
the curve starts at VGS(th) rather than VGS(off )on the horizontal
axis and never intersects the vertical axis. The equation for the E
MOSFET transfer characteristic curve is
𝟐
𝑰𝑫 = 𝑲 (𝑽𝑮𝑺 − 𝑽(𝑮𝑺𝑻𝒉 )
The constant K depends on the particular MOSFET and can be
determined from the datasheet.
The forward trans-conductance (transfer conductance), gm
∆𝑰𝑫
𝒈𝒎 = = 𝟐𝑲 (𝑽𝑮𝑺 − 𝑽(𝑮𝑺𝑻𝒉 )
∆𝑽𝑮𝑺

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MOSFET Symbols
The schematic symbols for the n-channel and p-channel E-MOSFETs
are shown in Figure 2–23.

Figure 2-23 E-MOSFET schematic

symbols.

FET SMALL-SIGNAL MODEL

The ac analysis of a FET configuration requires that a small-signal ac
model for the FET be developed. A major component of the ac model
will reflect the fact that an ac voltage applied to the input gate-to-
source (Vgs) terminals will control the level of current from drain to
source (Id).
The control of Id by Vgs is included as a current source gmVgs
connected from drain to source. The current source has its arrow
pointing from drain to source to establish a 180° phase shift between
output and input voltages as will occur in actual operation.
The input impedance of FETs is approximate an open circuit
𝑍𝑖𝑛 = ∞ Ώ

The output impedance of FETs is similar in magnitude to that of

conventional BJTs. On FET specification sheets, the output impedance
will typically appear as 𝒈𝑶𝑺 or 𝒚𝑶𝑺 with the units of (S).

∆𝑽𝑫𝑺 𝟏 𝟏
𝒁𝒐𝒖𝒕 = 𝒓𝒅 = ⃒𝑽𝑮𝑺=𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕 = =
∆𝑰𝑫 𝒈𝑶𝑺 𝒚𝑶𝑺

Figure (2-24) show the definition of 𝒓𝒅 using drain char.

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Figure (2-24) Definition of
𝒓𝒅 using JFET drain
characteristics.

Figure (2-25) shows the ac equivalent circuit for the FET.

Figure (2-25) FET ac

equivalent circuit.

Where 𝑔𝑚 for JFET and D-MOSFET

𝑽𝑮𝑺 𝑰𝑫
𝒈𝒎 = 𝒈𝒎𝟎 (𝟏 − ) = 𝒈𝒎𝟎 (√ )
𝑽𝑮𝑺(𝒐𝒇𝒇) 𝑰𝑫𝑺𝑺
𝟐𝑰𝑫𝑺𝑺
𝒈𝒎𝟎 =
|𝑽𝑮𝑺(𝒐𝒇𝒇) |

And for EMOSFET

∆𝑰𝑫
𝒈𝒎 = = 𝟐𝑲 (𝑽𝑮𝑺 − 𝑽(𝑮𝑺𝑻𝒉 )
∆𝑽𝑮𝑺

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 FET Amplifier Biasing
For the field-effect transistor, the relationship between input and
output quantities is nonlinear due to the squared term in Shockley’s
equation. The nonlinear relationship between ID and VGS can complicate
the mathematical approach to the dc analysis of FET configurations. A
graphical approach may limit solutions to tenths-place accuracy, but it is
a quicker method for most FET amplifiers.
The general relationships that can be applied to the dc analysis of all
FET amplifiers are
𝑰𝑮 ≅ 𝟎
𝑰𝑫 ≅ 𝑰𝑺
For JFETs and depletion-type MOSFETs and MESFETs, Shockley’s
equation is applied to relate the input and output quantities

𝑽𝑮𝑺 𝟐
𝑰𝑫 = 𝑰𝑫𝑺𝑺 (𝟏 − )
𝑽𝑷
For enhancement-type MOSFETs and MESFETs, the following
equation is applicable:
𝟐
𝑰𝑫 = 𝑲 (𝑽𝑮𝑺 − 𝑽(𝑮𝑺𝑻𝒉 )
It is particularly important to realize that all of the equations
above are for the field effect transistor only! They do not change
with each network configuration so long as the device is in the
active region.

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 Fixed-Bias Configuration:
DC Analysis of fixed biased configuration

Figure 2-26 Fixed Bias Configuration

Figure 2-26 finding the solution for the fixed bias

configuration using plot

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AC Analysis for Fixed Biased configuration

Figure (2-27) AC equivalent circuit for fixed biased

configuration

Example 2.1: for the circuit shown, if

yos=40µs determine
a. VGSQ g. Gm
b. IDQ h. rd
c. VDS i. Zin
d. VD j. Zout
e. VS k. Av
f. VG

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24 College of Electronics Engineering - Communication Engineering Dept.
 Self-Bias Configuration
DC Analysis of self-bias configuration
The self-bias configuration eliminates the need for two dc supplies.
The controlling gate-to-source voltage is now determined by the voltage
across a resistor RS introduced in the source leg of the configuration
as shown in Figure 2-28.

Figure 2-28 Self Bias Configuration

Figure 2-29 sketching the self-bias line.

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AC analysis of self-bias configuration (Un-bypassed)

Figure (2-30) Ac equivalent circuit for un-bypassed

self-biased configuration

AC analysis of self-bias configuration (bypassed)

Figure (2-31) Ac equivalent circuit for un-

bypassed self-biased configuration

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Example 2.2: for the circuit shown, if
yos=20µs determine
a. VGSQ g. Gm
b. IDQ h. rd
c. VDS i. Zin
d. VD j. Zout
e. VS k. Av
f. VG

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28 College of Electronics Engineering - Communication Engineering Dept.
 Voltage-Divider Biasing Configuration
DC analysis of voltage-divider biasing configuration

Figure 2-32 Voltage-Divider Biased amplifier

Figure 2-33 Sketching the network equation for the

voltage-divider configuration.

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AC analysis of voltage-divider biasing configuration
(Bypassed)

Figure (2-34) ac equivalent circuit for bypassed voltage divider configuration

AC analysis of voltage-divider biasing configuration

(Un-Bypassed)

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Example 2.3: for the circuit
shown, determine
l. VGSQ r. gm
m. IDQ s. rd
n. VDS t. Zin
o. VD u. Zout
p. VS v. Av
q. VG

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 Common-Drain (Source Follower) Configuration
DC analysis of common-drain (source follower) configuration

Figure 2-35 common drain Biased amplifier

Figure 2-36 sketching the common drain line.

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AC analysis of common-drain (source follower) configuration

Figure (2-37) ac equivalent circuit for the common

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34 College of Electronics Engineering - Communication Engineering Dept.
Example 2.4: for the circuit
shown, if yos=25µs determine
a. VGSQ g. Gm
b. IDQ h. rd
c. VDS i. Zin
d. VD j. Zout
e. VS k. Av
f. VG

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36 College of Electronics Engineering - Communication Engineering Dept.
 Common-Gate Configuration:
DC analysis of common-gate configuration:

Figure 2-38common gate configuration

Figure 2-39 determining the Q-point for the

network of Figure 2-35

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AC analysis of common-gate configuration:

Figure (2-40) ac equivalent model for the

common gate.

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39 College of Electronics Engineering - Communication Engineering Dept.
Example 2.5: for the circuit shown, determine
a. VGSQ g. Gm
b. IDQ h. rd
c. VDS i. Zin
d. VD j. Zout
e. VS k. Av
f. VG

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41 College of Electronics Engineering - Communication Engineering Dept.
Example 2.6: for the circuit shown, determine
a. VGSQ g. Gm
b. IDQ h. rd
c. VDS i. Zin
d. VD j. Zout
e. VS k. Av
f. VG

42 College of Electronics Engineering - Communication Engineering Dept.

 EMOS Amplifier
The transfer characteristics of the enhancement-type MOSFET are
quite different from those encountered for the JFET and depletion-
type MOSFETs, resulting in a graphical solution (which is shown in
figure (2-41)) quite different from those of the preceding sections.
Since specification sheets typically provide the threshold voltage
and a level of drain current (ID(on)) and its corresponding level of
VGS(on), two points are defined immediately as shown in figure (2-41).
To complete the curve, the constant k of transfer characteristics
equation must be determined as follows.
𝟐
𝑰𝑫(𝒐𝒏) = 𝑲 (𝑽𝑮𝑺(𝒐𝒏) − 𝑽(𝑮𝑺𝑻𝒉 )
Once k is defined, other levels of ID can be determined for chosen
values of V GS.

Figure (2-41) Transfer

characteristics of an n-channel
enhancement-type MOSFET.

E-MOSFET Drain-Feedback Configuration

DC Analysis E-MOSFET Drain-Feedback Configuration

Figure (2-42) E-MOSFET drain-feedback configuration.

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AC Analysis E-MOSFET Drain-Feedback Configuration

Figure (2-43) AC equivalent of the

network of figure (2-42)

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Example 2.6: for the circuit
shown, determine
l. VGSQ r. Gm
m. IDQ s. rd
n. VDS t. Zin
o. VD u. Zout
p. VS v. Av
q. VG

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Example 2.8 (H.W): for the circuit shown, determine Vo

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Example 2.9 : for the circuit shown, determine Vo

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48 College of Electronics Engineering - Communication Engineering Dept.
49 College of Electronics Engineering - Communication Engineering Dept.
 FET Frequency Response

Q1:- For the network of the self-biased amplifier shown:

a. Determine VGSQ and IDQ. frequency (fL).
b. Find gm0 and gm . h. Determine fH(in) and fH(out).
c. Calculate the midband gain (Av). i. Determine the high-cutoff
d. Determine Zi. frequency (fH).
e. Calculate Avs. j. Determine the bandwidth (BW).
f. Determine fL(C1), fL(C2) and k. Determine the Gain-Bandwidth
fL(CS) product (GBP).
g. Determine the low-cutoff

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51 College of Electronics Engineering - Communication Engineering Dept.
52 College of Electronics Engineering - Communication Engineering Dept.
 Q2:- For the network of the voltage divider amplifier shown:
a. Determine VGSQ and IDQ. g. Determine the low-cutoff
b. Find gm0 and gm . frequency (fL).
c. Calculate the midband gain (Av). h. Determine fH(in) and fH(out).
d. Determine Zi. i. Determine the high-cutoff
e. Calculate Avs. frequency (fH).
f. Determine fL(C1), fL(C2) and j. Determine the bandwidth (BW).
fL(CS) k. Determine the Gain-Bandwidth
product (GBP).

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 1

Chapter Three
The Operational Amplifier (Op-Amp)
An operational amplifier, or op-amp, is a very high gain differential
amplifier with high input impedance and low output impedance. Typical uses
of the operational amplifier are to provide voltage amplitude changes
(amplitude and polarity), oscillators, filter circuits, and many types of
instrumentation circuits. An op-amp contains a number of differential
amplifier stages to achieve a very high voltage gain. Figure (1a) shows one of
the most famous operation amplifiers which is known as 741 Op-Amp.
The standard operational amplifier (op-amp) symbol is shown in Figure
(1b). It has two input terminals, the inverting (-) input and the non-inverting
(+) input, and one output terminal. Most op-amps operate with two dc supply
voltages, one positive and the other negative, as shown in Figure (1c),
although some have a single dc supply.

(a) (b) (c)

Figure (1) Op-Amp package and symbol

Figure (2) shows the IC pin distribution

Figure (2) Op-Amp pin distribution

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Ideal and Practical Op-Amp
The ideal op-amp has infinite voltage gain and infinite bandwidth. Also,
it has an infinite input impedance (open) so that it does not load the driving
source. Finally, it has a zero output impedance. Op-amp characteristics are
illustrated in Figure (3a).
Characteristics of a practical op-amp are very high voltage gain, very
high input impedance, and very low output impedance. These are labelled in
Figure (3b).

Figure (3) Basic op-amp representations.

The op-amp can be connected in a large number of circuits to provide
various operating characteristics. In this experiment, we cover a few of the
most common of these circuit connections.
Internal Block Diagram of an Op-Amp: A typical op-amp is made up
of three types of amplifier circuits: a differential amplifier, a voltage
amplifier, and a push-pull amplifier, as shown in Figure (4)

Figure (4) Basic internal arrangement of an op-amp.

Input Signal Modes
1- Single-ended differential mode
When an op-amp is operated in the single-ended differential mode, one
input is grounded and a signal voltage is applied to the other input, as

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shown in Figure (5). In the case where the signal voltage is applied to the
inverting input as in part (a), an inverted, amplified signal voltage appears
at the output. In the case where the signal is applied to the non-inverting
input with the inverting input grounded, as in Figure (5b), a non-inverted,
amplified signal voltage appears at the output.

Figure (5) Single-ended differential mode.

2- Double-ended differential mode
The double-ended differential mode, two opposite-polarity (out-of-phase)
signals are applied to the inputs, as shown in Figure (6a). The amplified
difference between the two inputs appears on the output. Equivalently,
the double-ended differential mode can be represented by a single source
Figure (6b).

Figure (6) Double-ended differential mode

3- Common Mode
In the common mode, two signal voltages of the same phase, frequency,
and amplitude are applied to the two
inputs, as shown in Figure (7). When
equal input signals are applied to both
inputs, they tend to cancel, resulting in a
zero output voltage.

Figure (7) Common-mode operation.

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 4

This action is called common-mode rejection. Its importance lies in the

situation where an unwanted signal appears commonly on both op-amp
inputs. Common-mode rejection means that this unwanted signal will not
appear on the output and distort the desired signal.

Op-Amp Parameters
1- Common-Mode Rejection Ratio
Desired signals can appear on only one input or with opposite polarities on
both input lines. These desired signals are amplified and appear on the output
as previously discussed. Unwanted signals (noise) appearing with the same
polarity on both input lines are essentially cancelled by the op-amp and do
not appear on the output. The measure of an amplifier’s ability to reject
common-mode signals is a parameter called the CMRR (common-mode
rejection ratio).
Practical op-amps, however, do exhibit a very small common-mode gain ( Acm
usually much less than 1), while providing a high open-loop differential voltage
gain ( Aol usually several thousand)
𝑨𝒐𝒍
𝑪𝑴𝑹𝑹 =
𝑨𝒄𝒎
𝑨𝒐𝒍
𝑪𝑴𝑹𝑹 (𝒅𝒃) = 𝟐𝟎 𝒍𝒐𝒈 ( )
𝑨𝒄𝒎

2- Maximum Output Voltage Swing (VO(p-p)):

With no input signal, the output of an op-amp is ideally 0 V. This is called
the quiescent output voltage. When an input signal is applied, the ideal
limits of the peak-to-peak output signal are ∓𝑉𝑐𝑐

3- Input Offset Voltage

The ideal op-amp produces zero volts out for zero volts in. In a practical
op-amp, however, a small dc voltage, VOUT(error), appears at the output
when no differential input voltage is applied.
The input offset voltage, VOS, is the differential dc voltage required
between the inputs to force the output to zero volts.

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4- The input bias current

The input bias current is the dc current required by the inputs of the
amplifier to properly operate the first stage

𝑰𝟏 + 𝑰𝟐
𝑰𝑩𝑰𝑨𝑺 =
𝟐

Figure (8)
5- Input Offset Current
Ideally, the two input bias currents are equal, and thus their difference is
zero. In a practical op-amp, however, the bias currents are not exactly equal.
The input offset current, IOS, is the difference of the input bias currents,
expressed as an absolute value.
𝑰𝑶𝑺 = |𝑰𝟏 − 𝑰𝟐 |
6- Input Impedance
Two basic ways of specifying the input impedance of an op-amp are the
differential and the common mode. The differential input impedance is the
total resistance between the inverting and the non-inverting inputs, as
illustrated in Figure (9a). The common-mode input impedance is the
resistance between each input and ground

Figure (9)

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Closed-Loop Voltage Gain, Acl
The closed-loop voltage gain is the voltage gain of an op-amp with external
feedback. The amplifier configuration consists of the op-amp and an
external negative feedback circuit that connects the output to the inverting
input. The closed-loop voltage gain is determined by the external component
values and can be precisely controlled by them.

Op-Amp Applications
1- Inverting Amplifier
An op-amp connected as an inverting amplifier with a controlled amount
of voltage gain is shown in Figure (10). The input signal is applied through a
series input resistor Ri to the inverting input. Also, the output is fed back
through Rf to the same input. The non-inverting (+) input is grounded.
At this point, the ideal op-amp parameters mentioned earlier are useful
in simplifying the analysis of this circuit. In particular, the concept of
infinite input impedance is of great value. An infinite input impedance implies
zero current at the inverting input. If there is zero current through the
input impedance, then there must be no-voltage drop between the inverting
and non-inverting inputs. This means that the voltage at the inverting input
is zero because the non-inverting (+) input is grounded. This zero voltage at
the inverting input terminal is referred to as virtual ground. This condition
is illustrated in Figure (10a).

Figure (10) Virtual ground concept and closed loop voltage gain
development for the inverting amplifier.
Since there is no current at the inverting input, the current through Ri
and the current through Rf are equal, as shown in Figure (4b).
𝐼𝑖𝑛 = 𝐼𝑓

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The voltage across Ri equals Vin because the resistor is connected to

virtual ground at the inverting input of the op-amp. Therefore,
𝑉𝑖𝑛
𝐼𝑖𝑛 =
𝑅𝑖
Also, the voltage across Rf equals because of virtual ground, and
therefore
−𝑉𝑜𝑢𝑡
𝐼𝑓 =
𝑅𝑓

Since 𝐼𝑖𝑛 = 𝐼𝑓
𝑉𝑖𝑛 −𝑉𝑜𝑢𝑡
=
𝑅𝑖 𝑅𝑓

𝑉𝑜𝑢𝑡 −𝑅𝑓
=
𝑉𝑖𝑛 𝑅𝑖

2- Non-inverting Amplifier
The connection of figure (11a) shows an op-amp circuit that works as a
non-inverting amplifier or constant-gain multiplier. To determine the voltage
gain of the circuit, we can use the equivalent representation shown in figure
(10b). Note that the voltage across R1 is V1 since Vi ≈ 0V. This must be
equal to the output voltage, through a voltage divider of R1 and Rf, so that
𝑅1
𝑉1 = 𝑉
𝑅1 + 𝑅𝑓 𝑜

Which results in

𝑉𝑜 𝑅1 + 𝑅𝑓 𝑅𝑓
= =1+
𝑉1 𝑅1 𝑅1

Figure (10) Non-

inverting Amplifier

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3- Voltage-Follower
The voltage-follower configuration is a special case of the non-
inverting amplifier where all of the output voltage is fed back to the
inverting input (-) by a straight connection, as shown in figure (12). As you
can see, the straight feedback connection has a voltage gain of 1 (which
means there is no gain).

Figure (12) Op-Amp Voltage Follower

Ex:-

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4- Inverting summing Amplifier

Probably the most used of the op-amp circuits is the summing amplifier
circuit shown in figure (13a). The circuit shows a three-input summing
amplifier circuit, which provides a means of algebraically summing (adding)
three voltages, each multiplied by a constant-gain factor. Using the
equivalent representation shown in figure (13b), we can express the output
voltage in terms of the inputs as

𝑉𝑜 𝑅𝑓 𝑅𝑓 𝑅𝑓
= −( 𝑉1 + 𝑉2 + 𝑉 )
𝑉𝑖 𝑅1 𝑅2 𝑅3 3

Figure (13) (a) inverting summing amplifier (b) equivalent circuit

In other words, each input adds a voltage to the output multiplied by
its separate constant-gain multiplier. If more inputs are used, they each add
an additional component to the output.

In the same way we can construct a non-inverting summing

amplifier

Example:- design an op-amp circuit that will produce an output

-(4v1+v2+0.1v3)

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 10

Write an expression for the output and sketch the waveform when
V1=2sinwt , v2=5V dc , v3=-100v dc

5- Comparator
A comparator is a specialized op-amp circuit that compares two input
voltages and produces an output that is always at either one of two states,
indicating the greater or less than relationship between the inputs. For less
critical applications, an op-amp running without negative feedback (open-
loop) is often used as a comparator.
One application of an op-amp used as a comparator is to determine when
an input voltage exceeds a certain level. Figure (14a) shows a zero-level
detector. Notice that the inverting input is grounded to produce a zero level
and that the input signal voltage is applied to the non-inverting input. Because
of the high open-loop voltage gain, a very small difference voltage between
the two inputs drives the amplifier into saturation, causing the output
voltage to go to its limit.
Figure (14b) shows the result of a sinusoidal input voltage applied to
the non-inverting input (+) of the zero-level detector. When the sine wave is
positive, the output is at its maximum positive level. When the sine wave
crosses 0, the amplifier is driven to its opposite state and the output goes
to its maximum negative level, as shown. As you can see, the zero level
detector can be used as a squaring circuit to produce a square wave from a
sine wave.

Figure (14) The op-amp as a zero-level detector.

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 11

6- Differential (Subtraction) Amplifier

Another connection to provide
subtraction of two signals is shown in
figure (15). This connection uses only one
op-amp stage to provide subtracting two
input signals. Using superposition, we can
show the output to be

Figure (15) Difference Amplifier

𝐕𝐨 = 𝐕𝐨𝟏 + 𝐕𝐨𝟐
𝑹𝟑 𝑹𝟒
𝑽𝒐𝟏 = ( (𝟏 + ) 𝑽𝟏 )
𝑹𝟏 + 𝑹𝟑 𝑹𝟐
𝑹𝟒
𝐕𝐨𝟐 = − ( 𝑽 )
𝑹𝟐 𝟐
𝑹𝟑 𝑹𝟒 𝑹𝟒
𝑽𝒐 = ( (𝟏 + ) 𝑽𝟏 ) − ( 𝑽 )
𝑹𝟏 + 𝑹𝟑 𝑹𝟐 𝑹𝟐 𝟐

Example

In order to reject common mode signals. We have to make the two gain
magnitudes equal.
𝐑𝟑 𝐑𝟒 𝐑𝟒
(𝟏 + ) =
𝐑𝟏 + 𝐑𝟑 𝐑𝟐 𝐑𝟐

Which can be put in the form:

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 12
𝐑𝟑 𝐑𝟒
=
𝐑𝟏 + 𝐑𝟑 𝐑𝟐 + 𝐑𝟒

This condition is satisfied by selecting

𝐑𝟑 𝐑𝟒
=
𝐑𝟏 𝐑𝟐

𝐕𝐨 = 𝐕𝐨𝟏 + 𝐕𝐨𝟐

𝐑𝟒
𝐕𝐨 = (𝐕 − 𝐕𝟐 )
𝐑𝟐 𝟏

𝐕𝐃𝐌 = 𝐕𝟐 − 𝐕𝟏 (𝐃𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐜𝐞 𝐦𝐨𝐝𝐞 𝐯𝐨𝐥𝐭𝐚𝐠𝐞 )

𝟏
𝐕𝐂𝐌 = (𝐕 + 𝐕𝟏 ) (𝐂𝐨𝐦𝐦𝐨𝐧 𝐦𝐨𝐝𝐞 𝐯𝐨𝐥𝐭𝐚𝐠𝐞 )
𝟐 𝟐
𝐕𝐃𝐌
𝐕𝟐 = 𝐕𝐂𝐌 +
𝟐
𝐕𝐃𝐌
𝐕𝟏 = 𝐕𝐂𝐌 −
𝟐

Substituted the V2 and V1 values in Vo equation, we estimate that only

the VDM is appears at the output. While the VCM is eliminated (Which appears
the noise signals)
If the amplifier is required to have a large differential gain (R 4 ⁄R 2 ),
then R 2 of necessity will be relatively small and the input resistance will be
correspondingly low, a problem of this circuit. Another problem of the circuit
is that it is not easy to vary the differential gain of the amplifier. Both of
these problems are overcome in the instrumentation amplifier discussed
next.

Instrumentation Amplifier
A circuit providing an output based on the difference between two
inputs (times a scale factor) is shown in Figure (16). A potentiometer is
provided to permit adjusting the scale factor of the circuit

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 13

Vout2

Vout1

Figure (16) instrumentation amplifier

Since we have 𝐕𝐢+ = 𝐕𝐢−
And the current pass through the resistors (𝐑, 𝐑 𝐩 𝐚𝐧𝐝 𝐑) is I, due to
the high input resistances of the op−amps. So we can say that:
V1 − Vout1
I=
R
V1 − Vout1 = IR ⟹ 𝐕𝐨𝟏 = 𝐕𝟏 − 𝐈𝐑

Vout2 − V2
I=
R
Vout2 − V2 = IR ⟹ 𝐕𝐨𝟐 = 𝐕𝟐 + 𝐈𝐑

Vo = Vo1 − Vo2

R𝑓 R𝑓
Vo = (V1 − IR − V2 − IR) = (V − V2 − 2 × IR)
R1 R1 1
V2 − V1
Since I =
RA
R𝑓 V2 − V1 R𝑓 V1 − V2
Vo = (V1 − V2 − 2R × )= (V1 − V2 + 2R × )
R1 RA R1 RA
R𝑓 2R
Vo = (V1 − V2 ) (1 + )
R1 RA

but Vin = (V1 − V2 )

𝐕𝐨 𝟐𝐑
𝐀𝐕 = = (𝟏 + )
𝐕𝐢𝐧 𝐑𝐀

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 14

Another circuit used to reduce CMRR

𝐑 𝟐 𝟐𝐑 𝟐
𝐕𝐨 = (𝐕𝟐 − 𝐕𝟏 ) (𝟏 + + ) 𝑯. 𝑾
𝐑𝟏 𝐑𝐀

Slew Rate
The maximum rate of change of the output voltage in response to a step
input voltage is the slew rate of an op-amp. Slew rate is measured with an
op-amp connected as shown in Figure (17a). This particular op-amp connection
gives a worst-case (slowest) slew rate.

Figure (17) slew rate measurement

A pulse is applied to the input and the resulting ideal output voltage is
indicated in Figure (17b). The width of the input pulse must be sufficient to
allow the output to “slew” from its lower limit to its upper limit. A certain
time interval, ∆𝒕 is required for the output voltage to go from its lower limit
−𝑉𝑚𝑎𝑥 to its upper limit +𝑉𝑚𝑎𝑥 once the input step is applied. The slew rate is
expressed as
∆𝑽𝒐𝒖𝒕
𝑺𝒍𝒆𝒘 𝑹𝒂𝒕𝒆 = 𝑽/𝝁𝑺
∆𝒕

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Integrator and Differentiator

An op-amp integrator simulates mathematical integration, which is
basically a summing process that determines the total area under the
curve of a function. An op-amp differentiator simulates mathematical
differentiation, which is a process of determining the instantaneous rate
of change of a function. It is not necessary for you to understand
mathematical integration or differentiation, at this point, in order to
learn how an integrator and differentiator work.

The Op-Amp Integrator

The Ideal Integrator: An ideal
integrator is shown in Figure (18). Notice
that the feedback element is a capacitor
that forms an RC circuit with the input
resistor.

Figure (18) Ideal Integrator

In Figure (18), the inverting input of the op-amp is at virtual ground (0
V), so the voltage across Ri equals Vin. Therefore, the input current is
𝑉𝑖𝑛
𝐼𝑖 =
𝑅𝑖
If Vin is a constant voltage, then Iin is also a constant because the
inverting input always remains at 0 V, keeping a constant voltage across Ri.
Because of the very high input impedance of the op-amp, there is negligible
current at the inverting input. This makes all of the input current go through
the capacitor, as indicated in Figure (1), so
𝐼𝑖𝑛 = −𝐼𝐶
𝑉𝑖𝑛 𝑑𝑉𝑜𝑢𝑡
− = 𝑡ℎ𝑖𝑠 𝑐𝑎𝑙𝑙𝑒𝑑 𝑡ℎ𝑒 𝑟𝑎𝑡𝑒 𝑜𝑓 𝑐ℎ𝑎𝑛𝑔𝑒 𝑜𝑓 𝑡ℎ𝑒 𝑜𝑢𝑡𝑝𝑢𝑡
𝑅𝑖 𝐶 𝑑𝑡
1
𝑑𝑉𝑜𝑢𝑡 = − 𝑉 𝑑𝑡
𝑅𝑖 𝐶 𝑖𝑛

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1
𝑉𝑜𝑢𝑡 = − ∫ 𝑉𝑖𝑛 𝑑𝑡 𝑖𝑛 𝑡𝑖𝑚𝑒 𝑑𝑜𝑚𝑎𝑖𝑛
𝑅𝑖 𝐶
𝑉𝑖𝑛 −𝑉𝑜𝑢𝑡
=
𝑅𝑖 𝑋𝑐
𝑉𝑜𝑢𝑡 −𝑋𝑐 −1
𝐴𝑣 = = = 𝑖𝑛𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑑𝑜𝑚𝑎𝑖𝑛
𝑉𝑖𝑛 𝑅𝑖 𝑤𝑅𝑖 𝐶
The Practical Integrator The ideal integrator uses a capacitor in the
feedback path, which is open to dc. This implies that the gain at dc is the
open-loop gain of the op-amp. In a practical integrator, any dc error voltage
due to offset error will cause the output to produce a ramp that moves
toward either positive or negative saturation (depending on the offset), even
when no signal is present.
Practical integrators must have some means of overcoming the effects
of offset and bias current. Various solutions are available, the simplest
solution is to use a resistor in parallel with the capacitor in the feedback
path, as shown in Figure (19). The feedback resistor, Rf, should be large
compared to the input resistor Rin , in order to have a negligible effect on
the output waveform. In addition, a compensating resistor, Rc, may be added
to the non-inverting input to balance the effects of bias current.

Figure (19) Practical Integrator

In the practical circuit it will

operate as inverting amplifier at frequencies less than the cutoff frequency
(fC). The gain is
𝑅𝑓
𝐺= −
𝑅𝑖𝑛
And as integrator at frequencies higher than the cutoff frequency (fC).
1
𝑓𝑐 =
2𝜋𝑅𝑓 𝐶

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The Op-Amp Differentiator

The Ideal Differentiator: An ideal differentiator is shown in Figure
(20). Notice how the placement of the capacitor
and resistor differ from the integrator. The
capacitor is now the input element, and the
resistor is the feedback element. A
differentiator produces an output that is
proportional to the rate of change of the input
voltage.

Figure (20) Ideal Differentiator

𝐼𝑖𝑛 = −𝐼𝑅
𝑑𝑉𝑖𝑛 −𝑉𝑜𝑢𝑡
𝐶 = =
𝑑𝑡 𝑅𝑓
𝑑𝑉𝑖𝑛
𝑉𝑜𝑢𝑡 = − 𝐶𝑅𝑓 𝑡ℎ𝑒 𝑜𝑢𝑡𝑝𝑢𝑡 𝑖𝑠 𝑡ℎ𝑒 𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑡𝑜𝑟 𝑜𝑓 𝑡ℎ𝑒 𝑖𝑛𝑝𝑢𝑡
𝑑𝑡
𝑉𝑜𝑢𝑡
𝐴𝑣 = = −𝑗𝑤𝐶𝑅𝑓
𝑉𝑖𝑛
The Practical Differentiator: The last equations shows that the ideal
differentiator has a very high gain amplifier at high frequencies. This means
that a differentiator circuit tends to be noisy because electrical noise mainly
consists of high frequencies. The solution to this problem is simply to add a
resistor, Rin, in series with the capacitor to act as a low-pass filter and
reduce the gain at high frequencies. The resistor should be small compared
to the feedback resistor in order to have a negligible effect on the desired
signal.
Figure (21) shows a practical differentiator. A bias compensating
resistor may also be used on the non-inverting input.

Figure (4) Practical

Differentiator

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In the practical circuit it will operate as inverting amplifier at

frequencies higher than the cutoff frequency (fC). The gain is
𝑅𝑓
𝐺= −
𝑅𝑖𝑛
And as differentiator at frequencies less than the cutoff frequency (fC).
1
𝑓𝑐 =
2𝜋𝑅𝑖𝑛 𝐶

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Chapter Four
Other Devices

The Unijunction Transistor (UJT)

The UJT (unijunction transistor) is a three-terminal device whose basic
construction is shown in Figure (4-1a). A slab of lightly doped (increased
resistance characteristic) n-type silicon material has two contacts attached
to both ends of one surface labelled as Base 1 and Base 2 (B1 and B2). The
p region of the device is formed at the other boundary of the n-type silicon
slab at a point closer to B2 contact than the B1 contact. The p region terminal
is labelled as Emitter (E). The single p–n junction accounts for the
terminology unijunction.
The schematic symbol appears in Figure (4-1b). Notice the terminals are
labelled Emitter (E), Base 1 and Base 2. Do not confuse this symbol with that
of a JFET; the difference is that the arrow is at an angle for the UJT.

Figure (4-1) UJT transistor (a) Basic Structure (b) Symbol

UJT Equivalent Circuit

The equivalent circuit for the UJT, shown in Figure (4-2), will aid in
understanding the basic operation. The diode shown in the figure represents
the pn junction. RB1 represents the internal dynamic resistance of the
silicon bar between the emitter and base 1. The resistance RB1 is shown as
a variable resistor since its magnitude will vary inversely with the current
IE. RB2 represents the dynamic resistance between the emitter and base 2.

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The Interbase resistance RBB is the resistance of the device between

terminals B1 and B2 when IE=0. In equation form
𝑹𝑩𝑩 = 𝑹𝑩𝟏 + 𝑹𝑩𝟐 𝒘𝒉𝒆𝒏 𝑰𝑬 = 𝟎
The magnitude of VRB1 (with IE=0) is determined by the voltage-divider rule
in the following manner:
𝑹𝑩𝟏 𝑹𝑩𝟏
𝑽𝑹𝑩𝟏 = 𝑽𝑩𝑩 = 𝑽𝑩𝑩
𝑹𝑩𝟏 + 𝑹𝑩𝟐 𝑹𝑩𝑩
𝑹𝑩𝟏
The ratio ( ) is a UJT characteristic called the intrinsic standoff
𝑹𝑩𝟏 +𝑹𝑩𝟐
ratio and is designated by
𝑹𝑩𝟏 𝑹𝑩𝟏
ɳ= =
𝑹𝑩𝟏 + 𝑹𝑩𝟐 𝑹𝑩𝑩

Figure (4-2) UJT equivalent circuit

UJT Emitter Characteristics Curve
The characteristics of a unijunction transistor are shown for VBB=10
V in Figure (4-3). As indicated in the figure there are four regions of
operations for the UJT.
Cutoff Region: As long as the applied emitter voltage (VE) is less than
(VRB1), there is no emitter current because the pn junction is not forward-
biased. The magnitude of IE is never greater than IEO (measured in
microamperes).

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Negative Resistance Region: The value of emitter voltage that causes the
pn junction to become forward biased is called (peak-point voltage) and is
expressed as VP.
𝑽𝑷 = 𝑽𝑹𝑩𝟏 + 𝑽𝑫 = ɳ𝑽𝑩𝑩 + 𝑽𝑫
Once conduction is established at VE=VP, the pn junction becomes forward-
biased and IE begins. Holes are injected into the n-type bar from the p-type
emitter. This increase in holes causes an increase in free electrons, thus
increasing the conductivity between emitter and B1 (decreasing RB1).
After turn-on, the UJT operates in a negative resistance region up to a
certain value of as shown by the characteristic curve in Figure (4-3). As you
can see, after the peak point (VE = VP and IE = IP), VE decreases as IE
continues to increase. This corresponds exactly to the decreasing resistance
RB1 for increasing current IE thus producing the negative resistance
characteristic.
Saturation Region: Eventually, the valley point will be reached (VE = VV and
IE = IV), and any further increase in IE will place the device in the saturation
region. In this region, the characteristics approach those of the
semiconductor diode in the equivalent circuit of Figure (4-2).

Figure (4-3) UJT emitter characteristic curve

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UJT Applications
UJT used in a various applications include
nonsinusoidal oscillators, sawtooth generators, phase
control, and timing circuits. Figure (4-4) shows a UJT
relaxation oscillator as an example of one application.
The resistor R1 must be chosen to ensure that the load
line determined by R1 passes through the device
characteristics in the negative-resistance region.

Figure (4-4) UJT Relaxation Oscillator

The operation is as follows.
When dc power is applied, the capacitor C charges exponentially through R1
until it reaches the peak-point voltage VP as shown in figure (4-5a). As VC
(and therefore VE) is less than VP the diode is off and the value of the output
voltage, as shown in figure (4-5b), is
𝑉 × 𝑅2
𝑉𝑜 = 𝑉𝑅2 =
𝑅2 + 𝑅𝐵𝐵

(b) Equivalent circuit

(a) Capacitor and output voltages

Figure (4-5) the action of the circuit during charging

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As the capacitor voltage reaches the pick point (VP), the pn junction becomes
forward-biased, and the emitter characteristic goes into the negative
resistance region (VE decreases and IE increases). The capacitor then quickly
discharges through the forward-biased junction, RB1 and R2.
Figure (4-6a) shows the capacitor and output waveforms and Figure (4-6b)
shows the equivalent circuit during this operation.

(a) Capacitor and output voltages (b) Equivalent circuit

Figure (4-6) the action of the circuit during discharging
When the capacitor voltage decreases to the valley-point voltage the
UJT turns off, the capacitor begins to charge again, and the cycle is
repeated.

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SHOCKLEY DIODE
The4-layer diode(also known as Shockley diode and SUS) is a type of
Thyristor, which is a class of devices constructed of four semiconductor
layers. The basic construction of a 4-layer diode and its schematic symbol
are shown in Figure (4-7).

Figure (4-7) Shockley Diode

The pnpn structure can be represented by an equivalent circuit

consisting of a pnp transistor and an npn transistor, as shown in Figure (4-
8a).

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