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Fa19 Eee 025 (DSD Lab05)

The document describes a lab assignment to implement a 4-digit decimal counter on an FPGA board. Key modules designed and interconnected include a BCD to 7-segment decoder, parameterized counter, 4x1 multiplexer, binary to BCD converter, and reset counter. The counter counts from 0 to 9999 and the output is displayed continuously on the FPGA's four 7-segment displays through a display controller. Critical analysis notes the clock divisor, multiplexing, and display controller allow the results to be visualized properly on the common anode 7-segment displays.

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18 views11 pages

Fa19 Eee 025 (DSD Lab05)

The document describes a lab assignment to implement a 4-digit decimal counter on an FPGA board. Key modules designed and interconnected include a BCD to 7-segment decoder, parameterized counter, 4x1 multiplexer, binary to BCD converter, and reset counter. The counter counts from 0 to 9999 and the output is displayed continuously on the FPGA's four 7-segment displays through a display controller. Critical analysis notes the clock divisor, multiplexing, and display controller allow the results to be visualized properly on the common anode 7-segment displays.

Uploaded by

tslfmn083
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Page |1

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

Digital System Design – LAB

Lab Report #05:

Design and Implementation of a Four Digit Decimal Counter on Nexys2 FPGA Board

Lab Assessment

Lab Task Lab Report Total


Evaluation Data Presentation Data Analysis Writing Style (PLO10)
4 2 2 2 10

Introduction:
The lab aimed to implement up/down counter with terminal count and reset on FPGA. We were
able to learn how to use the internal clock of FPGA and implement clock divisor. The counter
value will be displayed on 7-segment displays of Nexys2 board so we implement scanning
display controller to control multiple 7-segment displays because they have a common data bus
(CA – DP).The 4 seven segments of Nexys 2 board are common anode in configuration. A clock
divisor circuit was designed that converts internal 20nsec clock to 40ns to visualize the results on
seven segments as FPGA clock 20ns can’t be seen toggling due to persistence of vision. As 4-
digit 7-segment displays have a common data bus so multiplexer is used to select one data and
segment id at a time of refresh period. Seven segment display controller was also designed that
Page |2

helps to illuminate all four digits continuously. The results are displayed on FPGA 7 segments
and shown to the instructor.

Pre-Lab Task:

Fig1: 7 Segment pins configuration

Fig2: 7 Segment Common Anode Truth Table

BCD to 7 Segment Module:

module BCDto7Seg(input [3:0] BCD,output reg [6:0] segreg );

always@(BCD)

begin

case (BCD)

0 : segreg = 7'b0000001;

1 : segreg = 7'b1001111;

2 :segreg = 7'b0010010;

3 :segreg = 7'b0000110;

4 :segreg = 7'b1001100;

5 :segreg = 7'b0100100;
Page |3

Fig3: BCD to 7 Segment

Counter Module:

module COUNTER(clk,rst,en,UPcounter,count,tc);

parameter n = 26, N = 50000000;

input clk;

input rst;

input en;

input UPcounter;

output reg [n-1:0] count;

output reg tc;

always @(posedge clk or posedge rst) begin

if(rst) begin
Page |4

Fig4: Parameterized Counter

4x1 Mux Module:

module MUXfourxone(

input [3:0] A,

input [3:0] B,

input [3:0] C,

input [3:0] D,

input [1:0] S,

output reg [3:0] Z


Page |5

Fig5: 4x1 Mux

Binary to BCD Module:

module BinaryToBCD(binary,ones,tens,hundreds,thousands);

parameter n = 14;

input [n-1:0] binary; output reg [3:0] ones; output reg [3:0] tens;

output reg [3:0] hundreds; output reg [3:0] thousands; integer i;

always @(binary) begin

thousands = 4'd0;

hundreds = 4'd0;

tens = 4'd0;

ones = 4'd0;

for(i=n-1; i>=0; i=i-1) begin


if (thousands >= 5)

Page |6

Fig6: Binary to BCD

Main Module:

module main(

input clk,

input rst,

input en,

input UPcounter,

output [6:0] seg_out,

output [3:0] m2_out

);
Page |7

Fig7: Top level Module implements the below block diagram

Block Diagram for different modules interconnections:


Page |8

Fig8: Block Diagram

FPGA Implementation:

Fig9: FPGA Output

Module:

module reset_counter(count, sclk, clk, rst, En, UD, S);


input clk,En,UD;
input [7:0]S;
parameter n=25,N=25000000;
output reg [n-1:0]count;
output reg sclk, rst;
always@ (*)
if(S==0) begin
rst = 0;
end
Page |9

Fig10: Reset Counter

module tb_reset_counter;

// Inputs
reg clk;
reg En;
reg UD;
reg [7:0] S;

// Outputs
wire [24:0] count;
wire sclk;
wire rst;

// Instantiate the Unit Under Test (UUT)


reset_counter uut
( .count(count), .sclk(sclk), .clk(clk), .rst(rst), .En(En), .UD(UD), .
S(S) );
P a g e | 10

Fig11: Simulation

Critical Analysis/Conclusion:
In this lab we were assigned task to design up/down counter that counts the number in decimal
digits from 0 to 9999 and the results are displayed on 4 seven segments of Nexys 2 board which
are common anode in configuration. A clock divisor circuit was designed that converts internal
20nsec clock to 40ns to visualize the results on seven segments. As 4-digit 7-segment displays
have a common data bus so multiplexer is used to select one data and segment id at a time of
refresh period. Seven segment display controller was also designed that helps to illuminate all
four digits continuously. The results are displayed on FPGA 7 segments and shown to the
instructor.
P a g e | 11

THE END

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