2020 7th International Conference on Information Science and Control Engineering (ICISCE)

2020 7th International Conference on Information Science and Control Engineering (ICISCE) | 978-1-7281-6406-9/20/$31.00 ©2020 IEEE | DOI: 10.1109/ICISCE50968.2020.00465

Design and Verification of UART Circuit of SoC Based on AMBA Bus

Yuan Liu 1, Lei Zhang 1, Shuxi Xu 1, Jian Wang 1, Chen Ning Wang2*
Xu 1,Linglin Zhou 1 2. University of Shanghai for Science and Technology
1.214 Institute of China North Industries Shanghai 200082,China
Suzhou 215163, China *email: [email protected]
When receiving the low power level on 8 RXD interfaces
AbstractüUART (Universal Asynchronous Receiver/transmitter) continuously, the detector will automatically accept a start bit in
is a universal asynchronous transceiver used for serial data the RXD interface by default and will enter the state of
communication. It can not only receive data from peripheral receiving data. In the receiving state, the receiving controller
conducts sampling for three pulses of data bits 7, 8, and 9, and
devices, but also receive data from CPU, so as to achieve serial the final value will be determined in accordance with the
parallel conversion and parallel serial conversion. In this paper, a principle of two out of three[5-7]. The main purpose of this
UART circuit based on AMBA (Advanced Microcontroller Bus method is to enhance the anti-interference performance and
improve the reliability of data transmission. The sampling
Architecture) bus protocol is designed. The system bus is based
signal is always in the middle position of each receiving bit,
on AXI protocol, and the low-speed module interface adopts which can avoid the edge distortion at two ends of data bits, and
APB bus. AXI bus communicates with APB bus through also can prevent the occurrence of errors caused by incomplete
AXI-to-APB. UART is mounted on APB bus. The interactive synchronization between clock frequency receiving and clock
frequency sending. Its one-frame data format is Start bit (0) +8
communication between the system and external devices is bits +Stop (1), shown as follows:
realized in the system software. Quartus II is used for design and
verification on FPGA chip. The verification results show that the START D0 D1 D2 D3 D4 D5 D6 D7 STOP
transmission data is correct.
Figure 1 One-frame data format
Keywords: UART; AMBA bus; AXI bus; APB bus The data received and transmitted by UART starts with LSB, and
then MSB follows, and the line is stably pulled up to “1” in the idle
I. INTRODUCTION time. The interval time between multi-frame data is inconsistent, but the
interval between data in each bit inside the frame is stably consistent.
UART (Universal Asynchronous Receiver/transmitter) is a The multi-frame data is shown as follows [8].
universal asynchronous transceiver used for serial data
communication. Basically, it can receive data from peripheral
devices, to realize serial-parallel conversion, and also receive
data from CPU, to achieve parallel-serial conversion. CPU can
query the complete state of each channel at any time while it is
working, and monitor the execution of various commands and
the occurrence of any errors. UART, as a remote Figure 2 Multi-frame data format
communication interface, has been widely applied in digital
systems, and it is a very important module. The different
modules of UART are designed in a modular method, including III. FUNDAMENTAL PRINCIPLES
APB bus interface module, reset management module, register
management module, synchronization module, clock generator.
FIFO control management module, transmitter/receiver
module, and etc. Quartus II 13.0 is used for comprehensive
description
on FPGA chip, and the reliability and accuracy of design
are confirmed after validation[1-4].

II. THEORETICAL ANALYSIS

UART is an asynchronous transceiver. It is a part of
computer hardware, and converts the data to transmit between
serial communication and parallel communication. As a chip to
convert the parallel input signal to serial output signal, UART is
generally integrated on the connections of other communication
interfaces. The RXD front end of standard UART is provided Figure 3 UART structure diagram
with a “1 to 0 jump detector”.

Fund program: National Natural Science Foundation of China (61804096);

978-1-7281-6406-9/20/$31.00 ©2020 IEEE 2370

DOI 10.1109/ICISCE50968.2020.00465
Authorized licensed use limited to: KLE Technological University. Downloaded on November 23,2023 at 13:09:34 UTC from IEEE Xplore. Restrictions apply.
 The internal modules of UART mainly include APB bus IV. CIRCUIT DESIGN AND SIMULATION
interface module, reset management module, register
management module, synchronization module, clock generator, A. Baud rate generator
FIFO control management module, transmitter/receiver module, Considering that the accuracy of transmitting and receiving
and etc[9]. will be affected by clock jitter, deviation of slight fluctuation of
UART module is provided with the functions such as baud rate between communication parties and unstable state of
synchronous processing of serial asynchronous receiving data, edge of single bit data, the most important point of design is to
parallel-serial and serial –parallel conversion of data between improve the accuracy of sampling, which generally refers to the
the transmitter and the receiver, and all of these are needed for a fact that the sampling point is in the middle point of time of
digital system to convert the serial data to parallel data. The sampled data. Therefore, when sampling is received, a clock
synchronization of serial data streams is achieved by adding with a rate n times (n≥1) higher than the data baud rate is
start and stop bits to the sent data to form a data character needed to sample the data. In this design, the frequency division
(directional character transfer protocol), and the integrity of data control of the whole circuit is not directly equal to the value of
is ensured by adding a parity check bit behind the character, and preset baud rate. Instead, 16 times of the baud rate is used as the
the receiver can check the error of any sending bit via parity bit. data sampling rate to sample the middle value of single bit data
The UART module is provided with 512/1024 bytes of to improve the data accuracy, with the theory shown as
FIFO sending and receiving storage internally, which can follows :
communicate with the external interface and work in the
common network environment requiring high rate data
processing. These characteristics of UART interface are all
realized via FIFO sending and receiving, so that the external
processor can handle lots of network tasks in a fixed time.
The data selector is provided with 10 inputs, in which, 8
inputs are 8bit parallel data, and the remaining is 0 and 1,
respectively with the function of generating a start bit and Figure 6 Data sampling model
pulling up the idle, so that the parallel data can be accurately The data can be sampled when single-bit 7-9 clocks are in
converted to serial data under the control of counter to be sent rising edge, and sampling can be conducted for multiple times
in the currently set baud rate. Each bit of data lasts 16 times further improve the accuracy of data receiving and transmitting,
longer than that of th current frequency division clock. The and also when sending data, a clock with 16x baud rate can be
parallel-serial conversion principle is shown as below. used to accurately send the data one by one from LSB to MSB
 E
through counting control, which can reduce the influence of
local original clock errors and the design difficulty, to easily
convert the parallel data into the serial data sent with the set
'$7$>@ 7;' baud rate.
Table I Sampling rate clock division

 E
Sampling rate Clock
4800*16 650
FQW
Figure 4 Parallel-serial conversion principle 9600*16 325
When RXD data line is idle, it is usually pulled up to 1.
When the data is transmitted, there will be a start bit with 1BIT B. Baud rate control module design
= 0 at first. As the entire circuit clock follows the frequency The baud rate control module is mainly to produce the
division of the original clock, and the frequency division is 16 function of 16x baud rate through counting frequency division.
times of the baud rate, once the data 0 is detected on the data As two baud rate working modes, 4800bit/s and 9600bit/s, can
line, and “0” is detected for 8 continuous times, the start bit will be selected in this design, the counter has two counting modes,
be determined. Set receive as effective, start counting until 146 with the only difference lying in the different counting step
sampling, the data on RXD is just the stable value in the right length.
center of BSB in 1bit. Sampling with an interval of 146, and it
is the stable value of the next bit of data. Such design has S

reduced the difficulty and also improved the accuracy of data T

sampling[10].
!reset

T
clk

T
temp

T T
cnt<=0 cnt>=325 cnt>=650

cnt<=cnt+_1'b1 cnt<=0 cnt<=0 cnt<=cnt+_1'b1

Figure 5 Serial-parallel conversion principle

E

Figure 7 Baud rate control counting frequency division

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 C. Dejittering module design sram4x8:sram4x8
rx:rx
The core of dejittering module is to judge whether the CLK CLK IDLE
IDLE

possible key signals are input by external keys rather than

RSTN
SENT RSTN WIN
DOUT[7_0] DOUT[7_0]
WIN

internal flat fluctuations. Once the power level fluctuates, the RSTN RXD DATA[7_0] DATA[7_0]

counting starts. At 4800 and 9600 baud rates, the clock used is
16x baud rate, so the required dejittering time of key is 20ms, Figure 11 Receiver module diagram
and the actual dejittering time is 20-40ms. As for dejittering, RXD is a serial line for receiving data, which is often pulled
only the jitter when the key is pressed is considered, while the up to 1 in idle time, and the marking for data sending is that 1
level jitter is ignored when the key pops up, for such jitter bit of low level is received firstly, so it is required to check
doesn’t affect the circuit function and performance. The internal whether the level on the data line is low. When the detected data
interface oscillogram of dejittering module is shown as follows: line level is zero, addition counting is conducted until 8 before
receiving counter is turned on for counting, and then, the data
transmitted from RXD is sampled with an interval of 16, and at
the moment, what sampled is the stable median of the current
bit data rather than the data edge value under unsteady state.
The sampled data is shifted bit by bit. When all the 8bit data of
the data is sampled and shifted, the 8bit data is sent to SRAM
for storage once more, to complete the serial-parallel
conversion of data receiving and the data storage.
CLK

RSTN
Figure 8 Dejittering module sequence diagram
RXD 1 0 D0 D7 1
D. Transmitter module design IDLE
The transmitter module (uarttx module) includes
WIN
parallel-serial conversion transmitter (tx module) and an 8×8
BIT SRAM memory (SRAM8X8 module), and the connection DOUT[7:0] 8'hxx Data1
is generalized in uarttx module to form a complete function of
transmitter module.
Figure 12 Receiver module sequence diagram
SENT_DATA[7_0]
tx:tx

CLK CLK
sram8x8:sram CLK
RSTN
SENT
TXD[7_0] TXD
V. SIMULATION AND TEST
SENT RD DOUT[7_0] DATA[7_0]

RSTN RSTN

A. List of simulation and test functions

Figure 9 Transmitter module diagram
Function simulation and test should be carried out for each
When SENT signal has a low effectiveness, SRAM sends function to be realized in the design. The functions required to
the data to tx module which is mainly provided with a counter be realized and needing simulation and test in the design is
to generate addition counting to control timing sequence and listed as follows:
parallel-serial conversion, with the principle given as above. x Reset function: when the reset signal has a low
Through the value of counter, 10-input data selector is effectiveness, the circuit should be in the reset state: any
controlled, in which, two inputs are constantly 1 and 0, input has no response and the output is fully in reset
respectively with the function of generating a start bit 0 and state; when the reset signal turns to high level, the
pulling up the idle 1, while other 8 bits are parallel data output circuit can work normally.
by SRAM. Under the counting of counter, a bit of data is sent to x Generation of sampling rate: after frequency division
RXD data line with an interval of 16 counts, from LSB to state is determined, a fixed frequency division is
MSB. generated by the original clock to generate the
&/. sampling rate (16x baud rate).
5671
x Parallel-serial conversion transmitting: when SENT
key is pressed for dejittering firstly, 8bit parallel data
6(17 output by 8×8 SRAM is converted to serial data to
transmit.
x Serial-parallel conversion storage: when a frame of data
6(17B'$7$>B@  K[[ 'DWD

7;'  ' ' is transmitted from RXD data line, the data will be
Figure 10 Transmitter module sequence diagram converted to parallel data and then stored in 4×8bit
E. Receiver module design SRAM.
The receiver module (uarttx module) includes Bκ Simulation building and simulation results
parallel-serial conversion transmitter (rx module) and a 4×8 bit A top-level simulation excitation needs to be built for
SRAM memory (SRAM4X8 module), and the connection is testing the various functions of the simulation UART, and
generalized in uarttx module to form a complete function of appropriate signals need to be built for the input signals for the
transmitter module. purpose of simulation and also it is required to find out whether
the design is deficient. A top-level excitation document should
be written independently, and its reg signal is respectively CLK
(50min), BAUD_SEL (baud rate selection signal), RSTN


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 (entire circuit asynchronous reset), SENT (control signal
sending), RXD (serial receiving signal). For CLK signal
generation, always statement can be directly used for value
assignment, to generate periodic square wave signal, and
simulate the original clock signal on FPGA development board;
for BAUD_SEL signal, it should cooperate with RSTN signal.
When two RSTN reset signals are at a low level and continue to
RSTN ineffective pulling up, BAUD_SEL is at a low or high
level for one time respectively, it is required to check whether
Figure 13 BAUD_SEL different frequency division results
the output SAMPING signal of baud rate control module is
correct or not; for SENT signal, when RSTN is pull up The signal at the top is the 50M original clock. When
effectively, a low level signal lasting for a certain time will be RSTN is effective if it is 0, according to the value of
generated, with the time of duration greater than 20ms, to BAUD_SEL, the original clock frequency division is
prevent the module eliminated for jitter from elimination as a conducted when RSTN is ineffective, and it can be seen that the
level fluctuation; for RXD signal, it shall be generated bit by bit result after frequency division is correct. Baud rates 9600 and
from the start bit 0 from LSB to MSB, and the signal per bit 4800 have a difference of two times in frequency, and also a
should last for greater than 20us (roughly equal to the time of difference of two times in sampling rate. The simulation results
single cycle of 16x baud rate), so that RXD signal can be of parallel-serial data conversion transmitting are listed. When
simulated correctly and received for sampling. SENT is 0, after a high level is reached, the parallel 8bit data
Based on the signals built above, the following excitation output by 8×8bit SRAM will be converted to serial data to be
signals are listed as follows: transmitted via serial output data line TXD. The specific
simulation results are as follows:
Table II Excitation signal list
Name Attribute Description
CLK Reg Simulate the original clock of
Figure 14 Parallel-serial conversion transmiting
development board, with a cycle CLK signal is the output signal SAMPLING from the baud
of about 20ns rate control module, which is the sampling rate with clock
signal of 9,600×16. When RSTN is ineffective, SENT is at a
RSTN Reg Simulate the asynchronous reset low level, lasting for more than 20ms. When SENT is pulled up
after the key is pressed once more, the parallel-serial conversion data transmitting
operation is started. The listed below is the serial-parallel
BAUD_SEL Reg Simulate the selection of baud conversion recieving data and the data is stored in 4×8bit
rate by key SRAM. CLK signal is the output signal SAMPLING from the
baud rate control module, which is the sampling rate with clock
SENT Reg signal of 9600×16. If RSTN is ineefective, when RXD recieves
Simulate the key transmitting
the data transmitted from data line and such data is converted to
parallel data to be stored in SRAM, the contain signal is the
signal, needing to last for more
address signal of control SRAM.
than 20ms
RXD Reg
Simulate the serial data, lasting
Figure 15 Serial-parellel conversion recieving storage
for abour 100us per bit
TXD Reg Output the serial transmitting VI. CONCLUSION
signal This paper completes the design, function simulation and
Output the display code to Nixie experimental verification of UART module based on
DATA Reg
tube VerilogHDL language, with baud rate, parity bit and frame
length able to be flexibly configured. Also, Quartus II is used
SEL Reg Output the selected Nixie tube for design and verification on FPGA chip, and the verification
signal results show the accuracy of data transmitting. The test results
indicate the effectiveness and design universality of UART
module function. This module, as a universal UART module
First, different frequency division results after RSTN fully based on Verilog HDL linguistic performance description,
changes from effective to ineffective under different conditions can be widely applied in the design of physical layers and link
of BAUD_SEL should be listed. The above is the frequency layers of on-site serial communication in various low-speed
when BAUD_SEL=, i.e., the frequency of SAMPING signal industries.
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