APPENDIX Standard Parasitic Extraction Format (SPEF) his appendix describes the Standard Parasitic Extraction Format (SPEF). It is part of the IEEE Std 1481. C.1 Basics SPEF allows the description of parasitic information of a design (z, and c) in an ASCII exchange format. A user can read and check values in a SPEF file, though the user would never create this file manually. It is mainly 531APPENDIX © Standard Pa: tic Extraction Format (SPEF) used to pass parasitic information from one tool to another. Figure C-1 shows that SPEF can be generated by tools such as a place-and-route tool or a parasitic extraction tool, and then used by a timing analysis tool, in cir- cuit simulation or to perform crosstalk analysis. Place-and-route Timing analysis . Circuit simulation Parasitic extraction SPEF " — Crosstalk analysis Figure C-1 SPEF is a tool exchange medium. Parasitics can be represented at many different levels. SPEF supports the distributed net model, the reduced net model and the lumped capacitance model. In the distributed net model (5_nE7), each segment of a net route has its own rand c. Ina reduced net model (r_vE7), only a single reduced x and c is considered on the load pins of the net and a pie model (c-3-c) is considered on the driver pin of the net. In a lumped capacitance model, only a single capacitance is specified for the entire net. Figure C-2 shows an example of a physical net route. Figure C-3 shows the distributed net mod- _——— A Output pin Input pin (Driver) (Load) o 5 Q Oso Taput pin 2 (Load) Figure C-2 A layout of a net. el. Figure C-4 shows the reduced net model and Figure C-5 shows the Jumped capacitance model. 532Figure C-4 Reduced net (R_NET) model. t SO Figure C-5 Lumped capacitance model. Section C.APPENDIX C Standard Parasitie Extraction Format (SPEF) Interconnect parasitics depends on process. SPEF supports the specifica- tion of best-case, typical, and worst-case values. Such triplets are allowed for 8, Land c values, port slews and loads. By providing a name map consisting of a map of net names and instance names to indices, the SPEF file size is made effectively smaller, and more importantly, all long names appear in only one place. ASPEF file for a design can be split across multiple files and can also be hi- erarchical. C.2 Format The format of a SPEF file is as follows. header_definition [ name_map [ power _definition ] [ external_definition ] { define definition internal_definition The header definition contains basic information such as the SPEF version number, design name and units for &, and c. The name map specifies the mapping of net names and instance names to indices. The power definition declares the power nets and ground nets. The external definition defines the ports of the design. The define definition identifies instances, whose SPEF is described in additional files. The internal definition contains the guts of the file, which are the parasitics of the design. Figure C-6 shows an example of a header definition. 534Format. Section C.2 *SPEF "IEEE 1481-1998" *DESIGN "ddrphy" “DATE "Thu Oct 21 00:49:32 2004" *VENDOR "SGP Design Automation” “PROGRAM "Galaxy-RCXT" *VERSION "V2000.06" *DESIGN_FLOW "PIN CAP NONE" "NAME. SCOPE, LOCAL" “DIVIDER / “DELIMITER *BUS_DELIMITER [] *T_UNIT 1.00000 NS *C_UNIT 1.00000 FF *R_UNIT 1.00000 OHM *L_UNIT 1.00000 HENRY // A comment starts with the two characters “//”. i TCAD_GRD FILE /ead/I31v/galaxy-rext/ 1013s6mI_fog.nxtged i TCAD_TIME_STAMP Tuc May 14 22:19:36 2002 Figure C-6 A header definition. *SPEF name specifies the SPEF version. *DESIGN name specifies the design name. *DATE string specifies the time stamp when the file was created. *VENDOR string 535APPENDIX © Standard Pa: tic Extraction Format (SPEF) specifies the vendor tool that was used to create the SPEF. *PROGRAM string specifies the program that was used to generate the SPEF. “VERSION string specifies the version number of the program that was used to create the SPEF. *DESIGN_FLOW string string string... specifies at what stage the SPEF file was created. It describes information about the SPEF file that cannot be derived by reading the file. The pre- defined string values are: 536 ExTERNAL_Loaps : External loads are fully specified in the SPEF file. EXTERNAL_stews : External slews are fully specified in the SPEF file. FuLL_connecrivity : Logical netlist connectivity is present in the SPEF. MrssING_NETs : Some logical nets may be missing from the SPEF file. NETLIST_TYPE_vERILoG : Uses Verilog HDL type naming conven- tions. NETLIST_T¥PE_vupue7 : Uses VHDLS7 naming convention. NETLIST_TYPE_vupL93 : Uses VHDL9S netlist naming conven- tion. NETLIST_TYPE_eDrF : Uses EDIF type naming convention. ROUTING_CONFIDENCE positive integer : Default routing confi- dence number for all nets, basically the level of accuracy of the parasiticsFormat. Section C.2 * ROUTING_CONFIDENCE_ENTRY positive integer string : Supple- ments the routing confidence values. * NAME _scopE LocaL | FLAT : Specifies whether paths in the SPEF file are relative to file or to top of design. © SLEW_THRESHOLDS low_input_threshold_percent gh_input_threshold percent : Specifies the default input slew threshold for the design. * PIN_CAP NONE | INPUT_oUTPUT | INPUT_oNLY : Specifies what type of pin capacitances are included as part of total capacitance. The default is znput_ourpor. The line in the header definition: *DIVIDER / specifies the hierarchy delimiter. Other characters that can be used are , ; and/ *DELIMITER : specifies the delimiter between an instance and its pin. Other possible char- acters that can be used are .,/, ; or |. *BUS DELIMITER [ ] specifies the prefix and suffix that are used to identify a bit of a bus. Other possible characters that can be used for prefix and suffix are |, |<, .and },), >. *T_UNIT positive integer NS | PS specifies the time unit. *C_UNIT positive integer PF | FF 537APPENDIX CG Standard Parasitic Extraction Format (SPEF) specifies the capacitance unit. *R_UNIT positive integer OHM | KOHM specifies the resistance unit. *L_UNIT positive integer HENRY | MH | UH specifies the inductance unit. A comment in a SPEF file can appear in two forms. // Comment - until end of line. /* This comment can extend across multiple lines */ Figure C-7 shows an example of a name map. It is of the form: *NAME_MAP *positive_integer name *positive_integer name The name map specifies the mapping of names to unique integer values (their indices). The name map helps in reducing the file size by making all future references of the name by the index. A name can be a net name or an instance name. Given the name map in Figure C-7, the names can later be referenced in the SPEF file by using their index, such as: *364:D // D pin of instance J/ medll_write data/writel9/d_out_2x reg 19 *11172:¥ //¥pinofinstance ~ ~ // Tie_VSSQ_assign_buf_318_N_1 538Format. Section C.2 “NAME_MAP 1 memelk #2 memelk_2x #3 reset_ “4 refresh *5 resyne *6 int d_out{63] *7 int_d_out[62] #8 int_¢_out[61] *9 int_d_out[60] *10 imt_d_out[59] *11 int _d_out{58] *12imt_d_out[57] 364 medll_write_data/writel 9/d_out_2x_reg_19 +366 medll_write_data/write20/d_out_2x_reg_20 ¥368 medll_write_data/write21/d_out_2x_reg_21 +5423 medll_read_data/read? l/capture_data[53] 5426 medll_read_data/read? l/capture_pos_0[21] #11172 Tie VSSQ assign buf 318.N.1 #14954 test_se_15 $0 +14955 wr_sdly_course_ene{0]_LO 14956 wr_sdly_course_ene[0] L0_1 14957 wr_sdly_course_ene[0] SO Figure C-7 A name map. *5426:116 // Internal node of net // medll_read data/read21/capture pos 0[21] *5426:10278 // Internal node of net *5426 *12 // The net int_d out [57] The name map thus avoids repeating long, names and their paths by using, their unique integer representation 539APPENDIX CG Standard Parasitic Extraction Format (SPEF) The power definition section defines the power and ground nets. *POWER NETS net_name net_name... *GROUND_NETS net_name net_name... Here are some examples *POWER_NETS VDDQ *GROUND_NETS VSSQ The external definition contains the definition of the logical and physical ports of the design. Figure C-8 shows an example of logical ports. Logical ports are described in the form: *PORTS port_name direction { conn_attribute } port_name direction { conn_attribute } where a port_name can be the port index of form ‘positive _integer. The direction is 1 for input, o for output and 5 for bidirectional. Connection attri- butes are optional, and can be the following; * *cnunber number : Coordinates of the port. * ‘*nvar_value : Capacitive load of the port. * *spar_velue par_value : Defines the shape of the waveform on the port. * *pce11_type : Defines the driving cell of the port. Physical ports ina SPEF file are defined using: *PHYSICAL_PORTS pport_name direction { conn_attribute } pport name direction { conn attribute } 540Format. Section C.2 “PORTS “LL “21 “31 “41 “SI *6L “71 “81 “91 “101 “HL “4500 “4510 "4520 *453 0 "4540 "4550 “4560 Figure C-8 An external definition. The define definition section defines entity instances that are referenced in the current SPEF file but whose parasitics are described in additional SPEF files. *DEFINE instance_name { instance_name ) entity_name *PDEFINE physical instance entity name The *pogrine is used when the entity instance is a physical partition (in- stead of a logical hierarchy). Here are some examples. *DEFINE core/ulddrphy core/u2ddrphy “ddrphy” This implies that there would be another SPEF file with a pzsten value of aarpny - this file would contain the parasitics for the design carpny. It is S541APPENDIX C Standard Parasitic Extraction Format (SPEF) possible to have physical and logical hierarchy. Any nets that cross the hi- erarchical boundaries have to be described as distributed nets (D_neT). The internal definition forms the guts of the SPEF file - it describes the para- sitics for the nets in the design. There are basically two forms: the distribut- ed net, 0_n=7, and the reduced net, »_vev. Figure C-9 shows an example of a distributed net definition. “D_NET 5426 0.899466 4CONN 41 *14212:D L*C 21.7150 79.2300 “1 *14214:Q 0 *€ 21.4950 76.6000 *D DFFQX1 : 10278 *5290:8775 0.217446 54 0.0105401 5426:10278 #5266:9481 0.0278254 4 *5426:10278 45116:9922 0.113918 10278 0.529736 0278 *14212:D 0.340000 10278 *5426:10142 0.916273 3. #5426:10142 *14214:Q 0.340000 *END Figure C-9 Distributed net parasitics for net *5426. In the first line, *D_NET *5426 0.899466 *5426 is the net index (see name map for the net name) and 0.299466 is the total capacitance value on the net. The capacitance value is the sum of all capacitances on the net including cross-coupling capacitances that are as- sumed to be grounded, and including load capacitances. It may or may not 542Format. Section C.2 include pin capacitances depending on the setting of >in cae in the “DEsIGN_FLow definition. The connectivity section describes the drivers and loads for the net. In: *CONN *I *14212:D I *C 21.7150 79.2300 *I *14214:0 0 *C 21.4950 76.6000 *D DFFOX1 *r refers to an internal pin (* is used for a port), *14212:0 refers to the p pin of instance «14212 which is an index (see name map for actual name). “tr” says that it is a load (input pin) on the net. “o” says that it is a driver (output pin) on the net. *c and °p are as defined earlier in connection attri- butes - *c defines the coordinates of the pin and “p defines the driving cell of the pin. ‘The capacitance section describes the capacitances of the distributed net. The capacitance unit is as specified earlier with “c_onr7. *5290:8775 0.217446 *16:3754 0.0105401 *5266:9481 0.0278254 *5116:9922 0.113918 278 0.529736 The first number is the capacitance identifier. There are two forms of ca- pacitance specification; the first through fourth are of one form and the fifth is of the second form. The first form (first through fourth) specifies the cross-coupling capacitances between two nets, while the second form (with id 5) specifies the capacitance to ground. So in capacitance id 1, the cross- coupling capacitance between nets *5426 and *5290 is 0.217446. And in ca- pacitance id 5, the capacitance to ground is 0.529726. Notice that the first node name is necessarily the net name for the p_vst that is being described. The positive integer following the net index (1027¢ in “5426:10272) speci- fies an internal node or junction point. So capacitance id 4 states that there 543,APPENDIX C Standard Parasitic Extraction Format (SPEF) is a coupling capacitance between net “3226 with internal node 10278 and net *5115 with internal node 9922, and the value of this coupling capaci- tance is 0.1 16. The resistance section describes the resistances of the distributed net. The re- sistance unit is as specified with *R_uyzr. *RES 1 *5426:10278 *14212:D 0.340000 2 *5426:10278 *5426:10142 0.916273 345, 42 *14214:9 0.340000 The first field is the resistance identifier. So there are three resistance com- ponents for this net. The first one is between the internal node *5426:10278 to the p pin on *14212 and the resistance value is 0. 24. The capacitance and resistance section can be better understood with the xc network shown pic- torially in Figure C-10. *16:3754 — *5266:9481 *5290: ony oe 9 *5116:9922 ‘ #14214 Q 3 DFFQX1 { *5426:10278 #14212 D *5426:10142 Figure C-10 A&C for net *5426. Figure C-11 shows another example of a distributed net. This net has one driver and two loads and the total capacitance on the net is 2. 69358. Figure C-12 shows the xc network that corresponds to the distributed net specifi- cation.Format. Section C.2 *“D_NET *5423 2.69358 “CONN 1 414207:D 1 *C 21,7450 94.3150 *1*14205:D 1 *C 21.7450 90.4900 *1*14211:Q O *C 21.4900 83.8800 *D DFFQX1 10107 *547:12722 0.202686 2.*5423:10107 *5116:10594 0.104195 123:10107 *5233:9552 0.208867 123:10107 *5265:9483 0.02258 10 5 *5423:10107 *267:9668 0.0443454 6 *5423:10107 *5314:7853 0.120589 7 *3423:10212 *2109:996 0.029374 123:10212 *5187:7411 0.526945 123:14640 *6577:10075 0.126929 10 *5423:10213 1.30707 “RES 1 *5423:10107 *5423;10212 2.07195 2. *5423:10107 *5423:10106 0.340000 3. *5423:10212 *5423:10211 0.340000 10212 *5423:14640 1.17257 5 *5423:14640 *5423:10213 0.340000 6 *5423:10213 *14207:D 0.0806953 7 *5423:10211 *14205:D 0.210835 8 *5423:10106 *14211:Q 0,0932139 “END Figure C-11 Another example of a distributed net *5423. In general, an internal definition can comprise of the following specifica- tions: * p_ver: Distributed RC network form of a logical net. 8_Ner: Reduced RC network form of a logical net. * p_pwer: Distributed form of a physical net. n_pnet: Reduced form of a physical net. 545APPENDIX C Standard Par: sitic Extraction Format (SPEF) 7 #14207 AW—D es ge € 2 ¢€8 “14211 $ $ 5 *14205 oo Ea 2 > Q a *5423:10212 DFFQX! c4 *5116:10594 0-4 *5233:9552 o *5187:7411 oe *267:9668 *5265:9483 o> 1 *5314:7853 0 *547:1272) Figure C-12 RC network for D_NET *5423. Here is the syntax. *D_NET net_index 7 ection | [ cap_section ] [ res_section ] [ inductance_section ] *END 1_cap [*V routing_confidence ] co *R_NET net_index ( drive: 1_cap [ *V routing confidence ] ¢ reduction |Format. Section C.2 *END *D_PNET pnet_index total_cap [*V routing_confidence ] fpconn_section ] [ peap_section ] [ pres_section ] [ pinduc_section | *END *R_PNET pnet_index total_cap [*V routing_confidence ] ( pdriver_reduction ] *END The inductance section is used to specify inductances and the format is simi- lar to the resistance section. The *v is used to specify the accuracy of the parasitics of the net. These can be specified individually with a net or can be specified globally using the “pesrcn_FLow statement with the ROUTING CONFIDENCE value, such as: *DESIGN_FLOW “ROUTING _CONFIDENCE 100” which specifies that the parasitics were extracted after final cell placement and final route and 3c extraction was used. Other possible values of rout- ing confidence are: * 10: Statistical wireload model + 20: Phy * 30: Physical partitions with locations, and no cell placement sical wireload model ¢ 40: Estimated cell placement with steiner tree based route * 50: Estimated cell placement with global route * 60: Final cell placement with steiner route * 70: Final cell placement with global route * 80: Final cell placement, final route, 24 extraction * 90: Final cell placement, final route, 2.54 extraction 547APPENDIX C Standard Parasitic Extraction Format (SPEF) + 100: Final cell placement, final route, 20 extraction A reduced net is a net that has been reduced from a distributed net form. There is one driver reduction section for each driver ona net. The driver re- duction section is of the form: *DRIVER pin_name *CELL cell_type // Driver reduction: one such section for each driver // of net: *C2_R1_Cl cap_value res_value cap_value *LOADS // One following set for each load on net: *RC pin name rc value *RC pin_name rc ‘The *c2_n1_c1 shows the parasitics for the pie model on the driver pin of the net. The rc_value in the “re construct is the Elmore delay (x*c). Figure C-13 shows an example of a reduced net SPEF and Figure C-14 shows the *R_NET *1200 2.995 “DRIVER *1201:Q “CELL SEDFFX1 *€2_R1_C1 0.511 2.922 0.106 “LOADS ARC *1202:A 1.135 ARC *1203:A 0.946 “END Figure C-13 Reduced net example. RC network pictorially. A lumped capacitance model is described using either a *>_neT or a “R_NET construct with just the total capacitance and with no other information. Here are examples of lumped capacitance declarations. 548Format Section C.2 *1201 RI SEDFFX1 Figure C-14 Reduced net model. *D_NET *1 80.2096 *CONN *I *2:Y 0 *L 0 *D CLEMX2X2 *P*10*LO *END *R_NET *17 58.5204 *END Values in a SPEF file can be in a triplet form that represents the process variations, such as: oO. is the best-case value, 0.269 is the typical value and 0.300 is the worst-case value. 549APPENDIX C Standard Parasitic Extraction Format (SPEF) C.3 Complete Syntax This section describes the complete syntax! of a SPEF file. A character can be escaped by preceding with a backslash (\), Comments come in two forms: // starts a comment until end of line, while /* . . .*/ is a multi-line comment. In the following syntax, bold characters such as (, [ are part of the syntax. All constructs are arranged alphabetically and the start symbol is F_file. jentifier | Sidentifier><; ‘imx_bus_delim>() jelim> ] bus_delim a “BUS_DELIMITER prefix bus delin [ suffix bus_delin cap_elem cap_id node_name par value p_id node_name node_name2 par_value cap_id: os_integer *L par_value *c_UNIT pos_number cap_unit cap_sec :1= "CAP cap_elem { cap_elem } cap_unit ::- BF | FF index | name ell_type 1. Syntax is reprinted here with permission from IEEE Std. 1481-1999, Copyright 1999, by IEFE. Alll rights reserved. 550Complete Syntax SECTION C counber (real_component imaginary component ) complex_par_value ::- cnumber | number | cnunberscnumbericnutber | nunberinumbersnumber cont pos integer conn_attr ::= coordinates | cap_load | slews | driving_cell conn_def :: *P external connection direction | conn_attr } | *E internal_connection direction { conn_attr } conn_sec : *conN conn_def { conn_def } { internal_node_coord } coordinates ::= "Cc number number date : “DATE gstring decimal ::= [si gn]() [) define_def ::= define_entry { define_ent: define entry : “DEFINE ins | *PDEFINE phy name { inst_name } entity ical_inst entit gn_flow “DESIGN_FLOW string [ 4: “DESIGN ¢ ing direction | Blo driver cell *CELL cell type driver_palr i: “DRIVER pin_narie 551APPENDIX CG Standard Parasitic Extraction Format (SPEF) driver_reduc driver_pair driver_cell pie model load_desc driving_cell ::- *D cell_type ane: “D_NET net_re [ conn_sec ] [ cap_sec ] [ res_sec [ induc_sec ] “END total_cap [ routing_conf ] dpnet :: *D_PNET pnet [ peonn_sec ] [ peap_sec ] [ pres_sec ] [ pindac_sec ] “END ef total_cap | routing conf ] entity string escaped_char \ escaped char _set ::= | ” Ele |_connection ort_nane | pport_name external_def i: port_def | physical port_d | physical _port def | fraction | exp ign ].(} 552Complete Syntax SECTION C ground_net_def “GROUND_NETS net_name { net_name } nchar t=. 1/121 | neader_def : SPEF_version design_name date vendor program _name program_version design_flow hierarchy _div_def pin_delim def bus_delim_def unit_det hie * DIVIDER hier_delim nier_delim :t= hchar identifier ::= { identifier_char | salpha> | I imaginary component ::= number Index ::= " indue_elem: induc_id node_name node_name par_value induc_id : pos_integer induc_scale : L_UNIT pos_number induc_unit induc _sec ::= "INDUC induc elem { induc elem } Inducunit := HENRY | MH | Ua 553‘APPENDIX GC Standard Parasitic Extraction Format (SPEF) inst_name ::= index | path integer ::= [ sign ]{} interna, connection in_name | pnode_ref internal_def ::= nets { nets } internal node coord :: *N internal node name coordinates inter _node_name internal_pnode_coord ::= *N internal_pnode_name coordinates interna pnod=_name ::= load_dese *LOADS rc_desc [ ro_desc } lower tis a-z mapped_item identifier | bit_ice: | path | name | physic name ::=qstring | identifier name map 1:= *NAME MAP nave map entry { name map entry } name_map_entry ::= Index mapped_item neg_sign nets : q_net | rnet | d_pnet | r_pnet net_nane ::+net_ref | pnet_ref net_ref ::= index | path 554Complete Syntax SECTION C node_name external_connection | internal_connection | internal node name | pnode_ref node_name2 node_name | | number ::= integer | float partial path partial physical _ref ::= float | <£loat>:<£loat>:] {] peap_elem cap_id pnode name par_value | cap_id pnode_name pnode_name: par_value poap_sec :1= *€AP peap_elem | pcap_elen | poonn det *B pexternal_connection direction ( conn_attr } | #1 internal_connection direction { conn_attr } pconn_sec *OONN pconn_def { pconn_def } | internal_pnode coord } air onnection pdriver_| *DRIVER internal ( pdriver_reduc pdriver_pair driver_cell pie_model load_desc pexternal_connection ::= pport_name physical_inst index | physical_ref 555APPENDIX CG Standard Parasitic Extraction Format (SPEF) physi name name physical port_d “PHYSICAL PORTS pport entry { pport entry } physical_ref ::= (} pie_model : *€2_RI_Cl per value gar v ue par_value pin ::= index | bit_identifier pinduc_elem ::= induc_id pnode_name pnode_name par_value pinduc_sec INDUC pinduc_elem { pinduc_elem } pin_delim pin_delim_def *DELIMETER pin_delim pin_name ::~ pnet_ref ::= index | physical_ret pnet_ref2 ::= pnet_ref pnode ::= index | name pnode_na pexternal_connection | intern nnection | internal _pnode name | pnode_ref pnode_name2 :i= pnode_name | | Spnet_ref2> 556Complete Syntax SECTION C pole : complex_par_value pole_desc ::= *Q pos_integer pole | pole pole residue desc ::= pole desc residue dese port_def “PORTS port_entry { port_entry } pos_decimal ::= (}. {} port index | bit identifier port_ent = port_name direction { conn_attr } port_nane ] pos_exp pos_radix exp char integer pos_float : pos_decimal | pos_fraction | pos_exp pos_fraction ::= | pos_integer ::= (} pos_number ::= pos_integer | pos_float pos_radix os integer | pos decimal | pos fraction sign po power def : power_net_def [ ground net_def ] | ground_net_det power_net_de * POWER_NETS net_name { net_name } ppor’ index | name pport_entry ::= pport_name direction { conn_attr } 557‘APPENDIX GC Standard Parasitic Extraction Format (SPEF) pport_name : ]:: time_scale ::= *f_UNTT pos_number time unit time_unit ::= NS | PS total_cap ::~ par_value unit_def : cale res_scale induc_scale time_scale cap upper r= A-ZAPPENDIX C Standard Pat vendor $= “VENDOR string ris space | tab iti Extraction Format (SPEF)Bibliography 1. [ARN51] Amoldi, W.E., The principle of minimized iteration in the solution of the matrix eigenvalue problem, Quarterly of Applied Mathematics, Vol- ume 9, pages 17-25, 1951. 2, [BES07] Best, Roland E., Phase Locked Loops: Design, Simulation and Appli- cations, McGraw-Hill Professional, 2007. 3. [BHA99] Bhasker, J., A VHDL Primer, 3rd edition, Prentice Hall, 1999. 4, [BHA05] Bhasker, J. A Verilog HDL Primer, 3rd edition, Star Galaxy Pub- lishing, 2005. a [CEL02] Celik, M., Larry Pileggi and Altan Odabasioglu, IC Interconnect Analysis, Springer, 2002. 6. [DALO8] Dally, William J,, and John Poulton, Digital Systems Engineer ing, Cambridge University Press, 2008. 7. [ELG05] Elgamel, Mohamed A. and Magdy A. Bayoumi, Interconnect Noise Optimization in Nanometer Technologies, Springer, 2005.BIBLIOGRAPHY 8. [KANO3] Kang, S.M. and Yusuf Leblebici, CMOS Digital Integrated Cir- cuits Analysis and Design, 3rd Edition, New York: McGraw Hill, 2003. 9. [LIB] Liberty Users Guide, available at “http:/ /www.opensourceliberty.org” 10. [MONS51] Monroe, M.E., Theory of Probability, New York: McGraw Hill, 1951 11. [MUK86] Mukherjee, A., Introduction to nMOS & CMOS VLSI Systems Design, Prentice Hall, 1986. 12. [NAG75] Nagel, Laurence W., SPICE2; A computer program to simulate semiconductor circuits, Memorandum No. ERL-M520, University of Cali- fornia, Berkeley, May 1975. 13. [QIA94] Qian, J., S. Pullela and L. Pillegi, Modeling the “Effective Capaci- tance” for the RC Interconnect of CMOS Gates, IEEE Transaction on CAD of ICS, Vol 13, No 12, Dec 94 14. [RUB83] Rubenstein, J., P. Penfield, Jr., and M. A. Horowitz, Signal delay in RC tree networks, IEEE Trans. Computer-Aided Design, Vol. CAD-2, pp. 202-211, 1983. 15. [SDCO7] Using the Synopsys Design Constraints Format: Application Note, Version 1.7, Synopsys Inc., March 2007. 16. [SRI05] Srivastava, A., D. Sylvester, D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Springer, 2005. 56212-value delay 481 Lb value delay 481 5d extraction 547 2d extraction 547 2value delay 481 3d extraction 548 S-value delay 431 A absolute path delay 474 absolute port delay 475 AC noise rejection 156 AC specifications 318 AC threshold 159 accurate RC 7 active clock edge 277 active edge 61, 236 active power 88, 412 additional margin 32 additional pessimism 32 aggressor net 165, 167 aggressors 149 all-clocks 449 allinputs 449 alloutputs 449 allregisters 449 annotator 496 approximate RC 8 area specification 94 Index area units 100 asyne default path group 279 asynchronous control 277 asynehronous design 5 asynchronous input are 74 asynchronous inputs 60 B backannotation 467, 496 backslash 550 backward-annotation 485 balanced tree 108 BCF 41,420 best-case fast 41, 227, 370, 420 best-case process 534 best-case tree 108 best-case value 549 bidirectional skew timing check 483 black box 73 byte lane 121 c C value 534 CAC 336, 341 capacitance identifier 543 capacitance section 543 capacitance specification 543 capacitance unit. 100, 538, 543INDEX, capacitive load 540 capture clock 172, 173, 174, 367, 370 capture clock edge 326 capture flip-flop 36 CCB 80 CCS 47,76 CCS noise 80 CCS noise models 85 CCSN 80) cesn_first_stage 82, 84, 85,86 cesn_last stage 84,85, 86 cell check delays 369 cell delay 368, 467, 469 cell instance 473 cell library 12, 113, 153, 392 cell placement 547 cell rise 52 channel connected blocks 80 channel length 366 characterization 54 check event 482 circuit simulation 532 clock cycle 318 clock definitions 2 clock domain 36, 273, 435 clock domain crossing 10, 445 clock gating 365, 406, 413) clock gating cheek 192, 394 clock latency 30, 188 clock period jitter 31 clock reconvergence pessimism 373 clock reconvergence pessimism removal 370 clock skew 30 clock source 181 clock specification 181 clock synchronizer 10, 38, 445 clock tree 6, 236,370 clock tree synthesis 189 clock uncertainty 186,335 clock gating default 399 closing edge 377 CMOS 5 CMOS gate 16 CMOS inverter 16 CMOS technology 15 combinational cell 33 comment 538 common base period 306 common clock path 370, 375 common path pessimism 370, 375 common path pessimism 564 removal 370 common point 370 composite current source 76 COND 72 conditional check 510 conditional hold time 510 conditional path delay 477, 479 conditional propagation delay 502 conditional recovery time 511 conditional removal time 513 conditional setup time 508 conditional timing check 482 connection attribute 540), 543 connectivity section 543 constrained pin 385,392 constrained_pin 63 controlled current source 115 coordinates 540 coupled nets 118 coupling capacitance 118, 149, 544 CPP 370 CPPR 370 create clock 182, 453 create_generated_clock 190, 454 create_voltage_area 465 critical nets 120 critical path 6, 247 cross-coupling capacitance 542, 543, crosstalk 2,121 crosstalk analysis 147, 532 crosstalk delta delay 149 crosstalk glitch §3, 160 crosstalk noise 147, 163 CRPR 370 current loops 102 current spikes 148 current_design 450 current_instance 448 cyele stealing 377 D D_NET 532, 542 DAC interface 360 data to data check 385 data to data hold check 385, data to data setup check 385 DC margin 87, 154 DC noise analysis 156 DE noise limits 153 DC noise margin 153, 157 DC transfer characteristics 153,dc_current 82, 153 DDR xix DDR interface 121 DDR memory 10 DDR SDRAM 317 DDR SDRAM interface 341 deep n-well 177 default conditional path delay 479 default path delay 477 default path group 209 default wireload model 112 define definition 534, 541 delay 474 delay specification 480 delay-locked loop 336 derate specification 374 derating 367 derating factor 96, 97, 368 design name design rules Design Under Analysis 180 detailed extraction 104 device delay 477, 519 device threshold 41 diffusion leakage 92 distributed delay 470 distributed net 532, 542 distributed RC 149,545 distributed RC tree 103 distributed timing 477 DLL 336, 343, 349 DQ 341 DQS 341 DQS strobe 341 drive strength 211 driver pin 532, 548 driver reduction 548 driving cell 540 DSPF 113 DUA 3,180, 317, 336 duty eyele 181 E early path 35 ECSM 47,76 edge times 181 EDIF 536 effective capacitance 75 effective current source model 76 electromigration 13 e-limit 476 INDEX, Elmore delay 548 enclosed wireload mode 110 endpoint 207 entity instance 541 environmental conditions 96 error limit 476 escaped 550 escaped character 550 exchange format 531 expr 448 external definition 534, 40 external delay 206 external input delay 204 external load 536 external slew 536 extraction 119 extraction tool 7, 119 extrapolation slope 107 PF fall delay 51 fall glitch 152, 159 fall transition 51 fall_constraint 64 fall_glitch 154 fall_transition 51 false path 11, 38, 179, 272, 444 fanouts 21 fast clock domain 289 fast process 39, 96 file size 534 final route 7,547 flip-flop 3 footer 414 forward-annotation 469, 471, 485 FPGA 5 frequency histogram 246 function specification 95 functional correlation 162 functional failures 5 functional mode 220 a gate oxide tunneling 92 gating eell 394 gating pin 394 gating signal 394 generated clock 190, 328, 396, 435 generic 485 generic name 500 get_cells 450 565INDEX, get_clocks 450 get_lib_cells 451 getlib_pins 451 get_libs 451 get_nets 451 get_pins 451 get_ports 451 gliteh 159, 470 glitch analysis 10, 147 gliteh height 153 glitch magnitude 151, 153, 161 glitch propagation 159 gliteh width 87, 153 global process variation 423 global route 7, 547 ground net 540 grounded capacitance 102, 118, 151, 164 group_path 455 guard ring 177 H half-cycle path 274, 442 hardware description language 467 header 414 header definition 534 header section 471 hierarchical block 175, 472 hierarchical boundary 110, 542 hicrarchical instance 473, hierarchical methodology 119 hierarchy delimiter 537 hierarchy separator 472, 473 high transition glitch 159 high Ve 92, 416 high-fanout nets 443 hold 62 hold check 3, 227 hold check are 60 hold gating check 400 hold multieyele 262, 289 hold multiplier 269 hold time 509 hold timing check 248, 470, 474, 482, 510 hold_falling 393 hold_rising 393 I ideal clock tree 30 ideal clocks 9 566 ideal intereonnect 7, 9, 490 ideal waveform 25 IEEE Sid 1076.4 499 IEEE Std 1364 496 IEEE Std 1481 531 IEEE Sid 1497 468 IMD 431 inactive block 414 inductance 102, 547 inductance section 547 inductance unit 538 inertial delay 157 input arrival times 240 input constraints 319 input delay constraint. 203 input external delay 255 input glitch 157 input specifications 206 input_threshold_pet_fall 25 input_threshold_pet_rise 25 insertion delay 188, 236 instance name 538 inter-clock uncertainty 187 interconnect capacitance 102 interconnect corner 418, 419 interconnect delay 467, 469, 477, 479 interconnect length 107 interconnect modeling 471 interconnect parasitics 101, 534 interconnect path delay 518 interconnect RC 419 interconnect resistance 102, 120, 419 interconnect trace 101, 102 inter-die device variation 423 inter-metal dielectric 431 internal definition 534, 542, 545 internal pin 543 internal power 83 internal switching power 88 intra-die device variation 424 10 buffer 43 10 constraints 218 10 interface 337 10 path delay 475,477 10 timing 179 IR drop 366 is needed 82 J jitter 31K kx temp 99 k volt 98 k-fnetors 96, 97 L L value 584 label 474, 485 latch 377 late path 35 latency 40 launch clock 174, 370 launch edge 303 launch flip-flop 36 layout extracted parasities 119 leakage 19, 415 leakage power 88, 92, 412, 416 Liberty 26, 43,94 library cell 43 library hold time 253 library primitive 471 library removal time 279 library time units 100 linear delay model 46 linear extrapolation 107 list 448 load capacitance 46, 542 Toad pin 532 local process variation 424 logic optimization 5 logic synthesis 485 logic-0 19 logic-1 19 logical hierarchy 541 logical net. 536, 545 logical port 540 longest path 34 lookup table 48, 64 low transition glitch 159 low Vt_ 98, 416 lumped eapacitance 532, 548 M master clock 190, 328 max capacitance 215 max constraint 229 max output delay 327 max path 34,172 max path analysis 166 max path cheek 323 max timing path 229 INDEX, max transition 215 max_transition 58 maximal leakage 41 maximum delay 482, 502 maximum skew timing check 470 metal etch 430 metal layers 101 metal thickness 431 Miller capacitances 82 Miller effect. 76 miller_eap_fall 82 miller_eap_rise 82 min constraint 250 min output delay 327 min path 34, 172 min path analysis 166 min path check 323 minimum delay 482, 502 minimum period timing check 470 minimum pulse width timing check 470 MMMC 421 MOS devices 92 MOS transistor 15 multi Vt cell 416 multicyele 444 multicycle hold 264 multieycle path 179, 260, 292 multicycle setup 254 multicycle specification 285, 335, 390 multi-mode multi-eorner 421 multiple aggressors 160 N name directory 119 name map 534, 538, 542 narrow glitch 155 negative bias 417 negative crosstalk delay 166, 167 negative fall delay 170 negative hold check 65 negative rise delay 170 negative slack 246 negative unate 33, 59 negative_unate 52 neighboring aggressors 149 neighboring signal 102 net 101 net delay 368, 479, 518 net index 542 net name 538 567INDEX, netlist connectivity 536 network latency 188 NLDM 47,75, 393 NMOS 15 NMOS device 414 NMOS transistor 16 no change timing check 471 no-change data check 391 no-change hold time 516 no-change setup time 516 no-change timing check 483 no-change window 391 noise 2, 83 noise immunity 87 noise immunity model 87 noise rejection level 155 noise tolerance 155 noise_immunity_above_high 87, 159 noise_immunity_below_low 87, 159 noise_immunity_high 87, 159 noise_immunity_low 87, 159 nom_process 96 nom temperature 96 nom_voltage 96 nominal delay 502 nominal temperature 41 nominal voltage 41 non-common 174 Non-Linear Delay Model 47 non-monotonic 45 non-sequential cheek 392 non-sequential hold check 393 non-sequential setup check 393 non-sequential timing cheek 365 non-unate 34, 68 Newell 417 ° OCV 366 OCV derating 371 on.chip variation 365, opening edge 377 operating condition 39, 96, 472 operating mode 418 output current. 79) output external delay 257 output fall 56 output high drive 21 output low drive 21 output rise 56 output specifications 206 568 output switching power 88 output_current_fall 79 output_currentorise 80 output_threshold_pet_fall 25 output_threshold_pet_rise 26 output_voltage fall 83 output_voltage rise 83 overshoot 87 overshoot glitch 152, 159 P parallel PMOS 17 parasitic corners 418 parasitic extraction 532 parasitic information 531 parasitic interconnect 104 parasitic RC 7 path delay 34, 496 path exception 444 path groups 209 path segmentation 224 pathpulse delay 475 pathpulsepercent delay 477 paths 207 PCB interconnect 349 period 181, 513 period timing check 483 physical hierarchy 542 physieal net 532, 545 physieal partition 541, 547 physical port 540 physical wireload 547 pie model 532, 548 pi-model 104 pin capacitance 20, 44, 537, 543 pin-to-pin delay 470 place-and-rouie 532 PLL 10 PMOS 15 PMOS device 415 PMOS transistor 16 point-to-point delay 471 port delay 477,479, 517 port slew 534 ive crosstalk delay 166, 167 ve fall delay 170 ive glitch 150 positive rise delay 170 positive slack 247 positive unate 33,59 positive uate 56post-layout phase 104 power 12 power definition 534, 540 power dissipation 19 power gating 414 power gating cell 415 power net 540 power unit 100 pre-layout phase 104 process 534 process operating condition 482 process technology 12 propagated_noise 158 propagated noise_high 83 propagated noise low &3 propagation delay 25, 477, 502 pull-down structure 17 pull-up resistance 21 pull-up structure 17 pulse propagation 469, 470 pulse rejection limit 476, 481 pulse width 476, 514 pulse width check 66 PVT 39,336 PYT condition 366, 371 PVT corner 418 P-well 417 Q quarter-cycle delay 343, R R value 534 RNB 592,542 RC 7, 103 RC interconneet 103 RC network 23, 544, 548 RC time constant 23 RC tree 108 read cycle 343 receiver pin capacitance 76 receiver_eapacitancel. fall 77,78 receiver_eapacitancel_rise 78 receiver_eapacitance2 fall 77, 78 rocoiver_eapacitance2 rise 77, 78 recovery 66 recovery check 435 recovery check are 60 recovery time 66,511 recovery timing cheek 279, 470, 483 reduced format 115 INDEX, reduced net 532, 542, 548 reduced RC 545 reduced representation 118 reference time 80 related clocks 305 related pin 385,392 related_pin 63 removal 66 removal check are 60 removal time 66,512 removal timing check 277, 470, 483 resistance identifier 544 resistance section 544, 547 resistance unit 100, 538, 544 resistive tree 103 retain definition 47 retain delay 478 rise delay 51 rise glitch 152, 159 rise transition 51 rise constraint 64 rise_glitch 154 rise_transition 51 rising edge 69 limit 476 root-mean.squared 160 routing confidence 536 routing halo 177 RSPF 113 RTL 5 s same.eycle checks 385,389 SBPF 113 scan mode 65,162 scenarios 421 SDC xvii, 4,447 SDC commands 447 SDC file 447 SDF xvi, 94, 418, 468 sdf_cond 72,95 segment 101 sogmonted wireload mode 110 selection groups 113 sequential are 74 sequential coll 33, 60 series NMOS 17 set 448 set_case_analysis 219, 461 sot clock gating. check 295,407,412, & 569INDEX, set_clock_groups 455 set_clock latency 31, 188, 236, 456 set_clock_sense 456 set_clock transition 186, 456 set clock uncertainty 31, 186, 456 set_data_check 385,457 set_disable_timing 219, 434, 457 set_drive 210, 461 set_driving_cell 210, 461 set_false_path 38,219, 272, 457 set fanout load 462 sei_hierarchy_separator 448 set_ideal_latency 458 set ideal network 458 set_ideal_transition 458 set_input_delay 203, 239, 321, 369, 440, 458 set_input_transition 210, 213, 234, 4162 set level _shifter_stratezy 466 set_level_shifter_threshold 466 set_load 211, 242, 462 set logic de 462 set_logie_one 462 set_logie zero 463 set_max_area 217, 463 set_ma set_max_leakage_power 466 set_max_time borrow 459 set_max_transition 215, 463, set_min_capacitance 464 set_min_delay 222, 459 set_multieyele_path 219, 260, 460 set_operating conditions 41, 464 set_output_delay 206, 257, 325, 369, 440, 460 set_port_fanout_number 464 set_propagated clock 189, 461 set_resistance 464 set_timing_derate 368, 464 set_units 448 set_wire_load_min_block_size 465, set_wire_load_mode 110, 465 set_wire load model 465 set_wire_load_selection_group 113, 465 setup 62 setup capture edge 315 setup check 3, 227 570 setup check are 60 setup constraint 63 setup Taunch edge 251 setup multieyele 289 setup multicycle check 260 setup receiving edge 251 setup time 62, 508 setup timing check 228, 470, 474, 482, 510 setup_falling 393 setup_rising 393 setup_templa shield wires 176 shielding 177 shortest path 35 sidewall 148 sidewall capacitance 118 signal integrity 147 signal traces 148 simulation 467 skew 30,515 sleep mode 414 slew 28, 53, slew derate factor 54 slew derating 56 slew rate 120 slew threshold 54, 537 slew_derate_from library 55 slew lower threshold _pet fall 54 slew_lower_threshold_pet_rise 54 slew_upper_threshold_pet_fall 54 slew_upper_threshold_pct_rise 54 slow clock domain 289 slow corner 229 slow process 39, 96 souree latency 188 source eynehronous interface 317, 328 specify block 496 speeify parameter 485 specparam 474 SPEF xvi, 113, 418, 531 SPICE 113 SRAM 317 SRAM interface 336 SSTA 427 stage_type 82 stamp event 482 standard cell 19, 43 standard delay annotation 467 standard parasitic extraction format 531 x8 6dstandard Vi. 416 standhy mode 88 standby power 12, 88 startpoint 207 state-dependent model 70 state-dependent path delay 470 state-dependent table 59 statistical static timing analysis 427 statistical wireload 547 steiner tree 547 straight sum 169 subthreshold current 92 synchronous inputs 60 synchronous outputs 61 synthesis 471 T temperature inversion 41 temperature variations 366 thermal budget 12 threshold specification 26 time borrowing 365, 379 time stamp 535 timescale 472 timing analysis 2, 532 timing arc 33, 45, 59, 94, 219, 392, 434 timing break 434 timing check 469, 470, 474, 482, 496 timing constraint 474 timing corner 370 timing environment 469, 471, 474, 485 timing model variable 474 timing paths 207 timing sense 33, timing simulation 2 timing specification 474 timing windows 161 timing sense 51 timing type 64, 69 T-model 103 top wireload mode 110 total capacitance 537, 542, 548 total power 416 transition delay 480 transition time 23,28 triplet form 549 triplets 482, 534 TYP 41 jal delay 482 typieal leakage 41 INDEX, typical process 39, 96, 534 typieal value 549 U unateness 34 uncertainty 186 undershoot 87 undershoot glitch 152, 159 unidirectional skew timing cheek 483 units 99 upper metal Tayer 120 USB core 43 useful skew 444 v valid endpoints 207 valid startpoints 207 Verilog HDL 4, 467, 485, 496, 536 version number 472, 534 VHDL 4, 467, 485, 499 VHDLS7 536 VHDLO3 536 vias 102 vietim 149 vietim net 150, 167 VIH 154 VIHmin 19 VIL 154 ViLmax 19 virtual clock 217 virtual flip-flop 318 VITAL 499 VOH 154 VOL 154 voltage souree 115 voltage threshold 366 voltage unit 100 voltage waveform 23 w waveform specification 183 WCL 420 Wes 40, 420 well bias 417 when condition 71, 94 wide trace 120 width timing check 483 wildcard character 473 wire capacitance 148 S71INDEX, wireload mode 110 wireload model 7, 105 wireload selection group 112 worst-case cold 420 worst-case process 534 worst-case slow 40, 227, 370, 420 worst-case tree 108 worst-case value 549 write eyele 348, x X filter limit 481 Xhandling 10 L zero delay 30 zero violation 246 zero-cycle checks 385 zero-cycle setup 389 372