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Chapter 06 Synthesis of VHDL Code 6

This chapter discusses the synthesis of VHDL code. It explains the realization of VHDL operators and data types, and provides an overview of the VHDL synthesis flow. The chapter also discusses timing considerations and synthesis guidelines. Key aspects of the synthesis process include transforming the VHDL description into logic cells from a target device library using complex algorithms and handling large amounts of data.

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Chapter 06 Synthesis of VHDL Code 6

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CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6 Synthesis guidelines
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

SYNTHESIS OF VHDL CODE SYNTHESIS OF VHDL CODE

Synthesizing VHDL code is the process of realizing the The conceptual diagram can be 10
2
T
y
VHDL description using the primitive logic cells from the considered as the first step in F
2
target device’s library. realizing the code. 01
2
T

value_expr_1 T 00 F
The diagram is refined further
sig
In Chapters 4 and 5, we value_expr_2 T F
2

discussed how to derive a value_expr_3 T F during synthesis. r(1) =1

conceptual diagram from value_expr_4 F

r(2)
=1
VHDL statements. boolean_expr_3

boolean_expr_2
Bus conceptual diagram
boolean_expr_1

Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

SYNTHESIS OF VHDL CODE SYNTHESIS OF VHDL CODE

The synthesis process involves: This chapter explains:
• complex algorithms • the realization of VHDL operators
• a large amount of data, • data types
• computers are needed to
• provides an in-depth overview on the synthesis process,
facilitate the process.
Although today’s synthesis software appears to be • discusses the timing issue involved in synthesis.
sophisticated and capable, there are fundamental limitations.

1
SYNTHESIS OF VHDL CODE SYNTHESIS OF VHDL CODE

CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE
Developing a large digital circuit  The ideal scenario is that human designers would only need to
is a complicated process and develop a high-level behavioral description and EDA software would
involves many difficult tasks. perform:

We have to deal with complex • Synthesis

algorithms and procedures and • Placement
handle a large amount of data. • Routing
Computers are used to facilitate • Automatically derive the
the process. optimal circuit implementation
This is unfortunately not possible.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

2
6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE
The limitation comes from  The core is the algorithms that
the theoretical study of perform the transformation or
computational algorithms. optimization,

 The shell wraps the algorithm,

For the purposes of including data conversion,
discussion, we can separate memory and file management
an EDA software tool into a and user interface
core and a shell.

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE
Although the shell is
important, the core
algorithms ultimately
determine the quality
and efficiency of the
software tool.

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 1. COMPUTABILITY 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 1. COMPUTABILITY
If an algorithm exists, the problem is computable.
• Otherwise, the problem is uncomputable.
An example of an uncomputable
problem is the “halting problem.”

Informally speaking, any attempt to

examine the “meaning” of a program is
uncomputable.

3
6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

The computation complexity can be further divided into: Since most statements on time complexity can be applied to
space complexity as well,
• time complexity • space complexity • in the remaining section we focus on time complexity.

Time complexity is a measure of the time needed to complete

the computation.
Space complexity is a measure of hardware resources, such
as memory, needed to complete the computation

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

The computation time of an algorithm depends on: Type of

Type of processor Compiler
processor Compiler
01 03 05
01 03 05 02 04
02 04 The size of Programming Personal
The size of Programming Personal the input language coding style
the input language coding style
To characterize an algorithm, we normally focus on the
Difficult to determine the exact time needed to complete
impact of input size.
execution of an algorithm.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION
Type of
Compiler The order is defined as follows
processor
• Given two functions, f(n) and g(n),
01 03 05
• we say that f(n) is O(g(n)) (pronounced as f(n) is big-O
02 04 of g(n) or f(n) is of order g(n)) if two constants, n0 and
The size of Programming Personal
the input
c can be found to satisfy:
language coding style
• f(n) < cg(n) for any n, n > n0
Instead of determining the exact function for computation
time, we usually consider only the order of this function.

4
6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

The g(n) function is normally a simple function, such as n, Big-O notation is essentially a scaling
nlog2n, n2, n3 or 2n. factor or growth rate, indicating the
For example, all the following functions are O(n2): resources needed as input size
increase.
 0.1n2
 n2+5n+9 Commonly • O(1), O(n),
encountered • O(log2n), O(nlog2n),
 500 n2 + 1000000
orders are:
• O(n2), O(n3)
• and O(2n).
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

O(n) indicates the linear growth O(log2n) indicates the logarithmic

rate, in which the required growth rate, which changes rather
computation resources increase slowly.
in proportion to the input size. For a problem with O(1) or O(log2n),
the input size has very little impact
O(1) means that the required
on the resources.
computation resources are
constant and do not depend on
input size.

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

O(n2) and O(n3) have faster growth O(2n) indicates the exponential
rates growth rate and the
computation time increases
and the required computation geometrically.
resources become more significant
as the input size increases. Note that an increment of 1 in
input size doubles the
computation time.

5
6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

An example using these functions is shown in Table 6.1, which

lists the required computation times of algorithms of varying
computation complexity.
Input size Big-O function
n n log2n nlog2n n2 n3 2n
2 2 µs 1 µs 2 µs 4 µs 8 µs 4 µs
4 4 µs 2 µs 8 µs 16 µs 64 µs 16 µs
8 8 µs 3 µs 24 µs 64 µs 512 µs 256 µs
16 16 µs 4 µs 64 µs 256 µs 4 ms 66 ms
32 32 µs 5 µs 160 µs 1 ms 33 ms 71 min
48 48 µs 5.5 µs 268 µs 2 ms 111 ms 9 years
64 64 µs 6 µs 384 µs 4 ms 262 ms 600,000
years
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

One example of O(2n) complexity is the For a circuit with n inputs,

exhaustive testing of a combinational there are 2n possible input combinations.
circuit.

8 combinations
One way to test a combinational circuit
3 input

is to apply all possible input

combinations exhaustively and
examine their output responses.

6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE. 6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION 2. COMPUTATION COMPLEXITY. BIG-O NATATION

If we assume that the testing equipment

can check 1 million patterns per
second, exhaustively testing a 64-bit
circuit takes about 600,000 years.

264
6
 600,000 years
10 * 60 * 60 * 24 * 365

6
6.1. FUNDAMENTAL LIMITATIONS OF EDA SOFTWARE.
2. COMPUTATION COMPLEXITY. BIG-O NATATION CHAPTER 6

CONTENTS of CHAPTER 6 6.2. REALIZATION OF VHDL OPERATORS

Fundamental limitations of
1
EDA software .1 Realization of logical operators

1 2 Realization of VHDL operator .2 Realization of relational operators

6 2
3 Realization of VHDL data types .3 Realization of addition operators

5 3
6
4 VHDL synthesis flow .4 Synthesis support for other operator
4 Realization of an operator with
5 Timing considerations .5 constant operands
.6 An example implementation
6 Synthesis guidelines
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

1. REALIZATION OF LOGICAL OPERATORS 1. REALIZATION OF LOGICAL OPERATORS

 Logical operators can be mapped directly to logic gates, and their The xor and xnor operators are slightly
synthesis is straightforward.
more involved
y <= a and b; VHDL Statement

and their implementation

a y
b Hardware requires more silicon area
and experiences a larger
propagation delay.
The and, nand, or and nor operators have similar
area and delay characteristics.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

7
6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS
1. REALIZATION OF LOGICAL OPERATORS 1. REALIZATION OF LOGICAL OPERATORS

In VHDL, a logical operation a(0)

b(0)
y(0)

can be applied over operands a(1)

y(1)
b(1)
with multiple bits. a(2)
y(2)
b(2)
a(3)
a y(3)
y b(3)
b a(4)
y(4)
b(4)
a(5)
y(5)
b(5)
a(6)
y(6)
b(6)
a(7)
y(7)
b(7)
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

1. REALIZATION OF LOGICAL OPERATORS 1. REALIZATION OF LOGICAL OPERATORS

Since each bit of the input a(0)

b(0)
y(0)
a(4)
b(4)
y(4)

operates independently, a(1)

y(1)
a(5)
y(5)
b(1) b(5)
a a(2) a(6)
y y(2) y(6)
b b(2) b(6)
a(3) a(7)
y(3) y(7)
b(3) b(7)

• the area of the circuit grows linearly with the number of a(0)
y(0)
a(4)
y(4)
b(0) b(4)
input bits (i.e., on the order of O(n)), a(1)
y(1)
a(5)
y(5)
b(1) b(5)

• and the propagation delay is a constant (i.e., on the order a(2)

b(2)
y(2)
a(6)
b(6)
y(6)

of O(1)). a(3)
b(3)
y(3)
a(7)
b(7)
y(7)

6.2. REALIZATION OF VHDL OPERATORS

1. REALIZATION OF LOGICAL OPERATORS CHAPTER 6

8
CONTENTS of CHAPTER 6 6.2. REALIZATION OF VHDL OPERATORS
Fundamental limitations of
1
EDA software .1 Realization of logical operators

1 2 Realization of VHDL operator .2 Realization of relational operators

6 2
3 Realization of VHDL data types .3 Realization of addition operators

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

2. REALIZATION OF RELATIONAL OPERATORS 2. REALIZATION OF RELATIONAL OPERATORS

There are six relational operators in VHDL: According to their hardware implementation, these operators
=, Compare circuit can be divided into
Oa>=b
/=, a 2 Oa>b
Oa/=b
• The equality group,
Oa=b Compare circuit
<, b 2
Oa<b
which includes the = Oa>=b

<=, Oa=<b
and /= operators, 2 Oa>b
a Oa/=b
> and • The greater-less group, 2
Oa=b
b Oa<b
which includes the other
=>. Oa=<b
four operators.

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

2. REALIZATION OF RELATIONAL OPERATORS 2. REALIZATION OF RELATIONAL OPERATORS

In the equality group, operators can easily be implemented by

a tree-like structure.
a0
eq  (a0  b0 ) b0 eq
Compare circuit
Oa>=b eq  (a0  b0 )(a1  b1 )
Oa>b a(0)
2
a Oa/=b b(0)

2
Oa=b eq  (a0  b0 ).(a1  b1 ).(a2  b2 ) a(1)
b Oa<b b(1) eq
a(2)
eq  (a0  b0 ).(a1  b1 ).(a 2  b2 ).(a3  b3 )
Oa=<b b(2)
a(3)
b(3)

9
6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS
2. REALIZATION OF RELATIONAL OPERATORS 2. REALIZATION OF RELATIONAL OPERATORS

For this implementation: a(0)

b(0)
a(0)
b(0)
a(1) a(1)
• the circuit area grows linearly b(1) eq b(1) eq
a(2) a(2)
with the number of input bits b(2) b(2)
(i.e., O(n)), a(3)
b(3)
a(3)
b(3)

• and the delay grows at a relatively

slow O(log2n) rate.

eq  (a0  b0 ).(a1  b1 ).(a 2  b2 ).(a3  b3 ) eq  (a0  b0 ).(a1  b1 ).(a 2  b2 ).(a3  b3 )

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

2. REALIZATION OF RELATIONAL OPERATORS 2. REALIZATION OF RELATIONAL OPERATORS
Compare circuit

 In the greater-less group, the Oa>=b This leads to larger area and
Oa>b
operation exhibits a strong data a 2
Oa=b
Oa/=b
propagation delay.
2
dependency of input bits. b Oa<b

Oa=<b

 we first have to compare the

most significant bits of two
operands and, if they are equal,
the next lower bits and so on. Because of the circuit complexity, these operators can be
implemented in a variety of ways, each with a different area-
delay characteristic.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

2. REALIZATION OF RELATIONAL OPERATORS 2. REALIZATION OF RELATIONAL OPERATORS

In the minimal-area

implementation, both
area and delay grow
linearly (i.e., O(n))
with the number of
input bits.

10
6.2. REALIZATION OF VHDL OPERATORS
2. REALIZATION OF RELATIONAL OPERATORS CHAPTER 6

CONTENTS of CHAPTER 6 6.2. REALIZATION OF VHDL OPERATORS

Fundamental limitations of
1
EDA software .1 Realization of logical operators

1 2 Realization of VHDL operator .2 Realization of relational operators

6 2
3 Realization of VHDL data types .3 Realization of addition operators

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

3. REALIZATION OF ADDITION OPERATORS 3. REALIZATION OF ADDITION OPERATORS

The addition operator (+) is Since the adder is the basis of

the most basic arithmetic other arithmetic operations,
operator. its implementation has been
studied extensively and
Several other operators, including
• subtraction (-), a wide range of circuits that
exhibit different area-delay
• negation (- with one operand) and characteristics has been
• absolute value (abs), developed.
can easily be derived from the addition operator.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

11
6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS
3. REALIZATION OF ADDITION OPERATORS 3. REALIZATION OF ADDITION OPERATORS

The minimal-area circuit,

sometimes known as a serial or
ripple adder,

• can easily be implemented by cascading

a series of 1-bit full adders.

In this implementation, both area and delay grow linearly

(i.e., O(n))
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.2. REALIZATION OF VHDL OPERATORS

3. REALIZATION OF ADDITION OPERATORS CHAPTER 6

CONTENTS of CHAPTER 6 6.2. REALIZATION OF VHDL OPERATORS

Fundamental limitations of
1
EDA software .1 Realization of logical operators

1 2 Realization of VHDL operator .2 Realization of relational operators

6 2
3 Realization of VHDL data types .3 Realization of addition operators

12
6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS
4. SYNTHESIS SUPPORT FOR OTHER OPERATORS 4. SYNTHESIS SUPPORT FOR OTHER OPERATORS

Synthesis support for other more complicated operators is Some high-end synthesis software can automatically derive
sporadic.
• multiplication operator (*) and
It depends on:
• shift operators
• individual synthesis software,
• (sll, srl, sla, sra, rol and ror of VHDL, and
• the width of the input operands
• as well as the targeted device technology. • shift-left, shift right, rotate-left and rotate
right of the IEEE numeric std library).

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

4. SYNTHESIS SUPPORT FOR OTHER OPERATORS 4. SYNTHESIS SUPPORT FOR OTHER OPERATORS

Because of the hardware complexity,

• we must be extremely careful if these operators
are used in a VHDL code.
Synthesis software rarely supports:
• division-related operators (/, mod and rem) or
• the exponential operator (**) or
• any operators associated with floating-point data-
type operands.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.2. REALIZATION OF VHDL OPERATORS

4. SYNTHESIS SUPPORT FOR OTHER OPERATORS CHAPTER 6

13
CONTENTS of CHAPTER 6 6.2. REALIZATION OF VHDL OPERATORS
Fundamental limitations of
1
EDA software .1 Realization of logical operators

1 2 Realization of VHDL operator .2 Realization of relational operators

6 2
3 Realization of VHDL data types .3 Realization of addition operators

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS 5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS

The operands of VHDL operators can sometimes be a For example, consider the following code segment:
constant expression,
constant OFFSET: integer := 8;
• which does not depend on the value of any input signal. signal boundary: unsigned(8 downto 0);
signal overflow: std_logic;
 Operator with all constant operands ...

 Operator with partial constant operands overflow <='1' when boundary > (2**OFFSET-1) else
'0';

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS 5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS

Operator with partial constant operands

Most VHDL operators have two operands.
Sometimes one of the operands is a constant, as in count+1.

y <= rotate_right(x,3); y <= rotate_right(x,3);

It is the same as
y <= x(2 downto 0) & x(7 downto 3); y <= x(2 downto 0) & x(7 downto 3);

14
6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS
5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS 5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS

The logic expression of this operation is

( x3  y3 ).( x2  y2 ).( x1  y1 ).( x0  y0 )

If one operand is a constant, say, y3y2y1y0 = 0000, the
expression can be simplified to

x3 .x2 .x1.x0
x3 .x2 .x1.x0  x3  x2  x1  x0
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.2. REALIZATION OF VHDL OPERATORS

5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS CHAPTER 6

CONTENTS of CHAPTER 6 6.2. REALIZATION OF VHDL OPERATORS

Fundamental limitations of
1
EDA software .1 Realization of logical operators

1 2 Realization of VHDL operator .2 Realization of relational operators

6 2
3 Realization of VHDL data types .3 Realization of addition operators

15
6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS
6. AN EXAMPLE IMPLEMENTATION 6. AN EXAMPLE IMPLEMENTATION

It will be helpful to have a comprehensive table that lists the Table 6.2 shows one synthesis result for several
areas and delays of synthesizable operators. representative operators of different input widths in a 0.55-
micron CMOS standard-cell technology.
However, because of the complexity of the synthesis
process and device technology,

• a small variation in VHDL code, synthesis algorithm, or

device parameters will lead to different results.

6.2. REALIZATION OF VHDL OPERATORS 6.2. REALIZATION OF VHDL OPERATORS

6. AN EXAMPLE IMPLEMENTATION 6. AN EXAMPLE IMPLEMENTATION

6.2. REALIZATION OF VHDL OPERATORS

6. AN EXAMPLE IMPLEMENTATION CHAPTER 6

16
CONTENTS of CHAPTER 6 6.3. REALIZATION OF VHDL DATA TYPES
Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator .1 Use of the std-logic data type
6 2
3 Realization of VHDL data types 3 Use and realization of the ‘Z’
3 .2
5 3 4 VHDL synthesis flow 3 value
4
.3 Use of the ‘-’ value
5 Timing considerations

6.3. REALIZATION OF VHDL DATA TYPES. 1. USE OF THE STD-LOGIC DATA TYPE 6.3. REALIZATION OF VHDL DATA TYPES. 1. USE OF THE STD-LOGIC DATA TYPE

VHDL supports a rich set of data types. Recall that there are nine
possible values in the
During synthesis, these data types must be mapped into
std_logic data type.
binary representations so that they can be realized in a
physical circuit.
Among them, ‘0’ and ‘1’
are interpreted as logic 0
and logic 1 and are used in
regular synthesis.

6.3. REALIZATION OF VHDL DATA TYPES. 1. USE OF THE STD-LOGIC DATA TYPE 6.3. REALIZATION OF VHDL DATA TYPES. 1. USE OF THE STD-LOGIC DATA TYPE

‘L’ and ‘H’ are interpreted ‘U’, ‘X’ and ‘W’ are
as weak 0 and weak 1, as in meaningful only in
wired logic. modeling and simulation,
Since modern device and they cannot be
technologies no longer use synthesized.
this kind of circuitry, the
two values should not be
used.

17
6.3. REALIZATION OF VHDL DATA TYPES. 1. USE OF THE STD-LOGIC DATA TYPE 6.3. REALIZATION OF VHDL DATA TYPES. 1. USE OF THE STD-LOGIC DATA TYPE

The two remaining values,

‘Z’ and ‘-’, which
represent high impedance
• and “don’t care”
respectively, have some
impact on synthesis.

CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6.3. REALIZATION OF VHDL DATA TYPES 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

The ‘Z’ value means high

impedance or an open
.1 Use of the std-logic data type circuit.
3 Use and realization of the ‘Z’ It is not a value in Boolean
3 .2
3 value algebra

.3 Use of the ‘-’ value • but a special electrical

property exhibited in a
physical circuit.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

18
6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

Only a special kind of component, known as a tri-state buffer,

can have an output of this value.

The symbol and oe

in output
function table of a_in y oe y
a tri-state buffer 0 Z
are shown 1 a_in
Tri-state buffer.

6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

+VCC +VCC
+VCC

R1 R2 R3 R3
R3
Q4
Q4
Q4
Input Q2
Q1 D1
Output
D1
D3 High – Z output D1
High – Z output
Enable D2 Q3
Q5
R4 Q3
Q3

6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

19
6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

High impedance cannot be

oe
in output We cannot use a value of oe
in output

handled by regular logic a_in y oe y ‘Z’ as an input or a_in y oe y

0 Z 0 Z
1 a_in manipulate it as a logic 1 a_in
• and can exist only in the Tri-state buffer. value. Tri-state buffer.
output of a tri-state buffer.
For example, the following statements cannot be realized and
are meaningless in synthesis:
The VHDL description of the tri-state buffer is
f <= Z and a;
y <= a_in when oe = '1' else
y <= data_a when in_bus = 'Z' else
'Z'; data_b;
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

Since a tri-state buffer is not an ordinary logic value, it is a

good idea to code it in a separate statement.
For example, consider the following VHDL description:
with sel select with sel select
y <= 'Z' when “00”, tmp <= '1' when “01”|“11”,
'1' when “01”|“11”, '0' when others;
'0' when others;
y <= tmp when sel/= “00” else
Z 00 'Z'; 0 00
Z 00
0
1 01 1 01 00
y 1 01 tmp y y 1 01 tmp y
0 10 0 10
1 11 0 10 1 11 0 10
sel 1 11 sel 1 11
sel sel
(a) Confusing diagram /= (a) Confusing diagram 00
/=
00
(b) Better diagram (b) Better diagram
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

20
6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

VHDL description of a Most FPGA and memory devices utilize bidirectional I/O pins.
bidirectional I/O port
The schematic of a simple circuit with bidirectional I/O port,
bi, is shown in Figure
As a silicon device packs more
dir
circuitry into a chip, the number of dir

I/O signals increases accordingly. sig_out

sig_out
bi bi

A bidirectional I/O pin can be used as either an input or an

sig_in
output and thus makes more efficient use of an I/O pin. sig_in

6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE

The VHDL segment for the single-buffer diagram is

dir dir
entity bi_demo is
port ( sig_out sig_out
bi bi
bi: inout std_logic;
...
begin sig_in sig_in
sig_out <= output_expression;
...
some_signal <= expression_with_sig_in;
...
bi <= sig_out when dir = ’1’ else 'Z';
sig_in <= bi;
...
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE
dir
The VHDL segment for the
dir
sig_out
sig_out
tow-buffer diagram is bi
bi

sig_in
sig_in

bi <= sig_out when dir = ‘1’ else 'Z';

Sig_in <= bi when dir = ‘0’ else 'Z';

21
6.3. USE OF THE STD-LOGIC DATA TYPE. 2. USE AND REALIZATION OF THE ‘Z’ VALUE CHAPTER 6

CONTENTS of CHAPTER 6 6.3. REALIZATION OF VHDL DATA TYPES

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator .1 Use of the std-logic data type
6 2
3 Realization of VHDL data types 3 Use and realization of the ‘Z’
3 .2
5 3 4 VHDL synthesis flow 3 value
4
.3 Use of the ‘-’ value
5 Timing considerations

6.3. USE OF THE STD-LOGIC DATA TYPE. 3. USE OF THE ‘-’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 3. USE OF THE ‘-’ VALUE

Don't-care is not a valid Don't-care is not a valid logic value in Boolean algebra but is
logic value in Boolean used to facilitate the design process.
Input Output
algebra but is used to Input Output req code
facilitate the design process. req code 1 - - 1 0
1 0 0 1 0 0 1 - 0 1
0 0 1 0 0
Don't-care can be used as 1
1
0
1
1
0
1
1
0
0 0 0 0 0 0

an input value to make a 1 1 1 1 0

input output
0 1 0 0 1
function table clear and 0 1 1 0 1
a
0
b
0
f
0
compact. 0 0 1 0 0 0 1 1
0 0 0 0 0 1 0 1
1 1 -

22
6.3. USE OF THE STD-LOGIC DATA TYPE. 3. USE OF THE ‘-’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 3. USE OF THE ‘-’ VALUE

When used as an output value, don't-care input

a b
output
f
Consider the priority function.
indicates that the exact value is not 0 0 0
We may be tempted to code the circuit as follows:
0 1 1
important. 1 0 1
1 1 -
y <= "10" when req = "1--" else
This happens when some of the "01" when req = "01-" else
input combinations are not used. "00" when req = "001" else
"00";

During the synthesis process, we can

The code is syntactically correct.
assign a value that helps to reduce the
circuit complexity.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.3. USE OF THE STD-LOGIC DATA TYPE. 3. USE OF THE ‘-’ VALUE 6.3. USE OF THE STD-LOGIC DATA TYPE. 3. USE OF THE ‘-’ VALUE

However, in a physical circuit, an input signal can only assume

a value of '0' or '1' but never '-',
and thus the req="1--" and req="01-"
expressions will always be false.
y <= "10" when req = "1--" else
"01" when req = "01-" else
"00" when req = "001" else
"00";

Lead to the wrong circuit

6.3. USE OF THE STD-LOGIC DATA TYPE. 3. USE OF THE ‘-’ VALUE CHAPTER 6

23
CONTENTS of CHAPTER 6 6.4. VHDL SYNTHESIS FLOW
Fundamental limitations of
1
EDA software 5 .1 RT-level Synthesis
1 2 Realization of VHDL operator
5 .2 Module generator
6 2
3 Realization of VHDL data types
5 .3 Logic synthesis
5 3 4 VHDL synthesis flow
4
5 Timing considerations
5 .4 Technology mapping

6 Synthesis guidelines
5 .5 Effective use of synthesis Software
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.4. VHDL SYNTHESIS FLOW 6.4. VHDL SYNTHESIS FLOW

Synthesizing VHDL code is
the process of realizing a
VHDL description

using the primitive logic

cells from the target
device’s library.

It is a complex process.

6.4. VHDL SYNTHESIS FLOW 6.4. VHDL SYNTHESIS FLOW.

 To make it manageable, we normally High-level synthesis transforms
divide VHDL synthesis into steps, an algorithm into an architecture
including: consisting of a data path and
 High-level synthesis control path.
 RT-level synthesis

 Gate-level synthesis (commonly

known as logic synthesis)

 Cell-level synthesis (commonly known

as technology mapping).
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

24
6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS RT-LEVEL
CODE
DATA
FILE
6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS RT-LEVEL
CODE
DATA
FILE

Basically, the entire circuit

COMPONENT COMPONENT
LIBRARY LIBRARY
RT-level synthesis and PROCESS RT-level synthesis and PROCESS
optimization optimization

is transformed and RT-LEVEL RT-LEVEL

optimized level by level, netlist netlist

Predesigned Predesigned
• from an RT-level netlist to
Module generator Module generator
module library module library

a gate-level netlist and Logic synthesis gate library Logic synthesis gate library

• then to a cell-level netlist, Gate-level Gate-level

netlist netlist

as shown in the left Technology mapping Technology mapping

cell library cell library
column of the flowchart. Cell-level Cell-level
netlist netlist

6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS
RT-level synthesis RT-LEVEL DATA The components can be RT-LEVEL DATA
CODE FILE CODE FILE
transforms a COMPONENT
LIBRARY
classified into three COMPONENT
LIBRARY
RT-level synthesis and PROCESS RT-level synthesis and PROCESS
behavioral VHDL optimization categories: optimization

description into a RT-LEVEL RT-LEVEL

circuit
netlist
 functional units, netlist

• constructed by components  routing units

from a generic RT-level  storage units.
library.

6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS
 functional units RT-LEVEL
CODE
DATA
FILE
 routing units RT-LEVEL
CODE
DATA
FILE
COMPONENT COMPONENT

 are used to implement RT-level synthesis and PROCESS

LIBRARY
 are various multiplexers RT-level synthesis and PROCESS
LIBRARY

optimization optimization

the logic, relational and RT-LEVEL  used to construct the RT-LEVEL

arithmetic operators netlist
routing structure of a
netlist

 encountered in VHDL code. VHDL description,

 as discussed in Chapters 4 and 5.

25
6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS
 storage units. RT-LEVEL
CODE
DATA
FILE
RT-LEVEL
CODE
DATA
FILE
COMPONENT COMPONENT

 are registers and latches,

LIBRARY LIBRARY
RT-level synthesis and PROCESS RT-level synthesis and PROCESS
optimization optimization

 which are used only RT-LEVEL

in
netlist
RT-LEVEL
netlist

sequential circuits

 and are discussed in Chapter 8.

6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS
RT-level synthesis RT-LEVEL
CODE
DATA
FILE
Some optimization RT-LEVEL
CODE
DATA
FILE
includes the derivation COMPONENT
LIBRARY techniques, such as: COMPONENT
LIBRARY
RT-level synthesis and PROCESS RT-level synthesis and PROCESS
and optimization of an optimization optimization

RT-level netlist. RT-LEVEL RT-LEVEL

 operator sharing,
netlist netlist

can be applied to reduce

During the process, VHDL statements are converted into  common code elimination circuit complexity or to
corresponding structural implementation,  constant propagation. enhance performance
somewhat similar to the derivation of conceptual diagrams  Good design can drastically alter the RT-level structure and help
discussed in Chapters 4 and 5. software to derive a more effective implementation.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 1. RT-LEVEL SYNTHESIS

26
CHAPTER 6 CONTENTS of CHAPTER 6
Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6.4. VHDL SYNTHESIS FLOW 6.4. VHDL SYNTHESIS FLOW. 2. MODULE GENERATOR

.1 RT-level Synthesis Some RT-level

5 Predesigned
components, such as Module generator
module library
logical operators and
5 .2 Module generator
multiplexers, are simple Logic synthesis gate library

5 .3 Logic synthesis
• and can be y <= a and b; VHDL Statement
mapped directly
5 .4 Technology mapping into gate-level
implementation. a
5 .5 Effective use of synthesis Software b
y
Hardware
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.4. VHDL SYNTHESIS FLOW. 2. MODULE GENERATOR 6.4. VHDL SYNTHESIS FLOW. 2. MODULE GENERATOR
The other components They usually show some
Predesigned Predesigned
are quite complex Module generator
module library kind of repetitive structure Module generator
module library
and sometimes are known
• and need special software, Logic synthesis gate library
as regular logic. Logic synthesis gate library

• known as a module generator,

• to derive the gate-level implementation. Regular logic is usually designed in advance.
These components include adder, subtractor, incrementor,
decrementor, comparator and, if supported, shifter and
multiplier as well.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

27
6.4. VHDL SYNTHESIS FLOW. 2. MODULE GENERATOR 6.4. VHDL SYNTHESIS FLOW. 2. MODULE GENERATOR
A module generator can
Predesigned
produce modules in Module generator
module library
different levels of detail:
Logic synthesis gate library

• Gate-level behavioral description.

• Resynthesized gate-level netlist.
• Resynthesized cell-level netlist.

CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6.4. VHDL SYNTHESIS FLOW 6.4. VHDL SYNTHESIS FLOW. 3. LOGIC SYNTHESIS
.1 RT-level Synthesis Logic synthesis is the RT-LEVEL
5 netlist

process of generating a
structural view Predesigned
.2
Module generator

5 Module generator module library

• using an optimal
.3
Logic synthesis gate library
5 Logic synthesis number of generic
primitive gate-level Gate-level

.4
netlist

5 Technology mapping components.

Such as a not gate, and gate, nand
5 .5 Effective use of synthesis Software
gate, or gate and nor gate.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

28
6.4. VHDL SYNTHESIS FLOW. 3. LOGIC SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 3. LOGIC SYNTHESIS
At this level, a circuit can RT-LEVEL
netlist
RT-LEVEL
netlist

be expressed by a
Predesigned Predesigned
Boolean function, Module generator
module library
Module generator
module library

• and these generic Logic synthesis gate library Logic synthesis gate library

components are
Gate-level Gate-level
essentially the operators netlist netlist

of Boolean algebra.

6.4. VHDL SYNTHESIS FLOW. 3. LOGIC SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 3. LOGIC SYNTHESIS
Logic synthesis can be RT-LEVEL
netlist
An example is shown Other two-level forms can easily
divided into two-level a b c d e be derived from the sum-of-
synthesis and multilevel Module generator Predesigned
module library products form.
synthesis. y a b c d e
Logic synthesis gate library
The most commonly used
two-level form is the Gate-level
netlist y

sum-of-products form, • in which the first level of logic

corresponds to and gates and
the second level to or gates.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.4. VHDL SYNTHESIS FLOW. 3. LOGIC SYNTHESIS 6.4. VHDL SYNTHESIS FLOW. 3. LOGIC SYNTHESIS
a b c d e

a b c d e

29
CHAPTER 6 CONTENTS of CHAPTER 6
Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6.4. VHDL SYNTHESIS FLOW 6.4. VHDL SYNTHESIS FLOW. 4. TECHNOLOGY MAPPING
.1 RT-level Synthesis Technology mapping is the
5
process of transforming the
.2 Module generator netlist
5
using components from the Gate-level

5 .3 Logic synthesis
netlist
target device’s library.
Technology mapping
cell library
5 .4 Technology mapping Cell-level
netlist

5 .5 Effective use of synthesis Software

6.4. VHDL SYNTHESIS FLOW. 4. TECHNOLOGY MAPPING 6.4. VHDL SYNTHESIS FLOW. 4. TECHNOLOGY MAPPING
These components are
commonly referred to as cells,
and the technology library is
normally provided by a Gate-level

semiconductor vendor netlist

who manufactured (as in Technology mapping

cell library

FPGA technology) or will Cell-level

netlist

manufacture (as in ASIC

technology) the device.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

30
6.4. VHDL SYNTHESIS FLOW. 4. TECHNOLOGY MAPPING CHAPTER 6

CONTENTS of CHAPTER 6 6.4. VHDL SYNTHESIS FLOW

Fundamental limitations of
1
EDA software 5 .1 RT-level Synthesis
1 2 Realization of VHDL operator
5 .2 Module generator
6 2
3 Realization of VHDL data types
5 .3 Logic synthesis
5 3 4 VHDL synthesis flow
4
5 Timing considerations
5 .4 Technology mapping

6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE 6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE
Despite its undamental limitation, A good designer should
synthesis software is still a understand the capabilities and
powerful and necessary tool, limitation of software,

which can automate many design and know what this tool can
tasks and perform certain tedious and cannot do as well as when
and repetitive computations. to compromise.

31
6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE 6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE
 VHDL description of logical operators  VHDL description of logical operators

• In general, synthesis software is • VHDL logical operators can be

very effective in performing logic mapped directly to gate-level
synthesis components.
• Their implementations are
• and technology mapping for a simple and straightforward.
small to moderate-sized circuit
• Since synthesis is very effective at this level, we need not
• whose complexity is around 5000 worry about the sharing and optimization of logical
to 50,000 equivalent gates. operators in a VHDL description.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE 6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE
 VHDL description of arithmetic and relational operators  VHDL description of arithmetic and relational operators
• Optimization at the RT level • Human intervention is required,
involves complex arithmetic and and
relational operators and routing
• we have to specify explicitly the
structure.
desired design in a VHDL
• It is not well developed and is description.
frequently done on an ad hoc • Simple modifications on code
basis. frequently can improve circuit
efficiency significantly.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

32
6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE 6.4. VHDL SYNTHESIS FLOW. 5. EFFECTIVE USE OF SYNTHESIS SOFTWARE

CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6.5. TIMING CONSIDERATIONS 6.5. TIMING CONSIDERATIONS

A digital circuit cannot respond
instantaneously, and the
.1 Propagation delay output is actually a function of
3
time.
Synthesis With Timing
3 .2 The most important time-domain characteristic is the
3 Constraints
propagation delay.
.3 Timing Hazards

33
6.5. TIMING CONSIDERATIONS 6.5. TIMING CONSIDERATIONS. 1. PROPAGATION DELAY

 The propagation delay is the A digital system normally has

time required for the circuit to multiple input and output
generate a valid, stabilized ports,
output value after an input
change. • and each input-output path
may exhibit a different delay.
It is one of the major design criteria for a circuit.
We consider the worst-case scenario and use the largest
input-output delay as the system’s propagation delay.

6.5. TIMING CONSIDERATIONS. 1. PROPAGATION DELAY 6.5. TIMING CONSIDERATIONS. 1. PROPAGATION DELAY

The propagation delay reflects

how fast a system can operate Cw1 Cg1
and is usually considered as
the performance or the speed
a
of the system.
b
Cg2
Cw2
Combined with the circuit size (area), they are the two most
important design criteria of a digital system.
Cw3 Cg3

6.5. TIMING CONSIDERATIONS. 1. PROPAGATION DELAY 6.5. TIMING CONSIDERATIONS. 1. PROPAGATION DELAY. System delay
Once cell delays are known,
Cw1 Cg1
we can calculate the delay of a
path by adding the individual
cell delays along the path.
a

b
Cw2
Cg2
A digital system typically has many paths between input and
output ports, and their delays are different.
Cw3 Cg3

34
6.5. TIMING CONSIDERATIONS. 1. PROPAGATION DELAY. System delay 6.5. TIMING CONSIDERATIONS. 1. PROPAGATION DELAY. System delay
Since the system has to accommodate the worst-case
scenario, the system delay is defined as the longest delay.

The corresponding path is considered as the longest path and

is known as the critical path.

CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

6.5. TIMING CONSIDERATIONS 6.5. TIMING CONSIDERATIONS. 2. SYNTHESIS WITH TIMING CONSTRAINTS

The circuit area and time Minimal-area

implimentation
system delay are two
.1
Ideal implimentation
Propagation delay major design criteria. (with minimal area and
delay)

3 Synthesis With Timing

3 .2 In most applications, we
Minimal-delay
3 Constraints cannot find a design or an implimentation

implementation that is area

.3 Timing Hazards optimized for both
criteria.

35
6.5. TIMING CONSIDERATIONS. 2. SYNTHESIS WITH TIMING CONSTRAINTS 6.5. TIMING CONSIDERATIONS. 2. SYNTHESIS WITH TIMING CONSTRAINTS

A faster circuit normally is time Minimal-area

implimentation
An example is shown:
more complex and needs a(0)

more silicon real estate,

Ideal implimentation
(with minimal area and
a(1)
y(1)
optimized for
y(2)
delay) a(2)
a(3) y(3)
area
and a smaller circuit Minimal-delay (a) Optimized for area

normally has to sacrifice implimentation

a(0) y(1)
area a(1)
some performance. a(2)
y(2) system delay
a(3)
y(3)
is reduced
(b) Optimized for delay

6.5. TIMING CONSIDERATIONS. 2. SYNTHESIS WITH TIMING CONSTRAINTS 6.5. TIMING CONSIDERATIONS. 2. SYNTHESIS WITH TIMING CONSTRAINTS

CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

36
6.5. TIMING CONSIDERATIONS 6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS
The propagation delay of a system is the time required to
generate a valid, steady-state output value.
.1 Propagation delay
Timing hazards are the fluctuations occurring during the
3 Synthesis With Timing transient period.
3 .2
3 Constraints
.3 Timing Hazards

6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS 6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS
In a digital system, many a
ab
A static hazard is the condition that a circuit’s output
paths may lead to the b sh
produces a glitch when it should remain at a steady value.
b
same output port.
c
It is further divided into static-1 hazard and static-0 hazard.
bc

Since each path’s delay is different, signals may propagate to

the output port at different times.

Before the output port produces a steady-state value, it may

fluctuate several times.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS 6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS
An example bc
a=1 ab=0 a
sh 00 01 11 10 c
b=1 b=0
• Assume that a 0
0 1 3
1
2
0 sh=1 b

and c are ‘1’ a 4 5 7 6 c=1 bc=1 b

and that b 1 1 1 1 (a) At t0

bc
changes from ab a=1 ab=0
a
‘1’ to ‘0’. b=0 b=1
ab
b sh sh=1
b
sh
c=1 bc=0
c (b) At t1 t0 t1 t2 t3
bc
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

37
6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS 6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS
a=1 ab=1 a There are some techniques to eliminate hazards caused by a
b=0 b=1
c single input change.
sh=0 b
For example, we can add a redundant product term to
bc=0
c=1
(c) At t2
b eliminate the previous static hazard:
bc a
a=1 ab=1 Sh = a.b’ + b.c + a.c ab

b b
b=0 b=1 sh=1 ab bc
sh 00 01 11 10 sh
0 1 3 2
c
bc
bc=0
sh 0 1 0
c=1 a 4 5 7 6 ac
(d) At t3
t0 t1 t2 t3 1 1 1 1
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS 6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS

a ab

b b
bc
sh 00 01 11 10 sh
0 1 3 2
c
bc
0 1 0
a 4 5 7 6 ac
1 1 1 1
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 6: Synthesis of VHDL code. www.hcmute.edu.vn

CHAPTER 6 CONTENTS of CHAPTER 6

Fundamental limitations of
1
EDA software
1 2 Realization of VHDL operator
6 2
3 Realization of VHDL data types

5 3 4 VHDL synthesis flow

4
5 Timing considerations

38
6.6. SYNTHESIS GUIDELINES 6.6. SYNTHESIS GUIDELINES
Be aware of the theoretical limitation of synthesis software.
Unless there is a compelling reason, use a multiplexer instead
Be aware of the hardware complexity of different VHDL of an internal tri-state bus.
operators. Avoid using the ’-’ value of the std-logic data type as an input
value.
Isolate tri-state buffers from other logic and code them in a
separate segment.

6.6. SYNTHESIS GUIDELINES 6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS

In RT-level description, there is no effective way to eliminate
glitches from a combinational circuit.

We should deal with the glitches rather than attempting to

derive a glitch-free combinational circuit.
Do not use delay-sensitive design in RT-level description.

6.5. TIMING CONSIDERATIONS. 3. TIMING HAZARDS

THANK
YOU

39
6.6. CÁC CÂU HỎI KIỂM TRA 6.6. CÁC CÂU HỎI KIỂM TRA
 Câu 6.1  Câu 6.2

 Hãy vẽ ký hiệu cổng  Hãy vẽ ký hiệu cổng  Hãy vẽ mạch port IO  Hãy vẽ mạch port IO
các dạng cổng 3 trạng 3 trạng thái dùng 1 cổng 3 trạng dùng 2 cổng 3 trạng
thái thái thái
 Các bảng trạng thái  Viết lệnh mô tả cổng 3  Viết lệnh mô tả tương  Viết lệnh mô tả tương
tương ứng trạng thái ứng ứng

Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn

6.6. CÁC CÂU HỎI KIỂM TRA 6.6. CÁC CÂU HỎI KIỂM TRA
 Câu 6.3  Câu 6.4

 Hãy giải thích bảng sau

 Hãy liệt 5 hàm Big-O và  Hãy liệt kê các toán tử
giải tích tính chất logic Input size Big-O function
n n log2n nlog2n n2 n3 2n
2 2 µs 1 µs 2 µs 4 µs 8 µs 4 µs
 Hàm mô tả các toán tử 4 4 µs 2 µs 8 µs 16 µs 64 µs 16 µs
logic theo tài nguyên và 8 8 µs 3 µs 24 µs 64 µs 512 µs 256 µs
16 16 µs 4 µs 64 µs 256 µs 4 ms 66 ms
thời gian như thế nào 32 32 µs 5 µs 160 µs 1 ms 33 ms 71 min
khi ngõ vào tăng, cho ví 48 48 µs 5.5 µs 268 µs 2 ms 111 ms 9 years
64 64 µs 6 µs 384 µs 4 ms 262 ms 600,000
dụ minh họa? years
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn

6.6. CÁC CÂU HỎI KIỂM TRA 6.6. CÁC CÂU HỎI KIỂM TRA
 Câu 6.5  Câu 6.6
 Hãy vẽ sơ đồ mạch so  Hãy liệt kê các toán tử  Hãy vẽ sơ đồ khối, bảng  Hãy vẽ sơ đồ khối và sơ
sánh bằng của 2 số. so sánh trạng thái, phương trình, đồ mạch cộng 2 số nhị
sơ đồ mạch cộng toàn phân 4 bit sử dụng mạch
 Hãy vẽ sơ đồ khối phần 1 bit cộng nhị phân 1 bit
 Viết phương trình so sánh:
tương ứng
1 bit, 2 bit, 3 bit, 4 bit
 Hàm mô tả theo tài  Hãy cho biết khi ngõ vào
nguyên và thời gian của tăng thì tài nguyên và
 Vẽ mạch so sánh 3 bit thời gian theo hàm nào
toán tử so sánh bằng?
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn

40
6.6. CÁC CÂU HỎI KIỂM TRA 6.6. CÁC CÂU HỎI KIỂM TRA
 Câu 6.7  Câu 6.8
 Hãy vẽ sơ đồ khái niệm  Hãy vẽ sơ đồ khái niệm  Hãy đơn giản các phương trình dùng bìa K chuẩn:
mạch mã hóa ưu tiên ngõ mạch mã hóa ưu tiên ngõ
vào bit cao, có 6 ngõ vào. vào bit thấp, có 7ngõ  X = f(d,c,b,a) = Σ(1,4,5,7,13,15)
Dùng lệnh gán có điều vào. Dùng lệnh if
kiện  Y = f(d,c,b,a) = Σ(1,2,4,5,7,8,13,15)

 Hãy cho biết khi ngõ vào  Hãy cho biết khi ngõ vào  Z = f(d,c,b,a) = Σ(0,1,4,5,7,9,11,13,15)
tăng thì tài nguyên và thời tăng thì tài nguyên và
gian theo hàm nào thời gian theo hàm nào  V = f(d,c,b,a) = Σ(1,3,4,5,7,8,13,14,15)
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn

6.6. CÁC CÂU HỎI KIỂM TRA 6.6. CÁC CÂU HỎI KIỂM TRA
 Câu 6.8  Câu 6.8

 Cho hàm X = f(d,c,b,a) = Σ(1,4,5,7,13,15)

 Hãy cho ví dụ minh họa static hazard và cách khắc phục  Hãy chứng minh hàm này có bị nguy về thcho ví dụ minh
họa static hazard và cách khắc phục

Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn

6.6. CÁC CÂU HỎI KIỂM TRA 6.4. VHDL SYNTHESIS FLOW. 4. LOGIC SYNTHESIS

 Câu 6.4 Because of the large number of fan-ins for the and and or
gates, the two-level sum-of-products form can only be
 Hãy giải thích bảng sau implemented by using a special ASIC structure, known as
programmable logic array (PLA), and, with some
modification, by using programmable array logic (PAL)-based
CPLD devices.

Logic synthesis generates an optimized netlist that utilizes

generic components.
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn

41
6.2. REALIZATION OF VHDL OPERATORS
6.4. VHDL SYNTHESIS FLOW. 4. LOGIC SYNTHESIS - PAL - PLA 5. REALIZATION OF AN OPERATOR WITH CONSTANT OPERANDS

Caáu truùc PAL  Caáu truùc PLA

A
Give: x = “00000000”
A
B Excute: x <= x(6 downto 0) & not x(7);
B AB+AB+AB+AB

Result: x <= “00000001”

AB+AB
AB+AB
AB+AB
Give: x = “00000000”
AB+AB

 PAL coù AND laäp (b) PLA type array

Excute: x <= not x(0) & x(7 downto 1);
trình vaø OR coá ñònh
 PLA coù AND laäp Result: x <= “1000000”
taïo ra caùc bieåu thöùc
trình vaø OR laäp
SOP
trình
Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn Nguyễn Đình Phú. ĐHSP kỹ thuật tp HCM. Thiết kế vi mạch với VHDL. Chapter 5: Sequential signal assignment of VHDL. www.hcmute.edu.vn

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