EEE 466: Analog Integrated Circuits Laboratory

Lab Title
Study of Single Stage Common Source CMOS Amplifier
Design

Prepared by:
Naved Sadat Yamin
ID: 1806034

Lab partner:
H M Tahmeed-Ul-Islam
ID: 1806049

Group-12
Level-Term: 4-1

Submission Date:
015.07.2023
Abstract:
In this experiment, we examined five distinct configurations of single-stage CS amplifiers. These
stages include: Common-Source (CS) Stage with a resistive load, CS Stage with a diode-
connected load, CS Stage with a current source load, CS Stage with an active load, and CS Stage
with a triode load. For each configuration, we determined the appropriate bias voltage and
applied a small AC signal of 10 mV on top of the DC voltage. Then, we conducted a small-signal
AC analysis to determine the amplification characteristics of the amplifier.
Introduction:
Common source amplifiers are highly favored due to their exceptional benefits such as
remarkably high input impedance and low-noise output. These advantages make them more
commonly employed compared to other amplifier circuits. The simplicity and high input
impedance of common source amplifiers make them a popular choice in numerous applications,
including amplification of sensor signals and low-noise RF applications. The objective of this
laboratory experiment is to become acquainted with common source CMOS amplifiers and
simulate different topologies. For each topology, we determine the bias voltage and currents, and
then generate plots illustrating the small signal input, output, and low-frequency gain.
Common Source Stage with Resistive Load:
Initially, we constructed the DC bias circuit by connecting a resistor to the drain terminal of the
NMOS transistor. In this setup, the value of Vdc was fixed at 1V, while Vgs was varied. By
analyzing this circuit, we obtained the curve of gm (transconductance) as a function of Vgs to
identify the point of maximum gm.
Subsequently, we proceeded to set up the small signal AC circuit. Here, a small sinusoidal signal
with an amplitude of 10mV and frequency of 100Hz was added to the DC gate voltage. A 1MΩ
load was connected to the drain terminal through capacitor coupling. The parameters used for
this setup were VDD = 1.8V, VGS = 0.45V, RD = 2kΩ, and Finger = 20. Through transient
analysis, we plotted the input and output signals, and by employing a frequency sweep method,
we generated a plot showing the gain as a function of frequency.
CS amplifier with resistive load:

Fig: CS amplifier with resistive load

Fig:Common Source stage with resistive load (capacitor coupled)

CS Stage with Diode Connected Load:
Here we replace resistive load with an NMOS of W/L=480/100
Here gm2=(un)*Cox(W/L)(Vgs-Vt)=Kn*Vov

Fig:Common Source Stage with Diode Connected Load

CS Stage with Current Source Load:
In this case, the resistor RD has been substituted with a PMOS transistor operating in saturation
mode. By performing DC analysis, we determine the DC bias current ID and the corresponding
voltage VD. We then proceed to analyze the input and output AC waveforms. Additionally, we
modify the parameters of the PMOS transistor to have a width-to-length ratio (W/L) of 4800/400
and a threshold voltage (Vb) of 1.35V. We simulate the circuit with these updated parameters to
observe the resulting changes. It's important to note that the PMOS transistor is operated in
saturation mode throughout this process.

Fig:CS stage with Current Source Load

CS Stage with Active Load:
A complementary CS stage configuration has been implemented, allowing both the PMOS and
NMOS transistors to act as amplifiers. The circuit parameters used were VDD = 1.8V, VGS =
0.87V, with the PMOS transistor have a (W/L) of 4800/100 and the NMOS transistor have a
W/L of 2400/100. Similarly to earlier experiments, we conducted simulations to determine the
DC bias voltages and currents, observed the input/output waveforms, and calculated the small
signal gain for this

Fig:CS stage with Active Load

CS Stage with Triode Load :
In the final topology, the PMOS operates in the deep triode region. We have performed the
exact same works as before. Here, ��� = 1.8 �, ��� = 0.45 �, �� = 1.1 �, �/� = 4800/100 for
NMOS and �/� = 2400/100 for PMOS.

Fig:CS stage with Triode Load

Results:
Task 1-1 results:
i)

Fig: Id Vs VGS Graph of CS stage with resistive load

Fig: Vout Vs VGS Graph of CS stage with resistive load

 Fig: gm Vs VGS
ii) By observing the graph, we can determine that the maximum transconductance occurs at VGS
= 0.810V. Consequently, the gain (Av) is also maximized at this particular point, as Av is given
by Av = -gm * Rd for a common-source (CS) amplifier.
iii) When there is a large signal swing, the gain of the amplifier will vary as VGS changes. This
variation introduces distortion in the output signal.
iv) To increase the output swing, we need to increase VDD
v)Acoutputs:

Fig:Small signal input and output waveform of CS stage with resistive load

From the graph ,we get that gain Av=-25.5/10=-2.5 approx.

From figure , gm(max) = 1.25125, and from the circuit, �� = 2 �٠. So, theoretical Av= -
gm*Rd=2.5025, which is close to the simulated result.

Fig:Ac gain and phase vs frequency of CS stage with resistive load

Here gain Av=-7.96 dB at 100 Hz, which is -2.49, almost like before.

Task 1-2:
i)

Fig:gm&Id vs Vgs graph of CS stage with Diode Connected Load

ii)Here gain Av=-7 approx ,which is -2.22587.Gain vs frequency graph is shown
 Fig:AC gain&phase vs frequency plot for CS stage with diode connected load
Iii)To increase the gain, we can either increase the W/L ratio of the first MOSFET to enhance
gm1 or decrease the W/L ratio of the second MOSFET to reduce gm2. By adjusting these
parameters, we can effectively raise the overall gain of the amplifier.
Task 1-3:
i) DC bias voltage VD = 629.45 mV
ii) The small signal input and output waveform are given below:

iii)
Fig:Small Signal Input and output waveform of CS stage with current source
load

iv) Here gain Av=-38/10=-3.8

v) The gain formula is Av = −gm(��1 || ��2). Either ��1 or ��2 can be increased by
increasing channel length of the MOSFETs, resulting in a higher gain.
 vi) W/L for the PMOS was changed to 4800/400 and �� = 1 � and the following input
output waveforms were obtained-

vii)
Fig:Small signal input and Output Waveform for current change
Here, gain �� = −62.8/10 = −6.28, which has significantly increased. Increasing L2 also
increases the overdrive voltage, and thus Vds required to maintain the PMOS saturated. This is
why the gate voltage was lowered so that the MOS remains in saturation region.

Task 1-4:
i) DC bias voltage VD = 804.195 mV. We had to increase the bias voltage VGS from 0.45
V to 0.87 V because it is now common to both MOSFETs and the value 0.87V ensures
that both operate in saturation (for pMOS, ��� = 1.8 – 0.87 = 0.93�)
ii) The small signal input and outputs-

Fig: Small Signal Input and Output Waveform of CS stage with Active load
iii) Small signal gain, Av = - 54/10 = -5.4, which is significantly higher than that of CS stage
with current source load with the same PMOS (which was -3.8)
iv) The drawback of this design is that both FETs must operate in the saturation area, which
requires maintaining VGS at a precisely determined intermediate value because it is not
flexible. Design issues arise as a result of the challenging maintenance of the FETs in the
saturation zone.

Task 1-5:
i) DC bias voltage �� = 1.3914 �. For the pMOS, ��� = 1.8 – 1.3914 = 0.4086 �,which is
less than ��� = (1.8 – 1.1) = 0.7 �. So, it is operating in the triode region.

ii) Small signal input and output-

 Fig : Small Signal Input and Output for CS stage with Triode Load
iii) Here Gain Av=-26/10=-2.6

Conclusion:
Each of the five topologies we studied in this experiment has its own advantages and
disadvantages. The resistive load topology is difficult to manufacture because of strict resistance
requirements. So, we explored other topologies that use transistors instead of resistors, which are
easier to make.
We also looked at ways to make CS amplifiers more linear. One method is to increase the DC
bias voltage, but this reduces power efficiency. Another way is to adjust the W/L ratio, which
affects the gain but also limits linearity.
In practical applications, PMOS amplifiers have their uses. They require less gate voltage but
have lower gain when operated in the deep triode region.
Considering these design factors is important when building amplifiers for real-world
applications.