COA QuestionBank - 1
COA QuestionBank - 1
Course: B.Tech. III Semester Course Name: Computer Organization and Architecture
Topics Covered
Register Transfer and Micro-operations: Register Transfer Language, Register Transfer, Bus and
Memory Transfers, Arithmetic Micro-operations, Logic Micro-operations, Shift Microoperations,
Arithmetic logic shift unit
Basic Computer Organizations and Design: Instruction Codes, Computer Registers, Computer
Instructions, Timing and Control, Instruction Cycle, Memory - Reference Instructions, Register -
Reference Instructions, Input - Output Instructions
6. The devices that provide the means for a computer to communicate with the user or other
computers are referred to as:
7. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out
shift register that is initially clear. What are the Q outputs after two clock pulses?
(a) Holds the address of instruction (b) Holds the address of memory
(c ) PC (d) DR
10. The symbolic description of transfer from one register to another register is known
as ___________.
Short Questions:
Q.1. What are micro-operations? What are its various types? Illustrate the implementation of
each category of micro-operations through its block diagram(s).
Q.2. What is a bus? Design a bus system capable of transmitting data from any register from a
group or to registers (32-bits each) to any other register in a group of 8 registers (32-bits
each). Illustrate the logic through its block diagram?
Q.3. Design an arithmetic circuit with one selection variable S and two n-bit date inputs A and
B. The circuit generates the following four arithmetic operations in conjunction will the
input carry Cin. Draw the logic diagram for the first two stages.
S cin=0 cin=1
0 D=A+B D=A+1
1 D=A-1 D=A+B’+1
Q.4. The output of four registers R0, R1, R2, R3 are connected through 4-to 1 line multiplexers
to the inputs of a fifth register R5. Each register is eight bits long. The required transfers are dictated
by four timing variables T0 through T3 as follows:
To: R5R0
T1: R5R1
T2: R5R2
T3: R5R3
Timing variables are mutually exclusive. Draw a block diagram showing the hardware
implementation of the register transfers.
Q.5. What are the various phases of an instruction cycle? Give the micro-operations
of fetch and decode phases. How the first two register transfer statements are
Implemented?
Q.6. Tabulate various memory reference instruction. Explain BUN and BSA.
Q.7. Consider the instruction format of the basic computer for each of the following 16-bit
instruction give the equivalent four digits hexadecimal code and explain that what an instruction
going to perform.
a. 0001 0000 0010 0100
b. 1011 0001 0010 0100
c. 0111 1000 0000 0000
d. 0111 0000 1000 0000
e. 1111 1000 0000 0000