EXPT NO:

DATE:

AIM:

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. 2- I/P AND gate IC 7408 1
2. 3- I/P AND IC7411 1
3. gate OR gate IC 7432 1
4. NOT gate IC 7404 1
5. 2- I/P NAND gate IC7400 1
6. 3- I/P NAND IC7410 1
7. gate NOR gate IC7402 1
8. EX-OR gate IC7486 1
9. IC Trainer Kit - 1
10. Patch cords - Few

THOERY:

Logic gates are the basic elements that make up a digital system. The gate is a digital
circuit with one or more inputs, but only one output. By connecting the different gates in
different ways, we can build circuits that perform arithmetic and other functions.
The operation of a logic gate can be easily understood with the help of “truth table”.
A truth table is a table that shows all the input-output possibilities of a logic circuit ie., the
truth table indicates the outputs for different possibilities of the inputs.
The types of gates available are the AND, OR, NOT, NAND, NOR, exclusive-OR
and the exclusive-NOR. Except for the exclusive-NOR gate they are available in monolithic
integrated form.

AND gate:
The AND gates has two or more inputs. It performs a logical multiplication. The
output is HIGH (1), when both the inputs are 1; otherwise, the output from the gate is LOW
(0). The output from the AND gate is written as A.B.

1
OR gate:

NOT gate:

2
AND gate:

3- Input AND gate:

3
OR gate:
The OR gates has two or more inputs. It performs a logical addition. The output is HIGH
(1), if any of the inputs are 1; the output is LOW (0) if and only if all the inputs are 0. The
output from the AND gate is written as A+B.

NOT gate:
The NOT gate has only one input. It performs a basic logic function called
inversion. The output is HIGH (1), when the input is 0; the output is LOW (0) when the
input is 1. The output from the NOT gate is written as A’.

NAND gate:
The NAND gate is a contraction of AND-NOT. It has two or more inputs. The output
is HIGH (1), when any of the inputs are 0; the output is LOW (0), if and only if all the inputs
are 1. The output from the AND gate is written as (A.B)’. It is a universal gate.

NOR gate:
The NOR gate is a contraction of OR-NOT. It has two or more inputs. The output is
HIGH (1), when all inputs are 0; the output is LOW (0), when any of the inputs are 1. The
output from the AND gate is written as (A+B)’. It is a universal gate.

EX-OR gate:
The EX-OR gate has two or more inputs. The output is HIGH (1), when odd number
of inputs is 1. The output from the AND gate is written as (A B).

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth table.

4
2- Input NAND gate:

3- Input NAND gate:

5
NOR gate:

EX-OR gate:

6
RESULT:
Thus, the logic gates are studied and their truth tables are verified.

7
EXPT NO: DESIGN AND IMPLEMENTATION OF 4 – BIT BINARY ADDER /
DATE: SUBTRACTOR USING IC7483

AIM:
To study the 4-bit binary adder/subtractor using IC7483.

REQUIREMENT

S.No.
Name of the Specification Quantit
apparatus s y

1 Digital Trainer kit - 1

2 OR gate IC 7432 1
3 AND gate IC 7408 1
4 Binary Adder / IC 7483 2
Subtractor
5 Connecting wires - some

THEORY

The full adder/sub tractors are capable of adding/subtracting only two single
digit binary numbers along with a carry input. But in practice we need to
add/subtract binary numbers, which are much longer than just one bit. To
add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.

Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor. The two 4-
bit input binary numbers are A1 through A4 and B1 through B4. The sum is
obtained from S1 through S4. C0 is the input carry and C4 the output carry. Test the 4-
bit binary adder 7483 by connecting the power supply and ground terminals. Then
connect the four A inputs to a fixed binary numbers such as 1001 and the B inputs
and the input carry to five toggle switches. The five outputs are applied to indicator
lamps. Perform the addition of a few binary numbers and check that the output sum
and output carry give the proper values. Show that when the input carry is equal to
1, it adds 1 to the output sum.

Binary subtractor: The subtraction of two binary numbers can be done by taking
the 2’s complementof the subtrahend and adding it to the minuend. The 2’s
8
complement can be obtained by taking the 1’s complement and adding. To
perform A-B, we

9
 complement the four bits of B, add them to the four bitsof A, and add 1 through the
input carry. The four XOR gates complement the

bits of B when the mode select M=1(because x Θ 0 = x ) and leave the bits of B
unchanged when M=0(because x Θ 0 = x ) .Thus , when the mode select M is equal
to 1, the input carry C0 is equal 1 and the sum output is A plus the 2’s complement
of
B. when M is equal to 0, the input carry is equalto 0 and the sum generates A+B.

Functional symbol for IC 7483:

Operand1 Operand2

B B B A A A

Cout 4-bit IC Cin

Output

Pin Diagram of IC7483:

10
Circuit Diagram for 4-bit Binary adder/subtractor:

2- BIT BINARY ADDER:

11
4- BIT BINARY SUBTRACTOR

12
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode M =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.
4. Repeat the same step in step 3 by keeping M=1 such that circuit will
operate insubtraction mode.

RESULT:
Thus the 4-bit Binary Adder / Subtractor using IC7483 is been implemented for both
additionand subtraction and the corresponding truth tables are verified.

13
EXPT NO: DESIGN AND IMPLEMENTATION OF CODE CONVERTER
DATE:

AIM:
To design and implement 4-bit
1. Binary to Gray code Converter
2. Gray to Binary code Converter
3. BCD to Excess-3 code Converter
4. Excess-3 code to BCD Converter

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer - 1
2. kit EX-OR IC7486 1
3. gate NOT IC7404 1
4. gate OR gate IC7432 1
5. 2- Input AND gate IC7408 1
6. 3- Input AND gate IC7411 1
7. Patch cords - As Required

THEORY:
An availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for the same
information. Thus, code converter is a circuit that makes the two systems compatible even
though each uses different binary code.
The input variable is designed as B3, B2, B1, B0 and the output variables are designed
as G3, G2, G1, G0. From the truth table, combinational circuit is designed. The Boolean
functions are obtained from K-Map for each output variable.

14
BINARY TO GRAY CODE CONVERTER:
TRUTH TABLE:

Binary code Gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K- Map Simplification:

15
Logic Diagram:

GRAY TO BINARY CODE CONVERTER:

TRUTH TABLE:

Gray code Binary code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

16
K-Map Simplification:

Logic Diagram:

To convert from binary code to Excess-3 code, the input lines must supply the bit
combination of elements as specified by code and the output lines generate the corresponding
bit combination of code. Each one of the four maps represents one of the four outputs of the
circuit as a function of the four input variables.
17
 A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit.
BCD TO EXCESS-3 CODE:
Truth table:

BCD code Excess-3 code

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

K-Map Simplification:

18
Logic Diagram:

EXCESS-3 TO BCD CONVERTER:

Truth Table:

Excess-3 code BCD code

E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

19
K-Map Simplification:

20
Logic Diagram:

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:

Thus the 4-bit

1. Binary to Gray code Converter
2. Gray to Binary code Converter
3. BCD to Excess-3 code Converter
4. Excess-3 code to BCD Converter was designed and implemented.

21
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF BCD ADDER
DATE:

AIM:
To design and implement the BCD adder by using IC7483.

REQUIREMENTS:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1

2 OR gate IC 7432 1

3 AND gate IC 7408 1

4 Binary Adder / IC 7483 2

Subtractor
5 Connecting wires - some

THEORY
The full adder/sub tractors are capable of adding/subtracting only two single
digit binary numbers along with a carry input. But in practice we need to
add/subtract binary numbers, which are much longer than just one bit. To
add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.
Binary adder:
IC type 7483 is a 4-bit binary parallel adder/subtractor. The two 4-bit input
binary numbers are A1 through A4 and B1 through B4. The sum is obtained from
S1 through S4. C0 is the input carry and C4 the output carry. Test the 4-bit binary
adder 7483 by connecting the power supply and ground terminals. Then connect the
four A inputs to a fixed binary numbers such as 1001 and the B inputs and the input
carry to five toggle switches. The five outputs are applied to indicator lamps.
Perform the addition of a few binary numbers and check that the output sum and
output carry give the proper values. Show that when the input carry is equal to 1, it
adds 1 to the output sum.
Binary subtractor:
The subtraction of two binary numbers can be done by taking the 2’s
complementof the subtrahend and adding it to the minuend. The 2’s complement
can be obtained by taking the 1’s complement and adding. To perform A-B,
22
we
complement the four bits of B, add them to the four bitsof A, and add 1 through the

23
 input carry. The four XOR gates complement the bits of B when the mode select
M=1(because x Θ 0 = x) and leave the bits of B unchanged when M=0(because x
Θ 0 = x). Thus, when the mode select M is equal to 1, the input carry C0 is equal 1
and the sum output is A.
plus the 2’s complement of B. when M is equal to 0, the input carry is equal to
0 and the sumgenerates A+B.

Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0

Cout 4 bit IC 7483

Cin

Output

24
Pin Diagram of IC7483:

25
26
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode CE =0 such that the circuit will operate in addition mode.
Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.

RESULT:

Thus, the BCD Adder using IC7483 is been implemented for and the corresponding
truthtables are verified.

27
EXPT NO: DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER
DATE:
AIM:
To design and implementation encoder and decoder using logic gates.

APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3-I/P NAND IC7410 2
3. gate NOT gate IC7404 1
4. OR gate IC7432 3
5. Patch - Few
cords

THEORY:
Encoder:
An encoder is a digital circuit that performs inverse operation of a decoder. An
encoder has 2n input lines and ‘n’ output lines. In encoder the output lines generate the
binary code corresponding to the input value. In octal to binary encoder, it has eight inputs,
one for each octal digit and three output that generates the corresponding binary code. In
encoder it is assumed that only one input has a value of one at any given time otherwise the
circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero.
The zero outputs can also be generated when D0=1.

Decoder:
A decoder is a multiple output logic circuit which converts input into coded output
where input and output codes are different. The input code generally has few bits than the
output code. Each input code word produces a different output code word i.e., there is one to
one mapping can be expressed in truth table. In block diagram of decoder circuit, the
encoded information is present as n input producing 2n possible outputs. The 2n output values
are from 0 through out 2n-1.

28
ENCODER:
Logic Diagram (2-to-4- Line Decoder with Enable Input):

Truth Table:

INPUTS OUTPUTS
E A B D3 D1 D2 D3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

29
Logic Diagram:

Truth Table:

INPUTS OUTPUTS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

30
RESULT:
Thus, the design and implementation of encoder and decoder using logic gates
wasdone successfully.

31
EXPT NO: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
DATE: DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates.

APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3-I/P AND GATE IC7411 2
3. NOT GATE IC7404 1
4. OR GATE IC7432 1
5. Patch cords - Few

THEORY:
Multiplexer:

Multiplexer means transmitting a large number of information units over a

smallnumber of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are
2n input line and ‘n’ selection lines whose bit combination determine which input is selected.
It is called as data selector, because the output depends on the input data bit that is selected.

Demultiplexer:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used as
Demultiplexer.
In the 1:4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

32
4:1 MULTIPLEXER:
BLOCK DIAGRAM:

Function table:

S1 S0 INPUTS, (Y)

0 0 D0= D0 S1’S0’
0 1 D1= D1 S1’S0
1 0 D2= D2 S1S0’
1 1 D3= D3 S1S0

Output, Y= D0 S1’S0’ +D1 S1’S0+ D2 S1S0’ +D3 S1S0

Logic Diagram:

33
Truth table:

S1 S0 OUTPUTS, (Y)

0 0 D0
0 1 D1
1 0 D2
1 1 D3

1: 4 DEMULTIPLEXER:
Block Diagram:

Function Table:

S1 S0 INPUT, X

0 0 D0= XS1’S0’
0 1 D1= XS1’S0
1 0 D2= XS1S0’
1 1 D3= XS1S0

Output, Y= XS1’S0’ +XS1’S0+ XS1S0’ +XS1S0

34
Logic Diagram:

Truth Table:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

35
PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus, the multiplexer and demultiplexer was designed and implemented using logic gates
was verified.

36
EXPT NO: DESIGN AND IMPLEMENTATION OF 3-BIT SYNCHRONOUS
UP/DOWN COUNTER
DATE:

AIM:
To design and implement 3 bit synchronous up/down counter using JK flip-flop.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. JK Flip-flop IC7476 2
3. 3-I/P NAND IC7411 1
4. gate NOT gate IC7404 1
5. OR gate IC7432 1
6. EX-OR gate IC7486 1
7. Patch Cords Few

THEORY:
A Counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that
is capable of progressing in increasing order or decreasing order through a certain sequence.
An up/down counter is also called bi-directional counter. Usually up/down operation of the
counter is controlled by up/down signal. When this signal high counter goes through up
sequence and when up/down signal is low counter follows reverse sequence.
The counter counts upwards when UP control are logic ‘1’ and DOWN control is
logic ‘0’. In this case the clock input of each flip-flop other than the LSB flip-flop is fed from
the normal output of the immediately preceding flip-flop. The counter counts downwards
when the UP controls input are logic ‘0’ and DOWN control is logic ‘1’. In this case,
theclock input of each flip-flop other than the LSB flip-flop is fed from the complemented
output of the immediately preceding flip-flop.

37
 3- BIT SYNCHRONOUS UP/DOWN COUNTER:
STATE DIAGRAM:

TRUTH TABLE:

Input Present State Next State A B C

Up/Down’ QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 x 1 x 1 x
0 1 1 1 1 1 0 x 0 X 0 x 1
0 1 1 0 1 0 1 x 0 X 1 1 x
0 1 0 1 1 0 0 x 0 0 x x 1
0 1 0 0 0 1 1 x 1 1 x 1 x
0 0 1 1 0 1 0 0 x X 0 x 1
0 0 1 0 0 0 1 0 x X 1 1 x
0 0 0 1 0 0 0 0 x 0 x x 1
1 0 0 0 0 0 1 0 x 0 x 1 x
1 0 0 1 0 1 0 0 x 1 x x 1
1 0 1 0 0 1 1 0 x X 0 1 x
1 0 1 1 1 0 0 1 x X 1 x 1
1 1 0 0 1 0 1 x 0 0 x 1 x
1 1 0 1 1 1 0 x 0 1 x x 1
1 1 1 0 1 1 1 x 0 X 0 1 x
1 1 1 1 0 0 0 x 1 X 1 x 1

38
EXCITATION TABLE: (JK Flip-Flop)

Q Q t+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
K-MAP SIMPLIFICATION:

39
LOGIC DIAGRAM:

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.

RESULT:

Thus 3- bit synchronous up/down counter was designed and implemented

successfully.

40
EXPT NO: DESIGN AND IMPLEMENTATION OF 4-BIT RIPPLE COUNTER &
DATE: MOD-10/MOD-12 RIPPLE COUNTERS

AIM:
To design and implement 4-bit ripple counter, MOD-10 and MOD-12 ripple counter.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. JK Flip-flop IC7476 2
3. NAND gate IC7400 1
4. Patch cords - Few

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulse arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counters, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous, first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or Q’ output of pervious stage.
A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-
flop drives the clock input of the following flip-flop. The number of flip-flops in the
cascaded arrangement depends upon the number of different logic states that it goes through
before it repeats the sequence, a parameter known as the MODulus of the counter.
In a ripple counter, also called an asynchronous counter or a serial counter, the clock
input is applied only to the first flip-flop, also called the input flip-flop, in the cascaded
arrangement. The clock input to any subsequent flip-flop comes from the output of its
immediately preceding flip-flop. For instance, the output of the first flip-flop acts as the clock
input to the second flip-flop, the output of the second flip-flop feeds the clock input of the
third flip-flop and so on.

41
 4- BIT RIPPLE COUNTER:
PIN DIAGRAM: (JK Flip-Flop)

Function Table for 7476:

Inputs Outputs

Preset Clear Clock J K Q Q’

0 1 X X X 1 0

1 0 X X X 0 1

0 0 X X X 1 1

1 1 0 0 No Change

1 1 0 1 0 1

1 1 1 0 1 0

1 1 1 1 Toggle

42
LOGIC DIAGRAM: (4-Bit Ripple Counter)

TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

43
 A four-bit ripple counter is implemented with negative edge-triggered J-K flip-flops
wired as toggle flip-flops. The output of the first flip-flop feeds the clock input of the second,
and the output of the second flip-flop feeds the clock input of the third, the output of which in
turn feeds the clock input of the fourth flip-flop. The outputs of the four flip-flops are designated
as Q0 (LSB flip-flop), Q1, Q2 and Q3 (MSB flip-flop).
LOGIC DIAGRAM: (MOD-10 Ripple Counter)

TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

44
LOGIC DIAGRAM: (MOD-12 Ripple Counter)

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

45
PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus 4-bit ripple counter, MOD-10 and MOD-12 ripple counter was designed and
implemented successfully.

46
EXPT NO: DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS
DATE:

AIM:
To design and implement
1. Serial in serial Out (SISO)
2. Serial in parallel Out (SIPO)
3. Parallel in serial Out (PISO)
4. Parallel in parallel Out (PIPO)

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer - 1
2. kit D-Flip IC7474 2
3. flop AND IC7408 1
4. gate OR IC7432 1
5. gate IC7404 1
6. NOT gate - Few
Patch cords

THEORY:
A register is capable of shifting its binary information in one or both directions is known
as shift register. A logical configuration of shift register consist of a D flip flop cascaded
with output of one flip flop connected to input of next flip flop. All flip flopsreceive common
clock pulses which causes the shift in the output of the flip flop. The simplest possible shift
register is one that uses only flip flop. The output of a given flip flop isconnected to the input
of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.

47
SHIFT REGISTER:
PIN DIAGRAM: (D-Flip-Flop)

Function Table:

Inputs Outputs
Preset Clear Clock D Q Q’
0 1 X X 1 0
1 0 X X 0 1
0 0 X X 1 1
1 1 0 0 1

1 1 1 1 0
1 1 0 X No Change

SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:

48
TRUTH TABLE:
CLK Serial IN Serial OUT
1 1 0
2 1 0
3 1 0
4 1 1
5 0 1
6 0 1
7 0 1
8 0 0

Serial IN Parallel OUT:

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA
Q3 Q2 Q1 Q0
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1

49
Parallel IN Serial
OUT:
LOGIC DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUT
S/ L’ CLK
A B C D Q
0 0 1 0 0 1 1
1 1 1 0 0 1 0
1 2 1 0 0 1 0
1 3 1 0 0 1 1

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Parallel IN Parallel
OUT: Logic Diagram:

TRUTH TABLE:

DATA INPUTS OUTPUT

CLK
D3 D2 D1 D0 Q3 Q2 Q1 Q0
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.

RESULT:
Thus, the design and implementation of
1. Serial in serial Out (SISO)
2. Serial in parallel Out (SIPO)
3. Parallel in serial Out (PISO)
4. Parallel in parallel Out (PIPO) were done successfully.

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EXPT NO:
STUDY OF UNIVERSAL SHIFT REGISTER
DATE:

AIM:

To study and verify the load, shift and rotate operation of a 4-bit shift register.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Quantity

1. Digital IC Trainer .... 1
2. IC 74195 ... 1
3. Connecting Wires ...
THEORY:

A register is a group of binary storage cells capable of holding binary information. A

group of flip flops constitutes a register, since each flip-flop can work as a binary cell. An
n-bit register, has n flip-flopsand is capable of holding n-bits of information. In addition
to flip-flops a register can have a combinational part that performs data-processing tasks.

Shift Register: A register capable of shifting its binary contents either to the left or to the
right is called a shift register. The shift register permits the stored data to move from a
particular location to some other location within the register. Registers can be designed
using discrete flip-flops (S- R, J-K, and D-type). The data in a shift register can be shifted
in two possible ways: (a) serial shifting and (b) parallel shifting. The serial shifting
method shifts one bit at a time for each clock pulse in a serial manner, beginning with
either LSB or MSB. On the other hand, in parallel shifting operation, all the data (input or
output) gets shifted simultaneously during a single clock pulse. Hence, we may say that
parallel shifting operation is much faster than serial shifting operation.

8- bit Universal Shift Register: IC 74195 is a 4-bit TTL MSI having both serial/parallel
input and serial/parallel output capability. The pinout diagram of IC 74195 is shown.

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When the SH / LD input is LOW, the data on the parallel inputs, i.e., A, B, C, and D are
entered synchronously on the positive transition of the clock. When SH / LD is HIGH, the
stored data will shift right (QA to QD) synchronously with the clock. J and K are the
serial inputs to the first stage of the register (QA); QD can be used for getting a serial
output data. The active low clear is asynchronous.

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Example:
Right Shift Operation: Input data: 1011

Clock QA QB QC QD
0 1 0 1 1
1 0 1 0 1
2 0 0 1 0
3 0 0 0 1
4 0 0 0 0
1 0 0 1 1 0 0 1

0 1 0 0 1 1 0 0

PROCEDURE:

1. Load data using parallel loading

2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 OFF (0) connect logic input switch
5. Press the clock button

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Example:
Rotate Right Operation: Input data: 1011

Clock QA QB QC QD
0 1 0 1 1
1 1 1 0 1
2 1 1 1 0
3 0 1 1 1
4 1 0 1 1

1 0 1 1 0 0 0 1

PROCEDURE:

1. Load data using parallel loading

2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 connects to the QD logic output switch
5. Press the clock button

RESULT:
Thus the 4-bit Universal Shift Register was studied successfully.

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