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Datapath Design - 1

This document discusses datapath design for fixed-point arithmetic circuits. It covers half adders, full adders, serial and parallel binary adders, subtractors, overflow handling, and different adder designs including ripple carry adders, carry lookahead adders, and adder expansion. The key points are: - It describes the basic building blocks for addition like half adders and full adders along with their truth tables. - Serial adders are slow but use less hardware while parallel adders provide faster addition but use more hardware. - Subtraction can be performed using 2's complement representation and adding the minuend and complement of the subtrahend. - Carry lookahead

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Md. Atikur Rahman
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38 views

Datapath Design - 1

This document discusses datapath design for fixed-point arithmetic circuits. It covers half adders, full adders, serial and parallel binary adders, subtractors, overflow handling, and different adder designs including ripple carry adders, carry lookahead adders, and adder expansion. The key points are: - It describes the basic building blocks for addition like half adders and full adders along with their truth tables. - Serial adders are slow but use less hardware while parallel adders provide faster addition but use more hardware. - Subtraction can be performed using 2's complement representation and adding the minuend and complement of the subtrahend. - Carry lookahead

Uploaded by

Md. Atikur Rahman
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Lecture 2

Datapath Design
Book of John P. Hayes
Fixed-Point Arithmetic
✔ Addition
✔ Subtraction
✔ Multiplication
✔ Division
Half Adder
X 0 Y0 S0 C 0
0 0 0 0
X0 0 1 1 0
S0 1 0 1 0
1 1 1 1

Y0 C0

(a) Half Adder (b) Truth Table

S0 = X0 xor Y0 and C0 = X0Y0


Full Adder

(a) Full Adder (b) Truth Table


s0 = x0 xor y0 xor c-1
c0 = x0y0 + x0c-1 + y0c-1
Full Adder

(b) Symbol

(a) Two-level AND-OR logic circuit


Serial Binary Adder
✔ Least expensive circuit
in terms of hardware
cost.
✔ It adds the numbers bit
by bit and so requires n
clock cycle to compute
the sum of two n-bit
numbers.
✔ Circuit size is
independent of n.
Ripple Carry Adder / Parallel Adder

✔A 1 appearing on the carry in line of a 1-bit adder cause it to generate a 1 on its


carry out line. So, the carry signal propagate through the adder from right to left.
✔The maximum signal propagation delay is nd, where d is the delay of a full-adder
stage.
✔The amount of hardware increase linearly with n.
Subtracter for 2’s Complement
Number
✔ When s =0 then X xor s = X
✔ When s=1 then X xor s = X
Subtracter for 2’s Complement
Number
Subtracter
✔ For sign-magnitude number, it is useful to construct a subtracter on the
full (1-bit) subtracter function zi = xi xor yi xor bi-1

16 bit Adder
Overflow
✔ When the result of an arithmetic operation exceeds the standard word size
n, overflow occurs.
✔ Example: let n=8 X=11101011=23510 and Y=00101010=4210
Z= X+Y =11101011

+ 00101010
00010101 =2110 C7 =1

C7Z = 100010101 =27710 = 25610 + 2110

✔ The result of an addition simply wraps around when the largest number
2n-1 is exceeds.
✔ For n, the number range for unsigned number is 0 to 2n-1
Overflow
✔ We can never have overflow on adding a negative and positive number.
✔ Example: let n=8 X=11101011=-2110 and Y=00101010=+4210
Z= X+Y = 00010101 = 21 C7 =1
10
So, Cn-1 = 1 does not indicate overflow.
✔ Overflow in 2’s complement addition can result from adding 1) two
positive numbers or 2) two negative numbers.
✔ Case 1: Two numbers are positive.
Let n=4 +7 = 0111 +3 = 0011 so, 0111+0011 = 1010 so, cn-2 = 1
✔ Cn-2 =1 indicates that the magnitude of the sum exceeds the n-1 bits
allocated to it.
Overflow
✔ Case 2: Two numbers are negative.
Let n=4 -7 = 1001 -3 = 1101 so, 1001+1101 = 10110 so, cn-2 = 0
✔ Cn-2 =0 indicates the overflow.
✔ For n the number for 2’s complement number is +(2n-1-1) to -2n.
Overflow
✔ Zn-1Zn-2….Z0 : = Xn-1Xn-2…X0 + Xn-1 Yn-1 Cn-2 Zn-1 v
Yn-1Yn-2…Y0 0 0 0 0 0
✔ v = Xn-1Yn-1Cn-2 + Xn-1Yn-1Cn-2
✔ v = Cn-1 xor Cn-2 0 0 1 0 1

0 1 0 1 0

0 1 1 0 0

1 0 0 1 0

1 0 1 0 0

1 1 0 1 1

1 1 1 1 0
Ripple Carry Adder

✔ the carry signal propagate through the adder from right to left
✔ The maximum signal propagation delay is nd, where d is the delay of
a full-adder stage.
High Speed Adder
✔ Reduce the time required to form carry signals.
✔ Approach: To compute the input carry needed by stage i
directly from carrylike signals obtained from all the
preceeding stages i-1, i-2, ..,0.
✔ Adders that use this principle are called carry-lookahead
adders.
Carry Lookahead Adder

✔generate signal gi = xiyi and propagate signal pi = xi + yi


✔ci = xiyi + xici-1 + yici-1 is the carry to be sent to the stage i+1.
✔ci = gi + pici-1
✔ci-1 = gi-1 + pi-1ci-2
✔ci = gi + pigi-1+pipi-1ci-2
4-bit Carry Lookahead Adder
✔ c0 = g0 + p0cin
c1 = g1 + p1g0 + p1p0cin
c2 = g2 + p2g1 + p2p1g0 + p2p1p0cin
c3 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0cin

✔ zi = xi xor yi xor ci-1 can be written as zi = pi xor gi xor ci-1


4-bit Carry Lookahead Adder
4-bit CarryLookahead Adder
✔ Maximum delay is 4d, where d is the average gate delay. It is
independent of number of input n.
✔ The complexity of the carry generation logic in the carry lookahead
adder, including its gate count, its maximum fan-in, and its maximum
fan-out, increase steadily with n.
✔ It limits n to 4.
Adder Expansion
✔ If we replace n 1-bit adder stages in the n-bit ripple carry adder with n k-bit
adders, we obtain an nk-bit adder.

Figure: A 16-bit adder composed of 4-bit adders linked by ripple-carry propagation


Adder Expansion
Design of a Complete 2’s
Complement Adder-Subtracter
Chapter 4, Section 4.1 of John P. Hayes Book

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