Week 2

Chapter 2: x86 Processor Architecture

Class 4
 Chapter Overview

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System

2
 General Concepts

• Basic microcomputer design

• Instruction execution cycle
• Reading from memory
• How programs run

Book's Page No 33

3
 Basic Microcomputer Design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of execution steps
• ALU performs arithmetic and bitwise processing

data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2

ALU CU clock

control bus

address bus

4
 Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events

one cycle

5
 What's Next

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• 64-Bit Processors
• Components of an IA-32 Microcomputer
• Input-Output System

6
 Instruction Execution Cycle

• Fetch
• Decode
• Fetch operands
• Execute
• Store output

7
 Reading from Memory
Multiple machine cycles are required when reading from
memory, because it responds much more slowly than the
CPU. The steps are:
1. Place the address of the value you want to read on the
address bus.
2. Assert (changing the value of) the processor’s RD
(read) pin.
3. Wait one clock cycle for the memory chips to respond.
4. Copy the data from the data bus into the destination
operand

8
 Cache Memory

• High-speed expensive static RAM both inside and

outside the CPU.
• Level-1 cache: inside the CPU
• Level-2 cache: outside the CPU
• Cache hit: when data to be read is already in cache
memory
• Cache miss: when data to be read is not in cache
memory.

9
 How a Program Runs
User

sends program
name to

Operating searches for Current

system program in directory

gets starting
cluster from returns to
System
loads and path
starts
Directory Program
entry

10
IA-32 Processor Architecture

• Modes of operation
• Basic execution environment
• Floating-point unit
• Intel Microprocessor history

11
 Modes of Operation
• Protected mode
• native mode (Windows, Linux)
• Real-address mode
• native MS-DOS
• System management mode
• power management, system security, diagnostics

• Virtual-8086 mode
• hybrid of Protected
• each program has its own 8086 computer

12
Basic Execution Environment

• Addressable memory
• General-purpose registers
• Index and base registers
• Specialized register uses
• Status flags
• Floating-point, MMX, XMM registers

13
 Addressable Memory

• Protected mode
• 4 GB
• 32-bit address
• Real-address and Virtual-8086 modes
• 1 MB space
• 20-bit address

14
 General-Purpose Registers

Named storage locations inside the CPU, optimized for

speed.
32-bit General-Purpose Registers

EAX EBP
EBX ESP
ECX ESI
EDX EDI

16-bit Segment Registers

EFLAGS CS ES
SS FS
EIP
DS GS

15
 Accessing Parts of Registers
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
8 8

AH AL 8 bits + 8 bits

AX 16 bits

EAX 32 bits

16
 Index and Base Registers

• Some registers have only a 16-bit name for their

lower half:

17
Some Specialized Register Uses (1 of 2)

• General-Purpose
• EAX – accumulator
• ECX – loop counter
• ESP – stack pointer
• ESI, EDI – index registers
• EBP – extended frame pointer (stack)
• Segment
• CS – code segment
• DS – data segment
• SS – stack segment
• ES, FS, GS - additional segments

18
Some Specialized Register Uses (2 of 2)

• EIP – instruction pointer

• EFLAGS
• status and control flags
• each flag is a single binary bit

19
 Status Flags
• Carry
• unsigned arithmetic out of range
• Overflow
• signed arithmetic out of range
• Sign
• result is negative
• Zero
• result is zero
• Auxiliary Carry
• carry from bit 3 to bit 4
• Parity
• sum of 1 bits is an even number

20
 Floating-Point, MMX, XMM Registers

• Eight 80-bit floating-point data registers ST(0)

• ST(0), ST(1), . . . , ST(7) ST(1)

ST(2)
• arranged in a stack
ST(3)
• used for all floating-point
ST(4)
arithmetic
ST(5)
• Eight 64-bit MMX registers
ST(6)
• Eight 128-bit XMM registers for single-
ST(7)
instruction multiple-data (SIMD) operations

21