Unit VI

Introduction to

11 Computer Architecture

11.1 Introduction to Ideal Microprocessor

short note on ideal
ideal
? Write a
a.1 What is microprocessor
[SPPU: June-22,
Marks 6]
microprocessor.
architecture
Ans. A microprocessor is an important part of a computer
on your
without which you will not be able to perform anything

computer some

t 1s a programmable
that takes in input, performs
device
desired output.
arithmetic and logical operations over
it and produces
which
device on a chip
in simple words, microprocessor is a digital
a
them and give
decode and execute
can fetch instructions from memory,

Tesults. understand
However, to
ideal microprocessor.
here is nothing like an
have introduced this hypothetical
we
unction of the microprocessor
tne
device.
Fig. Q.1.1 shows an
Output
ideal microprocessor P Microprocessor device
Input
with n inputs and m device
outputs.
Input signals are

applied from input

devices. The input Memory
devices may include unit

keyboard, mouse, mlcroprocessor

sensors, switches, etc. Flg. Q.1.1 An ideal
These signals are in teminals of the
at the input
the binary form and are applied
microprocessor.

(11- 1)
Digital Electronics and Logie Deslgn 11-2 Logle Deslgn
a n dLogtc 1-3 Introducton to
ComputeIrntrArchl
oductteloctnure
o elal
Electronics Computer Architecture

Microprocessor 11.2 Data Bus, Address Bus and Control Bus

ALU
Input interconnection structure ?
device Control unit Output What is
device a2
: The central processing
central unit, memory unit and VO unit are the
Register array are components/mo of microprocessor based systems. They
hardwa.

ogether with communicating each other and have paths for

work
ing the
connecting the modules together. The collection of paths connecting the
modules is called the interconnection structure
Memory
unit design of this interconnection structure will depend on the
The
hat must be made between modules.
Fig. Q.1.2 ldeal
microprocessor with ALU, control
exchanges

unlt and registor What is bus ?

array a.3
Microprocessor
of
processes these input signals according to group of wires,
A
Anscommunication
called bus is used to provide necessary signals
operations stored in the memory. The sequnce the Sealen. between modules.
to as of
operations uence for
is
program in the binary form. refered bus ? SPPU : June-22, Marks 6]
The processed a4 What is system
output in the binary form is fed to the that connects major microprocessor based system
output device may include output device. The Ans. A bus
indicators, displays, alarms, actuators components/modules (CPU, memory, VO) s called a system
bus. The
etc.
Microprocessor
an ALU.
also called Central
Processing Unit (CPU) consists system bus is a set of conductors that connects the CPU, memory and O
control unit and into three functional
register array. of
modules. Usually, the system bus is separated
The ALU
perfomms arithmetic and logical groups
received from an input device or operations on the data Address bus
memory.
Control unit controls the
computer.
instructions and flow of data within Data bus
the
Control bus
Register array consists of
D, E, H, L, and registers identified by letters like B, C,
accumulator. CPU Memory
Principal components of a CPU include
the
(ALU) that performs
arithmetic and logic Arithmetic Logic Unit
registers that supply operands to the ALU operations, processor Control
ALU and store the results
operations, and control unit that
a of bus
(from memory) and orchestrates the fetching
coordinated operationsexecution of
instructions by
components.
of the
ALU, registers directing
and otherthe System
bus
Data
bus

Address
bus

Interconnection structure
Fig. Q.4.1

Students
A Guide for Engineering
OIcODE
A Guide
for
Engineering Studen's
 11-
Inrodacti
Comer Archikertre

stre@urte .erten of coatrol ines in the microprocessor.

ressimE ERce m e s m he o ocessor decide the nmn
of read operzOn (RD) ma s atved h s sed o
resshe add E k ouut eatic a
of the memor b case of
emm etha
R I Sma s xtved to múce he e operation.
ines egalane e actv he us The CPU sends
o
o i bus tmable the ouputs of addressed nmr

c mmcate her w nemar a 10

tTgrocessr
es ronds comoi s
hen S nas. e address n e a ir 10 devices
10

àati and address bas anre mutpiezed

T
bes
E de iroupieig af address and àata

23
o asaress and cata b s
C111 D e t p i e x g
Fg

(ALEsi ie
e ts Address Lsteh Enabie
xi

Susias
Engneeing
Garie or
 andLogleDesign I1.7
Ngd ElmomÁs and lege vvmksa
Dsan 11-6
ComputerIntrAroductchiteloctnureto
Dunng the first
phase ot machine cyele,
ComputerInirAroducchittelcson 11.31 Microprocessor Based
mulipleva Jare
address and data bus and the address is Systems Basic Operation
latehes the aidress AL E
sent byymiroprwessor signal is pt on
In the
remaining part of the
utput of the lateh remains machine cycle, inc
at

yc ALE signnl
the
output af the actatch.
ivated principle
unehanged. na his timeis multiple- This a eh e
the two components of:a microprocessor based
address and data bus is
Q.12 What is the
used as a data bus. During this
need of bus drivers
ime disslableded so microprocessor based
Ans: Bus
drivers, buffers are used to
the miervprocessor buses. inerease the
exed multiplexed ApsiA microp

rdWare a
software. The
GSOT

fware
based system
hardware
two has
is the principle components
Q.13 What
drivino e i c e s ,a n dt h e
is the
collection of and circuitry
physical
is DMA and DMA to
the hardware get the desired
p e r a l e st h eh a r
programs which controls
Ans.: To
increase the speed of
controller? output. and
the hardware data transfer lectronic components
used in the
Direct Memory controlled VO
Access (DMA). The
is used. It is between mem.
mory and VO,
whole, are refered to as hardware. microprocessor
based system, as
ransfer is commonly refa
commonly known as DMA hardware which controle nd loo 1 7Draw and explain the block
diagram of simple
Q.14
Explain the function
controller. controls his dat haSed system.
microprocessor
Ans. The
DMA
of DMA controller. ata ia
ADs. Fig. O.17.1 shows the block
to
initiate data controller sends a HOLD YStem. The major diagram of a simple
microprocessor
sends HLDA transfer. In response to signal to the the microprocessor components of microprocessor
based

signal HOLD micron. ocessing Unit (CPU), memory based are Central
and control as an
buses to the DMAacknowledgement signal,
and release micron.
and input and output
cireuitry or 10
ports
Then the data controller. essor These components
withour the transfer is controlled at high
of
microprocessor based are connected using three
intervention of the
controller sends speed by the ces parallel lines called buses. The three buses
of
low on microprocessor.
address and control the HOLD pin, which After data transfer,
DMA Cont
ontDM
roller
data bus and control bus. are address bus,

ransfer is buses back to the gives the DMA

used for large data control
Q.15 What is
an
transfers. microprocessor. This tvpe afof da
data,
Data bus

Ans.: The interrupt driven I/0? data

intermapting theinterrupt driven
execution of
10
approach, provides
provide this the normal the Input
Request). When
facility, there is control sequence of the facility of device

some reason, peripheral wants

a input called INTRprogram, To Control
Microprocessor
Control
it sends logic 1 to interrupt the (Interruntpt ports (CPU)
microprocessor
out
logic 0 on completes execution
on NTR
of the
conurol microprocessor
line. In for Output
DUs Dus

the current
acknowledging (INTA) (Interrupt instruction andresponse. device Memory
interrupt by
the
request of the Acknowledge), output control sends
interrupting
routine. This transíering the
program
device. It then line,
completion of intermupt
it was
service routine
the task, it
interrupted.
control
performs
to
the
an
services
interrupt
the
service
Address bus

retums control to desire task and Fig. Q.17.1 Block diagram of microprocessor based system
the main after
program at the point Central Processing
Unit ( CPU): Central Processing Unit is a
OECODE and is often referred as Microprocessor
microprocessor
Unit (MPU). Its

A Guide A Guide for Engineering Students

for
Engineering Students OECODD
 Electronics
and Logic
lDesign
I1-8
ComputerIntArchitecture
roduction to Electronics andLoglc Design
p y aE
l lectron

11-9 Introduction to
Diginel
coded
instruchons from
memory, decode the Computer Architecture
is to fetch
binary is program ?
ntrol signals
required to execute
control What
purpose the a10
and generate
letched
instnuctions
contains an hmetic Logic
Anth
Unit Program is a series of
the instructions.
The CPU
subtract, OR,
AND, ID, invert and
exchusiveU) (ALUu s.
.
instructions that can be
operations on binary words.
perfom add,
The CPU also contains a program cou erform
a pecified task. executed in order to
which can
perlornm
- OR

p COnsider a
ot the next
xt inct us Co
simple task to
which is used to
hold the
address
instruction nter
Let

of understand the
register
memory, general
purpose registers wh or
which are usedata
omponents a
microprocessor. The task functioning of the
to be fetched from involves following three
for temporary storage of binary
data, and circuitry which which generates used
the operations

1. Read a value from

control signals keyboard connected a
to the port
Input/ Output Module : Input'Output system consists of
a
01H at address
mmunicatm
devices for communicating with
the external worl
consists variety
of inp
of It . Add 30H to the value read
and control
from keyboard.
devices, output devices circuitry.
read datacrinnut
Each
control
has input port
a
3, Send the result to a
address.Microprocessor from input device
can
device like unique display connected to the port
readerskeyboard,
eyboard,
card readers and paper tape
at address 02H.
analog digital
to converter,
Table Q.18.I shows a
program to
used send data to
output evicesthrough accomplish the given task.
the input port. Output ports are to It consists
three instructions. of
as printer, video display, digital analog to converter, plotter such
punches. Physically the port i5 often just a set of
parallel D . card Memory Address
which
usually act as a bufer for input and as a latch for lops Contents (binary) Contents Operation
output
Memory Module The memory module is used to
: (Hex)
codes for the sequences of instructions we want the
store the 0 0 0 0 H1 1001 1001 1 DB Input from
carry out. This sequence of instructions or microprocessa to 00 0
1 H0 00 0 0 0 0 1 port 01H
numbers in successive memory locations.
program is stored as binary 01
It is also
used 0 0 2 H1 10 001
0
0 C6
binary coded data. to store th
the 0 0 0 3 H0 0
Add
1 0 0 0 0 30H immediate
Typically, memory is implemented with data 30h
Memory) and RAM ICs. RAM and ROM both, ROM (Read Onl
of registers, in which memories consist of
each register has an arra
ROM It is a read
unique address. 000 4 H 10 1 0 01 1 D3 Output to port|
only memory. We can't 0 00 5H0 0 0 0 0 0 1 0 02 02H
It is a non
volatile memory i.e. it can hold write data in this memory.
off. Generally, ROM is used to store data even if
of instructions the binary codes power is turned Table Q.18.1 Memory addresses and memory contents for a three
you want the for the instruction program
as
lookup tables. This is because microprocessor
to sequence
cary out and data such
his We assume that the microprocessor fetches instructions and data from
change rype of information does not memory 1 byte at a time.
RAM : Unlike
offen
ROM, we can
read from or Q.19 What is opcode ?
called read write into the
are to be
write memory. The numerical RAM, so it is Ans. An opcode (operation-code) is the first byte of an instruction in
processed by the and character data
must be
stored microprocessor change that machine language which tells the hardware what operation needs to be
memory firom which frequently.
in
type of These data
microprocessor, modified through they
can be
read
performed with this instruction. Every microprocessor has its own set of
storage. For this by the
they are storedprocessing,
opcodes (operational codes) defined in its architecture.
reason, and wTitten
in RANM back Tor
instead of ROM.
OECODE
A Guide for
Engineering Students OECODE A Guide for Engineering Students
 1-70

11.4 Microprocessor Operation

CeputerIerArchi
odacttieoctnus,te enics end Logic Design
11-11
20 hat
ComputerIntroduction
Architectureto
is sa
instrection cycle? ALU

AA
primary functhon efa maroprocessor 1s to execute
sevral registers
o
stratos sored &
memory. which is extem te sequen Control unit
rocess The sequenc ot operatuons ence
ction comsttutes a mtucbon cycle.
imvolved in to the
nal data bus is used
21 ritt a nete ot
instrectioa cycle.
processi
cessing an dvnces.
to transmit data between
these logic
A The coepiete mstructiom
decede ssé esecution cycle involves thr
three operations Fe
Fetch Data bus
Fetch
acoprocessor sends the address of the Instruction
Temp
Macoprocessor also scnds memory Tead ruction to the meme register Generai

signal to mory
purpose
mory contro
rol regsters
Macroprocessor reats insruction byte
enable Instruction
a a bas (opcode)
places 1 in the Instructio sent from ALU
Cecoder

mToprocsor Register (TR) in the

Address bus
when ttech
cycie
instruction Setch cyce. Onused
is
1o read instruction it
the other hand, wi is known Conro
sed to te2d when the fetch
oyerd t krown 25 Status unit Cortro
Decide uperand fetch cycle. cycle is regster

cproewr
mstruu
ieis te opÓE oi the
s decTmine which instruction stored in he Fig. Q.22.1 Simplified block diagram of
microprocessor
a
operation is to be Q23 Write a note on ALU.
ISPPU: June-22, Marks 6
Mrouun
es elrs te
speciied operation. This
Ans.One of the microprocessor s major logie devices is
logic unit (ALC) It contains the microprocessors data processing logc. It
the anithmetic

tz 1evut rlmitg z aihnec ofen

in the
iroiraticn rzison logycal opaTalion and storing ras two inputs and an outpu.
The intemal data bus of microprocessor is comrected to the wo inputs
11.5 Elock of ALU trough the ternporary regstaT and the accumulator.
Diagram of
with its
Functional Microprocessor
Units
The ALU's single cutput is connected to the intemal data bus so that
Can be sent to any device connected to the bus. in most of the
72
ra the bnk
diagyaro sf
TmicroprucessoTs register A gives data for the ALU and after perfoming
daa word 1s sent to tbe register A and stored
mieruprocesor. he te
operaion,
thete. This
resultin
special regster, where the resul: 15 accumulated is commonly
AB 92.1 V
SPPU; June-22, Marks
herws n y starus te simpsfsed blosk
knon 25 accumulator.
As
9221 in.des tare diagyan of 6) either one or wo data words, depending on the

majr gje device.microprocessn The ALU works on

Tie ALU Lses nput ports necessary. For example,

as
kind of operation.
uses both ALU Inputs while complementing data
addition operaticn
A uide for
Engineerin Students A Guide for Engineering Students
DECODE
 ComputerIntroduction
Architectureto
-12 Logic Design 11-13
ea aes st n Tt
CemputerTntArchitetn.
roductlon to is and

wd tha are
op art
ompiement the data wond nstructions tell the
microprocessor
t to legK , and all important that thes
exactly how to solve a
Taie
the e bit ii
f s instructions must be
smc of te funtns of der to get the corTect result. This executed in a
perfiomed
ed the sequence of instruction
by the
by
ALU n.Onitofed by the progam counter.It
monitored

AND
in
most is s being used and what the next instructionkeeps track of which
will be.
OR untet gives the address of
F r O g r tc o u n t e r

memory location from where

p r o g r a m

SRet
inCremeat Exclusive OR next
instruction
is to be fetched.
decides the
Due to this
the length of
counter maximum program the
2
abile Q231
Last the basic Functions pertormed by ALU
Decrement microprocessor that has 16 bit
program
length in bytes. For
registers of
T A m p l e ,

counter, can address

A
asc microprocessor. Es(64 K) of memory
regn frad n mos of the 7 W is status register
What ? Explain its use.
microprocessors are The status register is used to store the
results of certain
encertain operations:are performed during execution of the condition
The starus register is also referred to as
program.
nd certain register flag register. ALU
operations may set or reset one
or more
operations
stanus register. bits in the
Stanus bits lead to a new set of
instructions permit the execution of
microprocessor
a
instructions. These
hasis of the condition of bits in the proram to
change flow on the
Sack Pomter (SP status register. So the condition bits
in the starus
25 What s register can be used to take logical decisions within the
Aas The accumulator ? Evplain its
program.

Most of te cnultor is the function. .28 List the common status

tme t is major register bits and
explain
henever the used to hold work1ng regster of significance. their
the data for
ecy. the processes two words,manipulation.microprocessor.
operatnon Ans.:
Carry/Borrow : The carry bit is set when the surmmation of two
ye preseataccumulator whether Sbit numbers is
in
nother containsor one of the words. arithmetically or greater than 1111 1111 FFH). A borow is
when a large number is generated
Most of the register in The subtracted from a smaller number.
paced in the times tte result of an a memory location. other word Zero: The zero bit is set when the contents
of register are zero after
ongnal contenrsaccumulator. In such arithmetic or any operation. This happens not only when you decrement the
of
accumulator cases, after logical register,
accumulator is also used are lost because execution ofoperation
but also when
Toe is any arithmetie or logical operation causes the contents of
register to be zero.
a
they
memorylocanion, or between for data transfer between instruction
are
a.26 Wha
is one
overwTItten. Negative or Sign : In 2's complement arithmetic, the most
significant
Ans. The program counter ?
memory location andan 1O port and
bit is a sign bit. If this bit is logie 1, the number is
negative number,
Counter is one Explain its function. another.
otherwise a positive number. The negative bit or sign bit is set when
microprocessor.ProgramA program of the most
any arithmetie or logical operation gives a negative result.

is a
ecoD series important Auxiliary Carry : The auviliary curny' bt of status register is set when
of
instructions registers
stored in ne
the
in an addition in the first bits causes a cary into the fifth bit. This is

A
Guide for
Engineering Students OECOD
A Guide for Engineering Students
 cs and Logk Design I1-15
-1 ComputeIntroduction
r Architectureto
hen refemed
haf cRo intermedhate
a CommputermerArcht
educteloctnurto t is
stack pointer ?
ACD anthmetc cay
This is FO (last in, first
stackis
a

Orerflen Fleg In used The out) data

o
compiement hmetic,
in
the ,

AMarea and is used to stote addresses structure

R A M

implemented
most
represent sgn and remaning bits signif holds the address of the top location and data. The
magnitadc of aamber used ificant bi is of the stack Sack
register

are
This ag 5 set if the to
ter
persbon toc large te fit result ot a what is instruction decoder?
Sbt mumer) 1e
represent it
in the number of bits available a signe
ble
Tepresent
(7-bits fot
For
example. It decodes the opcode from instruction
decamai)
if
vou add the S-bit signed oded output. This decoded is
register
output
and generates
the
and the S-bi
signed number used by control
resut will e 10101100( 172 10 (5401110 0 (+118
number 00110110 n t r o lsignals. logic to generate
decimal),
result but in thus case it 1s too
magnitude n an S-bit signed number.
which is
large to fit in the the
1-bits
decimal).
The
ct binary
What is the function
g34 What of control
logie ?
ths The
operation to ndicate that the result overfloOw flag will allowed for The control logic is a important block in the
nto the of the the ADs

sign bit addition has beoverflowe

dition has setet after contro
logic is responsible for working of microprocessor. The
all other
Parity: When the result of an wed microprocesor together. parts of the
with an even number operation leave the
of Is, maintains the synchronization in operation of ditferent
29 What are parnty bit is set.
general purpose registers ?
mdicated register
indicated in the
microprocessor. The synchronization is achueved with the partsof one
Ans. In the control logic's major external inputs, help of
addition to the basic microprocessor's clock. The
registers called general reg1sters, most clock is a signal which is the basis of all the
purpose registers. microprocessors have oth. microprocessor.
timings inside the
The general
purpose ther
these are used to storeTegisters are used as Simple The control logic receives the signal from instruction decoder and
operand from the intemediate results of the storage
area, mainly generates the control signals necessary to execute the instruction.
memory so is general operation. Getting
purpose registers is more the
Tegister in the better have sufficient number of faster than from
to The control logic does a few other special functions. It looks after the

30 What is microprocessor.
microprocessor power-up sequence. It also processes inteTupts
general purpose
memory address Q.35 What is subroutine ? Explain the use of stack and stack
Ans. The register ?
pointer in the execution of subroutine program.
memory address
microprocessoOT wantsregister
hat the
gives the address Ans.: The instructions must be executed in a proper order to get the
holds 16-bit to use.
That is, of memory location
binary
drives the 16-bit number. The memory address
corect result. This does not mean that every instruction must follow the
address bus. Thisoutput of the memory address register last instruction in the memory. But it must
follow the logical sequence of
location output is used to register the instructions.
select a part of a program that is not
in
Q.31 What is memory In some situations, it is better to execute

instruction register? sequence (don't confuse with logical sequence) wth the
main program.

Ans.: The that must be repeated

instruction register holds
instruction the For example, there may
be a part ot a program
Rather than
the of the enure program.

Tegister is loadedmicroprocessor is curentlyoperation code (opcode) of the

execution
many times
dunng the and again, the programmer
ol the program again
durirng the opcode fetch executing. The instruction writing repeated part witien separately. The part
of
instruction Tegister are write that part only
once. ihis is
part
as the used to drive cycle. The contents of the can
written separately is called
subroutine.

instruction decoder. the part of

the control the program
which is

and subroutine programs

are executed.

logic known Fig, Q.35.1 shows how the

main

Students
CECODE A Guidefor Engineering
ORCODE
Digital Electromia and Logic Design i1-16

Man program Subroutine program

ComputeIrntrArchi
oducttleoctnuoto ronicsand Logic Design I1-17 Introduction to
Computer Architecture
allows the programmer to
build the stack
This
the Fig Q.35.2. down in
Subroutine CAL Part of the in memory as

program to be s import ote that as you go on

storing
repeated the stack pointer always points the last data(pushing) data on the
Return to you try
to
when remove (pop) data placed on the stack
nd you always get the
instruction after on the
stack. This kind of stack last
operation is called LIFO data
Subroutne CAL placedon
subroutine call First Out) operation. (Last
Fig. Q.35.1 Execution of subroutine
The program counter does programs 11.6: ALU using IC 74181
the major role in
Baslc
can be loaded
with required memory address. broutine
subroutine execution
eve
Arithmetic Operations
With the belp of instruction as i
it is O36 List the featurs of IC 74181-ALU.
n the possible toloa any
program counter. When subroutine is to
counter is loaded with the be memory executed, address Aa5.: Features of IC 74181-ALU are
subroutine. memory address of the first the
instructio
program Provides 16 arithmetic operations :add, subtract,
After execution of the welve other arithmetic operations. compare, double, plus
the memory subroutine, the program counter is loaded
address of the next
instruction from
Provides all 16
logic operations of two variables exclusive-OR,
control was transferred to
the where ded wit compare, AND, NAND, OR, NOR, plus ten other
subroutine the n logic operations.
During subroutine operation, before program. gram Full lookahead for high speed arithmetic
operation on long words.
the subroutine the
retum address 1s transferring the program controlto
the stack kept in a special program Q.37 Draw the block diagram and connection
diagram for IC 74181.
memory area called Ans.: Fig. Q.37.1 and Fig. Q.37.2 show the block
After the execution of diagram and
returm address is subroutine the connection diagram for IC74LS181.
stack and loadedpopped off from the 27FB
into the E
counter program -SP AgA
The memory 27FC CneCary output
address of the stack D
By-B ALU
area is
given by
A= B Equalityoutput
called the stack special register
a G Generate output

Like the
pointer. 27FD C Cn P propogate output

Pointer Program Counter, the Stack

Carry
input M
next automatically points
available location to the
27FE B
Select Mode
in the Inputs control
memory. In most
27FF
the stack
pointer microprocessors,
decrements
A
Fig. Q.37.1 Block diagram
to the
next lower (points
when data is memory address)
pushed on the stack.
Fig. Q.35.2 Stack
OECOD operation
A Guide for Enginezring Students
Guide fau T PICOD
 Digital Electronics and Logic
Design 11-18
ronics and Logic Desigm Introduction o
ComputerIntrAroductchiteioctnureto I1-19
Computer Architecture
24-Vcc a 9Give
ve the function table for IC 74181
ALU.
23
22 A
21
20
A
Mode Select Inputs Active HIGH
74LS181 19FA Operaads and F, Outpats
M8
Fo 9 Logie Arithmetic (Note 2)
F,- 0 5-
Fa 12
GND 14FA=B SS,5, (M 1) (M 0) (C-1
13- 0
00 0 F A F A
Fig. Q.37.2 Connection
diagram 0 01 F AB F A+B
a.38 Give the
pin description for IC 74181
Ans. ALU. 0 0 0F AB F A+B
1 F Logic 0 F minus
Pin Names
0 0 F AB F A plus AB
A A Description
Operand Inputs 0 FB F (A+B) plus AB
Bo B
Operand Inputs 0 F - A DB F A minus B minus
So S3 Function Select Inputs
M 0 F AB F AB minus 1
Mode Control lnput FA plus AB
0 0 0 F A +B
Carry Input (Active LOW) A plus B
0 0 F A B F
Function Outputs F (A+ B) plus AB
A B 0F B
Comparator Output F AB minus
0 F AB
Carry Generate Output F A plus A (Note 1)
P
I 0 0 F Logie
Camy Propagate Output F (A+ B) plus A
0 F AB
Carry Output (Active LOW) F (A+B) plus A
Table Q.38.1 Pin 0F A B
description of IC 74LS181 I IF A
F A minus
74LS181
Function table for IC
Table Q.39.1
two 74LS181
ICS.
ALU circuit usiug
bit ICs
O40
Design 8 connection of two
74LS181
cascaded
shOWS the
And
Fig Q.40.1
Srudens
Engtneering
A Guide for
orcODS
4 Guide for 4cODa
Engineeriag Student
 Cs and LoB
E e c i r o n c Sa n dL l

Digiral Electronies and Logic Design I1-20

ComputerIntArchitecture
roduction to
MSD of MSD of LSD of
LSD of
operand 1 operand 2 operand operand 2

Ag An Ay Ap AAz Ay A B, B B, B
74LS181 74LS181
ALU) M M (ALU,)
PGFF F, Fo SoS PG
FFa F Fo
TTTTT SorS3
Mode
control

Select lineS

Fig. Q.40.1 8-bit ALU using two 74LS181

ICs
As shown in the
Fig. Q.40.1 mode and select
connected in parallei so that inputs for both ICs are
same function. For
they operate in same mode and
ALU, cary out perform the
the ALU,, i.e. is connected to
,

C, (Cu)
output of ALU,
cary of one stage is
the
propagated to next stage. Theinput
gives final carry.C
of
n -
4
Q.41 Show how
the circuit
for following operations. designed in the
previous example works
1. A B 2. A + B 3. A
and B =
44. XOR B 4. A AND B
Assume : A =
56
Ans.: A = 561 0011 1000, and B 4510 =
=
0010 1100,
Substraction
0 0 1
o 1 10 o B Addition
1
10 10 0 1 ********"******T*****************"***
1 1 1
1
1's comploment of B Carry
1 10 1 Add 1 0: *****....
01
11 0 0 0 A
1 0 1 0 0 2s complement of B 0 0:1: 01 1
0 0 B
****
01 1o 0 1 00
1 1 1 ***- ******..
*******
Result
:0 0 1 Carry
11 0
lgnore 1 10 10 1 0 0 A

0 O0 91 0 0 7s
complement of B
10 0i Result

OIcODL A Gulde for Engineering

Students

A Guide for
Engineering Students OrCOD
 XOR oporation AND operation

1 1 0 0 o A
o 0 1
AND
XOR
00 10 1 1 0 0 B o 10 1 1 0 B
01 0 0 Resut 00 1 0 1 00 0 Resuit
0 0 0 1

Most Significant ALU Least Significant ALU

(ALU,) (ALU)
Mode
Select inputs
Output
Control

Operation Inputs Output Inputs Output

A B S B S Binary
M
S,S5,
1000 1J00 0100 0001 0100
0011 0010 0001
3. A XOR B

1100 0010 1000

4. A AND B I0I 0011 0010 0010 1000

o9

E
 gal
Elecnonlcsan. Logic Desigm 11-25 Introductlonto
Computer Architecture
Digial Elamomix end Legi* Desisa ComyputerInroduction
Architectureto 4-bit multiplier andmultiplicand
3 Steps 1 and are repested n ames to get the desired result nnsider

result in the 1 1 01 and

and Q registers a Multiplicand Multiplier -|01
A flowchart for mulip!ication operation is showm in Fig. Q422 F i e Q 4 2 . 3
shows operations involved and their results in the
mul)
tiplication process.

Start
B

C.A0
1101
Initial Values
S Multiplicand A
QMutiplier
Count n 1011
0
1 1 0 1 101 1 Add First cycle
Shift
0 011 0 11 0
No Yes 1 00 1 1 110 1 Add Second cycle
11 1 0 Shift
Q12 100 1
0 10 0 1 11 10 No Ado Third cycle
11 1
Shit
C.A A+B 0100
0 0 0 1 1 1 1 1 Add Fourth cycie
111 1 Shit
10 0 0

Finai Product

Shift right C,
A and Q Q.42.3 Multiplication
process
Fig.
Count Count 1
11.8:Memory Organization

address ?
Q.43 What is memory
memory is
No Each register in the
Ans. Memories are
made up of register: 1denutied by an address
called
Count=07? storage
location. Each
location is

one
memory address.

unit.
diagram of
memory
Yes the block
unit. The n data
Q.44 Explain block diagram memory of
shows the the k address
Stop Ans.: Fig. Q44.1
to be stored in memory
and
intormation
available. The
the the many
provide word chosen among
Fig. Q.42.2 Flowchart for lines
the particilar direction transfer.
multiplication operation lines specify and wnte) specify the
Let us see one control input
RW(read

example.
Students
A Guide for Engineering

OrcOD (OECODa

A Guide
for Engineering Studens
 11 - 27
Introduction to
ctronics and Logic Design
I1-26 Introduction
Computer Architectureto Dgltul
Computer Architecture
Digiral Electronics and Logic Design
4-Bit Data inputs

Bi-directiona
Data lines
Memory Input
buffers
Address 2
lines n-bit words
Memory Location0

RW Memory Location 1 MW
Read/Write Memory LOcation 2
control
4:16
Decoder
MR
CS
(Chip Select) A Memory Location 14
Memory Location 15 AND2 AND1

of memory unit
Fig. Q.44.1 Block diagram
Output ChipSelect
bufrers (CS)
.When R/W signal is HIGH, read operation is activated and data bus will

act as input for memory.

Read (RD)
Wnte (WR)
is LOW, write operation is activated and data bus
.When R/W signal 4-Bit Data outputS

will act as output for memory.

chip
of 16 x4 memory
select (CS) is used to
or Chip Enable (CE) organization
Another control signal, chip Fig. Q.45.1
internal

The CS input selects

enable the memory chip for read/write operation. time.
cycle
the specified memory chip in a multichip memory system. time and memory
Define access
by the memory
Q.46 required
16 x 4 memory chip. amount of time
Q.45 Explain the internal organization of Access time
refers to the
location.
Ans. addressed
time
between
4 memory the
shows the intermal organization of 16 the data at
x minimum
the
Ans. Fig. Q.45.l to r e t r i e v e time,
refers to

shown with detail connections of address cycle

chip. Here, the organization is Ts
h ue
memory
ccessive memory operations.
read o p e r a t i o n .
lines, data lines and control lines. memory

to perform
steps
Give the
are
address lines and operation
16 decoder is used to decode the contents on Q.47 read bus.
The 4 : memory
on the address

locations. to perforn1 to be
read
select one of the sixteen possible memory Ans. Steps location
bus.
address
of the the controi
on
the signal
T w o AND gates circuitry controlled by (RD) (WR) ,
and (CS)control 1. Place

the
memory
read
control

(RD) and
Note that, here Activate bus. read cycle.
Signals Is used to active read write operation. the d a t a
2. terminate the
from to
the data control signal
cycle.
(WR) are the two separate signals. 3.
Read
memory
read
for memory
read
the diagram
to be De-activate
the timing
to the operation
Input and output buffers are enabled according 4.
Draw
and explain diagram for read
cycle.
enabled and for memory timing
performed. For nmemory Write input buffers
Q.48 the
are shows
Q.48.l
read output butfers are enabled. Fig.
Ans.:
Students
Engineering
Guide for
 Introductionto
11-29 Computer Architecture
and Logic Design
ComputerIntroduction
Electronics
n to al
Digital Electronies and Logic Design 1- 28
Architecture from Read: It is the maximum time delay
.Output tri-state
1 'OTD (RD) goes HIGH (end of read pulse) and the output bufers
-Rc- after
impedance state.
to high
Valid address going It is the minimum time
for which the valid
Address Time :
Data Hold the address ends.
A OHA available on the data output after
Chip Select (CS)
data is memory write
operation.
the steps to perform
a49 Give follows:
-fco- oHA Write operation are as
RD to perform memory address bus.
Read (RD) Steps written on the
Ans. location to be
the address of the
1. Place written on the
data bus.
RDX lOTO- be
the data to bus.
2. Place signal on the control
write control
Data output Valid data
X 3. Activate the memory
write control signal to terminate the write

Logic
1 -lcx De-activate the memory
Wnte (WR) 1 4.
write cycle.
cycle. for memory
the timing diagram
and explain
Q.50 Draw
Fig. Q.48.1 Read cycle timing waveform shows the
wite cycle for memory.
Ans. Fig. Q.50.1
The timing diagram is drawn on the basis of different timing
parameters. These are as follows:
1. tpc : Read Cycle Time : It is the minimum time for which an address Address AW
must be held stable on the address bus, in read cycle.
2. t Address Access Time : It is the maximum Chip Select (CS)
specified time within
which a valid new data is available on the data bus after an address is
applied Write (WR)
3.
tRD Read Output Valid Time: It is the maximum time delay
to
after (RD) goes LOW (beginning of read Data valid
pulse) and the availability of
valid data on the data bus.
Using this timing paraneter we can specity Data input
the maximum rate at which data can be read.
Logic 1
4
RDX Read to Output Active Time: lt is the minimum time delay Read (RD)1
timing
waveform

after (RD) goes LOW (beginning of read Write cycle

pulse) and the output bufters Q.50.1
basis
different
of diffe timing
coming to active state. Fig.
drawn
on
the
is
5.
co:Chip Select :
diagram

to Output Valid Time: It follows

time for which an

is the maximum time hming are
as
minimum
delay after (CS) goes LOW (beginning of chip select pulse) and ue T
The These
is the
parameiers.
Time:
hus
bus, in wnte cycle. Using
the address
address
Cycle
availability of valid data on the data bus. Write held
stable
on

the maximum rate at which data

can specily
be
I. wc cs
6. nust
we
we

tcx Chip Select to Output Active Time: It

is the minimum ac
address

timing
p . i r a m e t e r

after (CS) goes LOW

buffers coming
(beginning of chip select pulse) and the ouput this
c a n b e s t o r e d .

to active state. 4 Gulde for Engineering Students

b E c O D E
Digital Electronics and Logic Design il - 30
roduction to
ComputerIntArchitecture
2. : Address Valid to End of Write :
tAW It iss the time
time at
address must be applied on the address bus before WR
goes hich
which
3. : It is the time high.
twR Write Recovery Time
address
for which addres
remain on
address bus after WR goes high. will
4. tAS Address Setup Time : When address is applied, it isis the
after which WR can be made low. time
5. :
tcw Chip Selection to the End of Write : It is the time at
the CS must be made low to select the device before
WR goes hiwhich
6. w Write Pulse Width : It is
the time for which WR
goes low
7.
tnw: Data Valid to the End of Write : It is the minimum
which data must be valid on the data bus before WR time ffor
goes high.
8. tn : Data Hold Time : It is the
time for which data must
valid after WR goes high. be held

END...