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01.A Practical Guide To High-Speed PCB Layout (3.13 MB)

This document provides an overview and agenda for a presentation on practical guidelines for high-speed printed circuit board layout. The presentation covers topics like ensuring a good schematic foundation, component placement, power supply bypassing, parasitic effects, ground and power planes, packaging, routing RF signals and shielding, layout checking, and summarizes key points. Emphasis is placed on including thorough information in schematics to guide layout designers and achieving expected circuit performance through careful attention to layout details.

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100% found this document useful (1 vote)
273 views107 pages

01.A Practical Guide To High-Speed PCB Layout (3.13 MB)

This document provides an overview and agenda for a presentation on practical guidelines for high-speed printed circuit board layout. The presentation covers topics like ensuring a good schematic foundation, component placement, power supply bypassing, parasitic effects, ground and power planes, packaging, routing RF signals and shielding, layout checking, and summarizes key points. Emphasis is placed on including thorough information in schematics to guide layout designers and achieving expected circuit performance through careful attention to layout details.

Uploaded by

smtplvikas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 107

www.pcbhwdesign.blogspot.

com

Th W
The World
ld LLeader
d iin Hi
High
h Performance
P f Signal
Si l P Processing
i Solutions
S l ti

A Practical Guide to
High-Speed Printed Circuit
Board Layout
John Ardizzoni Dennis Falls
Analog Devices Avnet Electronics Marketing
www.pcbhwdesign.blogspot.com

Agenda
g

‹ Overview
‹ Schematic
‹ Location, location, location
‹ Trust no one
‹ Power supply bypassing
‹ Parasitics
‹ Ground and power planes
‹ Packaging
‹ RF Signal
g routing
g and shielding
g
‹ Checking the layout
‹ Summary

2
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Overview

‹ PCB layout
y is one of the last steps
p in the design
g process
p and
often one of the most critical
‹ High-speed circuit performance is heavily dependant on
layout
y
‹ A high-performance design can be rendered useless due to a
poor or sloppy layout
‹ Today
Today’ss presentation will help:
z Improve the layout process
z Ensure expected circuit performance is achieved
z Reduce design time
z Lower cost
z Lower stress for you and the PCB designer

3
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Th W
The World
ld LLeader
d iin Hi
High
h Performance
P f Signal
Si l P Processing
i Solutions
S l ti

Schematic
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Schematic

‹ The strength
g of anyy structure (including
( g PCB’s)) is only
y as
good as the foundation on which it built upon!
‹ A good layout starts with a good Schematic!
‹ Schematic flow and content
‹ Include as much information as you can
‹ What should you include?

5
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Items to Include on a Schematic

‹ Notes
‹ Component tolerances and case sizes
‹ Part numbers (internal/external/alternative)
‹ Board stack up
‹ Tests
T t or alignment
li t procedures
d
‹ Power dissipation
‹ Controlled impedance and line matching
‹ Component de de-rating
rating
‹ Thermal requirements
‹ Keep outs
‹ Mechanical considerations
‹ Critical component placement
‹ Warning flags
‹ What ever else y you can think of!

6
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Schematic
+5V C1 Place this cap right at pin 14 to digital ground Put C4 and C7 on
0.1uF
back of board
right under the
R6 power supply pin.
40 MHz 301
U1
S1 Must be right at
40 MHz C4 op amp supply
OSC Out +5V 2.2uF pins
+
Run 40MHz traces on bottom
of the board ensure signal C5
trace is the same length 0.01uF
R4 U2
40 MHz 210
OSC Out - R7
50
R3 R5
R1 562 ADA4860- VOUT
562 C6
1K + 1
VIN 0.01uF

R2 C2 C3
50 C7
+5V SAT SAT
2.2uF
Must be right at
+ op amp supply
FREQUENCY ADJUST -5V pins
1.0 C2=C3, use these 2 capacitors to adjust the -3dB BW

See critical component placement


drawing for location
U3
Linear Regulator
D1 +5 U4
8
1N4148 V Temperature
D ti T
Derating Table
bl +12V ADP667
ITEM REF DES VALUE RATING ACTUAL +5 Sensor
1 R1 1K 62mW 10mW
C8 + + C12 V
2 R2
10uF 10uF
3 R3 Case +5V
Case AD590
4 C1 VOUT
size C9 C11 size
5 C2
6 C3 1210 0.01 0.1uF 1210
7 U1 D2 uF Linear Regulator -5V R8
8 U2 1N4148 1K
-12V
U5 -5V
C13 C16
10uf
+ + 10uF
Case Case size
size 1210
1210 C14 C15
0.1uF 0.1uF
NOTES:
BOARD STACK UP
1.0 All resistors and capacitors are 0603 case size unless noted otherwise.
2.0 All Resistors in ohms unless noted otherwise. Signal 1
3.0 All capacitors in pF unless noted otherwise.
Analog Ground 1
4.0 Run analog traces on Signal 1 layer, run digital traces on Signal 2 layer
Power plane
5.0 Remove ground plane on all layers under the mounting pins of U2 0.062"
Digital Ground
6 0 U1 SOIC
6.0 SOIC-14
14, U2 SOT
SOT-23-6
23 6, U3,
U3 SOIC
SOIC-8
8, U4 SOIC
SOIC-8 8 A l G
Analog Ground d2
Signal 2

7
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Th W
The World
ld LLeader
d iin Hi
High
h Performance
P f Signal
Si l P Processing
i Solutions
S l ti

Location, location, location!


www.pcbhwdesign.blogspot.com

Location,, Location,, Location

‹Just as in real estate location is everything!


‹Input/output and power connections are typically
defined…Everything else is undefined
z Criticalcomponent placement
z Signal routing
z Circuit and component proximity

9
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Th W
The World
ld LLeader
d iin Hi
High
h Performance
P f Signal
Si l P Processing
i Solutions
S l ti

Trust No One
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Trust No One

‹ If y
you’re doing
gyyour own
layout, that’s one thing.
‹ If you’re not ….

11
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Trust No One

‹ If y
you’re doing
gyyour own
layout, that’s one thing.
‹ If you’re not ….
z Don
Don’tt assume the CAD group is
going to read your mind and get
it right!

12
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Trust No One

‹ If y
you’re doing
gyyour own
layout, that’s one thing.
‹ If you’re not ….
z Don
Don’tt assume the CAD group is
going to read your mind and get
it right!
z In the end you’re responsible
for making it work!

13
www.pcbhwdesign.blogspot.com

Trust No One

‹ If y
you’re doing
gyyour own
layout, that’s one thing.
‹ If you’re not ….
z Don
Don’tt assume the CAD group is
going to read your mind and get
it right!
z You’re responsible for making it
work!
‹ When working with the CAD
Group

14
www.pcbhwdesign.blogspot.com

Trust No One

‹ If y
you’re doing
gyyour own
layout, that’s one thing.
‹ If you’re not ….
z Don
Don’tt assume the CAD group is
going to read your mind and get
it right!
z You’re responsible for making it
work!
‹ When working with the CAD
Group
z Make sure you and the designer
are on the same page

15
www.pcbhwdesign.blogspot.com

Trust No One

‹ If y
you’re doing
gyyour own
layout, that’s one thing.
‹ If you’re not ….
z Don
Don’tt assume the CAD group is
going to read your mind and get
it right!
z You’re responsible for making it
work!
‹ When working with the CAD
Group
z Make sure you and the designer
are on the same page
z Brief circuit explanation

16
www.pcbhwdesign.blogspot.com

Trust No One

‹ If y
you’re doing
gyyour own
layout, that’s one thing.
‹ If you’re not ….
z Don
Don’tt assume the CAD group is
going to read your mind and get
it right!
z You’re responsible for making it
work!
‹ When working with the CAD
Group
z Make sure you and the designer
are on the same page
z Brief circuit explanation
z Critical
C iti l componentt placement
l t

17
www.pcbhwdesign.blogspot.com

Trust No One

‹ If you’re doing your own


layout, that’s one thing.
‹ If you’re not ….
z Don’t assume the CAD group is
going to read your mind and get
it right!
z You’re responsible for making it
work!
‹ When working with the CAD
Group
z Make sure you and the designer
are on the same page
z Brief circuit explanation
z Critical component placement
z Input/Output connections

18
www.pcbhwdesign.blogspot.com

Trust No One

‹ If you’re doing your own layout,


th t’ one thi
that’s thing.
‹ If you’re not ….
z Don’t assume the CAD group is
going
g g to read your
y mind and get
g it
right!
z You’re responsible for making it
work!
‹ When working with the CAD
Group
z Make sure you and the designer
are on the same page
z Brief circuit explanation
z Critical component placement
z Input/Output connections
z Board outline drawing and stack up

19
www.pcbhwdesign.blogspot.com

Trust No One

‹ If you’re doing your own layout,


that’s one thing
thing.
‹ If you’re not ….
z Don’t assume the CAD group is
going to read your mind and get it
right!
i ht!
z You’re responsible for making it
work!
‹ When working with the CAD Group
z Make sure you and the designer
are on the same page
z Brief circuit explanation
z Critical component
p placement
p
z Input/Output connections
z Board outline, stack up
z Tell them to call you if they have a
question!

20
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Th W
The World
ld LLeader
d iin Hi
High
h Performance
P f Signal
Si l P Processing
i Solutions
S l ti

Power Supply Bypassing


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Power Supply
pp y Bypassing
yp g

‹ Bypassing
yp g is essential to
high speed circuit
performance

22
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Power Supply
pp y Bypassing
yp g

‹ Bypassing
yp g is essential to
high speed circuit
performance
‹ Capacitors
p right
g at power
p
supply pins

23
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Power Supply
pp y Bypassing
yp g

‹ Bypassing
yp g is essential to
high speed circuit
performance
‹ Capacitors
p right
g at power
p
supply pins
z Capacitors provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges

24
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Power Supply
pp y Bypassing
yp g

‹ Bypassing
yp g is essential to
high speed circuit L1
performance +VS
IC
‹ Capacitors
p right
g at power
p 1µH
supply pins C1
0.1µF
z Capacitors provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges EQUIVALENT DECOUPLED POWER
LINE CIRCUIT RESONATES AT:
‹ Keep trace lengths short
1
f =
2π √ LC

f = 500kHz

25
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Power Supply
pp y Bypassing
yp g

‹ Bypassing
yp g is essential to
high speed circuit
performance
‹ Capacitors
p right
g at power
p
supply pins
z Capacitors provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges
‹ Keep trace lengths short

26
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Power Supply
pp y Bypassing
yp g

‹ Bypassing
yp g is essential to
high speed circuit
performance
‹ Capacitors
p right
g at power
p
supply pins
z Capacitors provide low AC
impedance to ground
z Provide local charge storage
for fast rising/falling edges
‹ Keep trace lengths short
‹ Close to load return
z Helpsminimize transient
currents in the ground plane

27
www.pcbhwdesign.blogspot.com

Power Supply
pp y Bypassing
yp g

‹ Bypassing is essential to
high speed circuit
performance
‹ Capacitors right at power
supply pins
z Capacitors provide low AC
impedance to ground
z Provide local charge g storage
g
for fast rising/falling edges
‹ Keep trace lengths short
‹ Close to load return
z Helpsminimize transient
currents in the ground plane
‹ Values
z Individual circuit performance

28
www.pcbhwdesign.blogspot.com

Power Supply
pp y Bypassing
yp g

‹ Bypassing is essential to
high speed circuit
performance
‹ Capacitors right at power
supply pins
z Capacitors provide low AC
impedance to ground
z Provide local charge storage for
fast rising/falling edges
‹ Keep trace lengths short
‹ Close to load return
z Helps minimize transient currents
in the ground plane
‹ Values
z Individual circuit performance
z Maintains low AC impedance

29
www.pcbhwdesign.blogspot.com

Power Supply
pp y Bypassing
yp g

‹ Bypassing is essential to
high speed circuit
performance
‹ Capacitors right at power
supply pins
z Capacitors provide low AC
impedance to ground
z Provide local charge storage for
fast rising/falling edges
‹ Keep trace lengths short
‹ Close to load return
z Helps minimize transient currents
in the ground plane
‹ Values
V l
z Individual circuit performance
z Maintains low AC impedance
z Multiple
p resonances

30
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Power Supply
pp y Bypassing
yp g

‹ Bypassing is essential to high


speed
d circuit
i it performance
f
‹ Capacitors right at power
supply pins
z Capacitors provide low
impedance AC return
z Provide local charge storage for
fast rising/falling edges
‹ Keep trace lengths short
‹ Close to load return
z Helps minimize transient currents
in the ground plane
‹ Values
V l
z Individual circuit performance
z Maintains low AC impedance
z Multiple resonances
‹ Ferrite beads

31
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Th W
The World
ld LLeader
d iin Hi
High
h Performance
P f Signal
Si l P Processing
i Solutions
S l ti

Parasitics
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Parasitics

‹ Parasite – An organism
g that grows,
g , feeds,, and is sheltered on
or in a different organism while contributing nothing to the
survival of its host.

‹ Parasitics in high-speed PCB’s, can destroy circuit


performance!

33
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Parasitics

‹ PCB parasites take the form of undesired capacitors,


inductors and resistors embedded within the PCB
‹ Parasitics are extremely difficult to remove from a PCB
‹ Prevention is the best method to minimize parasitics

34
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Trace/Pad Capacitance
p

d
A

kA
C=
11.3d

K = relative dielectric constant


A = area in cm2
d = spacing between plates in cm

35
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Trace/Pad Capacitance
p

d Example: Pad of SOIC


A
L = 0.2cm W = 0.063cm
K= 4.7
A = 0.0126cm2
kA
C= d = 0.073cm
11.3d
C = 0.072pF
K = relative dielectric constant
A = area in cm2
d = spacing between plates in cm

36
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Trace/Pad Capacitance
p
Example: Pad of SOIC
L = 0.2cm
0 2cm W = 0
0.063cm
063cm
d K= 4.7
A
A = 0.0126cm2
d = 0.073cm

kA C = 0.072pF
p
C=
11.3d

K = relative dielectric constant Reduce Capacitance


C
A = area in cm2 1) Increase board thickness or layers
d = spacing between plates in cm 2) Reduce trace/pad area
3) Remove ground plane

37
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Approximate
pp Trace Inductance

All dimensions are in mm

38
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Approximate
pp Trace Inductance

All dimensions are in mm

Example
L= 25.4mm
W = .25mm
H = .035mm (1oz copper)
Strip Inductance = 28.8nH
At 10MHz 1 86 Ω a 3
10MH ZL = 1.86 3.6%
6% error
in a 50Ω system
39
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Approximate
pp Trace Inductance

All dimensions are in mm

Example Minimize Inductance


L= 2.54cm =25.4mm
1) Use Ground plane
W = .25mm 2) Keep length short (halving
H = .035mm (1oz copper) the length reduces
inductance by 44%)
Strip Inductance = 28.8nH 3) Doubling width only
At 10MHz 1 86 Ω a 3
10MH ZL = 1.86 3.6%
6% error reduces inductance by
in a 50Ω system 11%
40
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Via Parasitics
Via Inductance Via Capacitance
⎡ ⎛ 44hh ⎞ ⎤ 0.55ε r TD1 pF
L ≈ 2h ⎢ln⎜ ⎟ + 1⎥ nH C≈
D2 − D1
⎣ ⎝ d ⎠ ⎦
D2 = diameter of clearance hole in the
L = inductance of the via, nH ground plane, cm
D1 = diameter
di t off pad d surrounding
di via,i cm
H = length of via, cm T = thickness of printed circuit board, cm
D = diameter of via, cm ε r = relative electric permeability of circuit
board material
C = parasitic via capacitance, pF
Given:
H= 0.157 cm thick board, Given:
D= 0.041 cm T = 0.157cm,
D1=0.071cm
0 071
L ~ 1.2nh D2 = 0.127
C ~ 0.51pf

41
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Via Cross Section

D2

T&H
D1

42
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Capacitor
p Parasitic Model

RP RS L

r
C

RDA CDA

C = Capacitor
RP = insulation resistance
RS = equivalent series resistance (ESR)
L = series inductance of the leads and plates
RDA = dielectric absorption
CDA = dielectric absorption

43
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Resistor Parasitic Model

CP L

R
R = Resistor
CP = Parallel capacitance
L= equivalent series inductance (ESL)

44
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Low Frequency
q y Op
p Amp
p Schematic

45
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High
g Speed
p Op
p Amp
p
Schematic

46
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High
g Speed
p Op
p Amp
p
Schematic

Parasitic Capacitance

47
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http://www.analog.com/en/design-tools/dt-multisim-spice-program-download/design-center/index.html

48
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Stray
y Capacitance
p Simulation Schematic

49
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Frequency
q y Response
p with 2pF
p Stray
y Capacitance
p

1.8dB peaking

1.8dB peaking

50
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Stray
y Inductance

Parasitic Inductance

51
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Parasitic Inductance Simulation Schematic

AD8055 24.5mm x .25mm” =29nH

52
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Pulse Response
p With and Without Ground
Plane

0.6dB overshoot

53
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Transient Response
p AD8009
1GHz Current Feedback Amplifier
RF
402Ω

+5V
10uF
RG
402Ω
0.1uF

0.1uF

150Ω

10 F
10uF
-5V

54
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Small Changes
g Can Make a Big
g Difference!

Circuit A Circuit B

55
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Improper
p p Use of Scope
p Probe Ground Clip
p

56
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Effect of Clip
p Lead Inductance

57
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Proper
p Grounding
g for Scope
p Probe in High-
g
Speed Measurments

58
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Small Changes
g Make Big
g Differences
Circuit A Circuit B

21ns 17ns

25% reduction in ringing duration and amplitude


59
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Th W
The World
ld LLeader
d iin Hi
High
h Performance
P f Signal
Si l P Processing
i Solutions
S l ti

Ground and Power Planes


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Ground and Power Planes Provide

‹A common reference point


p
‹ Shielding
‹ Lower noise
‹ Lower resistance
‹ Lower impedance
‹ Reduces parasitics
‹ Heat sink
‹ Power distribution

61
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Ground Plane

62
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Ground Plane and Trace Routing

Input Connector

Wrong Way

Resistor
Clock Analog Digital
Circuitry Circuitry Circuitry

Sensitive Analog
Circuitry Disrupted by
Digital Supply Noise

ID
IA
INCORRECT
+ +
ANALOG DIGITAL
VD VA
VIN CIRCUITS CIRCUITS

GND IA + ID ID
63 REF
www.pcbhwdesign.blogspot.com

Ground Plane and Trace Routing

Wrong Way

Resistor
Clock Analog Digital
Circuitry Circuitry Circuitry

Sensitive Analog
Circuitry Disrupted by
Digital Supply Noise

ID
IA
INCORRECT
+ +
ANALOG DIGITAL
VD VA
VIN CIRCUITS CIRCUITS

GND IA + ID ID
64 REF
www.pcbhwdesign.blogspot.com

Ground Plane and Trace Routing

Resistor
Analog

Right Way
Circuitry

Digital
Circuitry

Sensitive Analog
Circuitry Safe from Clock
Digital Supply Noise Circuitry

ID

IA CORRECT
+ +
ANALOG DIGITAL
VD VA
VIN CIRCUITS CIRCUITS

GND IA
REF
ID
65
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Ground Plane and Trace Routing

Resistor
Analog

Right Way
Circuitry

Digital
Circuitry

Sensitive Analog
Circuitry Safe from Clock
Digital Supply Noise Circuitry

ID

IA CORRECT
+ +
ANALOG DIGITAL
VD VA
VIN CIRCUITS CIRCUITS

GND IA
REF
ID
66
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Ground Plane and Trace Routing

Grounding Example:

Resistor
Signal
‹ Topp layer
y is solid g ground. Input Termination
Resistor
‹ Bottom has a trace/transmission line
connecting the RF connector to the Top Side
load.
‹ R t
Return currentt fl
flows iin the
th top
t layer
l
ground plane directly above the trace
on the opposite side.

Bottom side

67
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Ground Plane and Trace Routing


AC current
follows the
Grounding Example: DC Current vs. AC path of least
Current: impedance

In a split or broken ground, the return

Resistor
‹
currents follow the path of least
i
impedance
d DC current
follows the
‹ At DC, the current follows the path of path of least
least resistance resistance
‹ As the frequency increases
increases, the
current follows the path of least
inductance
‹ Since there is now a ‘loop’ the
inductance can be quite high and the
circuit can now propagate EMI/RFI

68
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Grounding
g Mixed Signal
g ICs: Single
g PC Board

VA VD

VA VD
ANALOG MIXED DIGITAL
CIRCUITS SIGNAL CIRCUITS
DEVICE
SYSTEM AGND DGND
STAR
GROUND
A A D D

ANALOG DIGITAL
GROUND PLANE GROUND PLANE

A D

ANALOG DIGITAL
SUPPLY SUPPLY

69
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Ground Plane Recommendations


‹ There is no single grounding method which is guaranteed to work
100% of the time!
‹ Remove
R groundd plane
l under
d op amps to t reduce
d parasitic
iti
capacitance
‹ At least one layer on each PC board MUST be dedicated to ground
p
plane!
‹ Provide as much ground plane as possible especially under traces
that operate at high frequency
‹ Use thickest metal as feasible (reduces resistance and provides
improved thermal transfer)
‹ Use multiple vias to connect same ground planes together
‹ Do initial layout with split analog and digital ground planes
‹ Follow recommendations on device data sheet (read datasheet)
‹ Keep bypass capacitors and load returns close to reduce distortion
‹ Connect analog, digital and RF grounds at one point

70
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Si l P Processing
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Packaging and Pinout


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Op
p Amp
p Packaging
g g and Pinout

‹ Packaging
g g plays
p y a large
g role in high-speed
g p applications
pp
Smaller packages
z Betterat higher speeds
z Less parasitics
z Compact layout

‹ Analog Devices Low Distortion Pinout


z Intuitively
makes more sense
z Compact layout
z Streamline signal flow
z Lower distortion

72
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Op
p Amp
p SOIC Packaging
g g
‹ Traditional
SOIC-8 layout
‹ Feedback routed around or underneath amplifier
p

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Op
p Amp
p SOIC Packaging
g g
‹ Traditional
SOIC-8 layout
‹ Feedback routed around or underneath amplifier
p

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Analog
g Devices Low Distortion Pinout

Original Pin-Out
‹ Pinout enables compact
p
layout NC
FB 1 8 Disable
–IN 2 - 7 +VS

+IN 3 + 6 VOUT

–VS 4 5 NC

SOIC

NC 1 8 +VS
FEEDBACK 2 7 OUTPUT
–IN 3 6 NC

14-0-001
+IN 4 5 –VS

0481
LFCSP
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Analog
g Devices Low Distortion Pinout

Original Pin-Out
‹ Pinout enables compact
p
layout FB 1 8 Disable
‹ Lower distortion –IN 2 - 7 +VS

+IN 3 + 6 VOUT

–VS 4 5 NC

SOIC

NC 1 8 +VS
FEEDBACK 2 7 OUTPUT
–IN 3 6 NC

04814-0-001
+IN 4 5 –VS

LFCSP
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Analog
g Devices Low Distortion Pinout

Original Pin-Out
‹ Pinout enables compact
p
layout FB 1 8 Disable
‹ Lower distortion –IN 2 - 7 +VS
‹ Improved thermal +IN 3 + 6 VOUT
performance
–VS 4 5 NC

SOIC

NC 1 8 +VS
FEEDBACK 2 7 OUTPUT
–IN 3 6 NC

04814-0-001
+IN 4 5 –VS

LFCSP
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Analog
g Devices Low Distortion Pinout

Original Pin-Out
‹ Pinout enables compact
p
layout FB 1 8 Disable
‹ Lower distortion –IN 2 - 7 +VS
‹ Improved thermal +IN 3 + 6 VOUT
performance
–VS 4 5 NC
‹ LFCSP
z AD8099,
AD8099AD8045,
AD8045 AD8000
AD8000, SOIC
ADA4899, ADA4857, ADA4817

NC 1 8 +VS
FEEDBACK 2 7 OUTPUT
–IN 3 6 NC

04814-0-001
+IN 4 5 –VS

LFCSP
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Low distortion p
pinout enables compact
p
and streamline layout

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Low distortion p
pinout enable compact
p and
streamline layout

Tantalum

C
RF
R

RG
AD80XX
RT

0 0 RL

Tantalum

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RF Signal Routing and


Shielding
www.pcbhwdesign.blogspot.com

In This Section
‹ RF Components from Analog Devices
‹ PC Board Circuit Material Types
yp and Minimizing
g Losses
‹ Microstrip and Stripline Transmission Lines
‹ Ground Plane Layout Considerations
‹ Developing a RF Printed Circuit Board
‹ Using Discrete Components with RF Devices
‹ Shielding of RF Circuit Boards

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RF Components from Analog Devices

http://www.analog.com/en/rfif-components/products/index.html
p g p p

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Analog Devices Components Requiring Matched


RF Interfaces

‹ AD60x, AD8xxx and ADL533x series of RF/IF and Variable Gain


Amplifiers
‹ ADF70xx and 702x series Radio Transmitters and
Transceivers
‹ AD4xxx and ADF7xxx series of PLL Synthesizers and VCO’s
‹ AD84xx and ADL53xx series of Modulators and Demodulators
‹ AD83xx and ADL539x series of Mixers and Multipliers
‹ AD83xx and ADL5519 series of Log Amps and Detectors
‹ AD836x and ADL550x series of RMS Detectors
‹ ADG9xx
ADG9 seriesi off RF Switches
S it h

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PC Board Circuit Material Type and Minimizing


Losses

‹ PC board material selection is usually based on price verses


performance
‹ Select PC board dielectric material to have the lowest loss tangent
‹ Some types of “FR4”
FR4 dielectric materials are low loss below 8-10
GHz
‹ PTFE(Teflon) dielectric material is usually used for the lowest loss
g
at the higher RF and microwave frequency
q y ranges,
g , but at a much
higher price
‹ Be sure that the correct impedance transmission line is used for the
interconnection of the RF devices
‹ Use as wide of a transmission line as possible for the correct
impedance, and try to keep it short to reduce “Skin Effect” losses
‹ Use high “Q”, or low loss passive components for all RF matching,
coupling and bypassing requirements
coupling,

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Microstrip
p and Stripline
p Transmission Lines

‹ 50 ohm interfaces are most often used between most “integrated”


RF devices
‹ Interconnects less than 1/20 of a wavelength long can usually be
made without a matched transmission line
‹ Avoid longg microstrip
p lines as they
y could become
“antennas”(microstrip) and radiate RF
‹ To minimize coupling to the transmission line, DO NOT place other
traces or ground plane closer than three times of the dielectric
h i ht
height
‹ Use proper technique for making bends in microstrip lines
‹ Locate the microstrip lines on the component side of the board if
possible

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Microstrip
p Transmission Lines
‹Microstrip
Controlled Impedance Line
C
Cross S
Section
ti
‹ Advantages:
‹ Transmission line on outside layer
of board
‹ Easy to attach components to trace
‹ Components can be placed at
different locations along the line to
aid in tuning
‹ Aid in RF testing as you are able to
measure levels along the line

‹ Disadvantages:
g 87 ⎡ 5.98H ⎤
ZO = ln⎢
ε r + 1.41 ⎣(0.8W + T )⎥⎦
‹ Slightly higher loss
‹ Not shielded and could radiate RF
signal

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Stripline Transmission Lines

‹ Stripline
Controlled Impedance Line
Cross Section
‹ Advantages:
‹ Lower loss at higher microwave
frequencies
‹ Shielded transmission line, no RF
radiation from board

‹ Disavantages:
‹ Requires vias to connect to line
‹ No ability to connect tuning or
termination components to line
‹ No access to line to make
adjustments or connections to line 60 ⎡ 1.9(B) ⎤
ZO (Ω) = ln⎢
for RF testing εr ⎣(0.8W + T)⎥⎦
‹ Higher PCB cost

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Microstrip
p and Stripline
p Transmission Lines

‹ Bends in Microstrip and Stripline

‹ In order to preserve a constant


impedance around a bend, some
general layout rules MUST be
followed
‹ DO NOT make a right angle bend as
shown
‹ A right
i ht angle
l bend
b d can be
b maded with
ith
a “swept” bend, or a “Mitered” bend
‹ Bends in a transmission line that are
less than 90 degrees
g can also be
mitered as shown

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Ground Plane Layout


y Considerations

‹ Do NOT have breaks or voids in the RF ground plane under, or over


RF transmission lines
‹ Ground plane Vias around the RF circuits should be spaced closer
than 1/20 of a wavelength as a minimum, or closer if possible at the
higher frequencies
‹ Use as large size vias as practical to minimize inductance
‹ “Stitch” the top and bottom ground planes together with as many
vias as possible
‹ Signal and bias lines can be placed below RF ground plane layer
followed by another “power” ground plane layer for the DC and
digital returns
‹ Under components that require heat sinking,
sinking have solid ground
plane with many closely spaced vias to transfer heat to all ground
plane layers

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Ground Plane Layout


y Considerations

Closely spaced vias under


components requiring heat
sinking Vias placed in ground
plane at each end of
the DC bias bypass
50 ohm microstrip components
transmission line

Proper spacing of ground plane


away from transmission line
(gap= 3 times dielectric height)

Closely spaced Proper layout pattern for


G
Groundd plane
l vias
i connecting edge mounted
along transmission RF connector to PC board
line
“Stitch” ground
Maximum amount of ground plane
planes
l ttogether
th
on top and bottom sides of PC board
with multiple vias

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Developing a RF Printed Circuit Board

‹ Draw Schematic of circuit to be placed on the PC board


‹ Have data sheets on components to indicate pkg size, pinouts, etc
‹ Determine location and orientation of active devices to optimize RF
interfaces
‹ Place RF matching/terminating components around the device to
provide the shortest possible connections
‹ Use as small of mounting pad as possible with discrete RF
components to keep stray capacitance to a minimum
‹ Observe proper orientation of discrete components if placed next to
eachh other
th to
t avoid
id coupling
li effects
ff t
‹ Separate inductors from each other in the layout, or place
perpendicular to each other to prevent coupling of their magnetic
fields
‹ Make sure that components that are connected to the ground plane
have a via(s) as close to the end of the component as possible
‹ Use wide power traces if possible to lower DC losses and provide
higher stray capacitance to ground(will also act as a RF bypass cap)

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Designing a RF Printed Circuit Board


‹ Draw Schematic of circuit

‹ Draw layout of components to optimize parts placement and interconnections

AD8353
ADL5523 AD5350
LNA Mixer IF AMP

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Designing a RF Printed Circuit Board


Ground plane Ground vias at end Place bias line bypassing Matching Large number of vias under devices
Is not close to of RF and bypass components close to RF components placed to provide good RF grounds and
transmission components device close to RF device thermal conductivity
line to reduce
coupling

RF Input

AD5350 AD8353 IF
ADL5523
LNA Mixer IF AMP
Output

LO Input

RF attenuator RF devices placed in a straight Inductors placed at right Short interstage RF Very short ground
placed close to line to aid in overall circuit angles to reduce coupling transmission lines leads from device
board connector stability of their magnetic fields between stages to ground plane

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Shielding
g on RF Circuit Boards
‹ On multilayer circuit boards, use Stripline transmission lines if possible
‹ Route DC bias and signal traces on inner layers between the ground planes
‹ If required,
equ ed, place
p ace shielded
s e ded enclosures
e c osu es a around
ou d tthe e RF stages o
on tthe
e boa
board
d
‹ Be careful as to the physical size of the shielded enclosures, as it could
become a resonate “cavity” at the higher frequencies
‹ Traces going to or from shielded sections should be routed on inner layers
if possible Shield enclosure outlines DC bias line on inner layer

RF Input D C Bias

ADL5523 AD5350 AD8353 IF Output


LNA Mixer IF AMP

L O Input

All board mounting holes should be On multilayer board use stripline


plated through to provide good RF transmission lines to provide
grounds to the external housing shielding

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Checking the Layout


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Checking
g the Layout
y

‹ Design
g review
‹ Colleague review

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Checking
g the Layout
y

‹ Design
g review
‹ Colleague
‹ Colored pencils
z Old School
z Helps trace signal path on
schematic and PCB

98
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Checking
g the Layout
y

‹ Design
g review
‹ Colleague
‹ Colored pencils
z Old School
z Helps trace signal path on
schematic and PCB
‹ Sit with the designer when
board corrections are made
z Trustno one
z A change in one area of the
board could inadvertently
change another part of the
board

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Next Steps
p

‹ Order Boards
‹ Build and test
‹ Evaluate performance
‹ Iterate and try again if required
‹ Successful High Speed/RF PCB design is a combination of
education and experience

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Summary
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Summary
y
‹ High speed PCB design requires deliberate thought and attention to detail!
‹ Load the schematic with as much information as possible
‹ Where you put individual components on the board is just as important as
to where you put entire circuits
‹ Take the lead when laying out your board, don’t leave anything to chance
‹ Use multiple capacitors for power supply bypassing
‹ Parasitics must be considered and dealt with
‹ Ground and Power planes play a key role in reducing noise and parasitics
‹ New packaging and pinout options allow for improved performance and
more compact layouts
‹ There are many options for signal distribution, make sure you choose the
right one for your application
‹ Check
Ch k ththe llayoutt and
d check
h k it again
i
‹ Successful High Speed PCB design is a combination of education and
experience and sometimes a little luck!

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Summary
y
‹ Work directly with PC board designer as they most likely will not
understand proper RF layout techniques
‹ Provide
P id designer
d i with
ith a drawing
d i off the
th location
l ti off the
th critical
iti l high
hi h
frequency components and transmission lines
‹ Instruct the board designer that transmission line widths and
g
lengths are very
y critical and must be exactlyy as calculated
‹ Place the components to minimize the length of RF
interconnections
‹ Generally try to place components in a “straight line” to avoid
feedback loops and instabilities
‹ Place circuit blocks such as oscillators, mixers, amplifiers in
separate sections on the board if possible
‹ Do NOT mix digital,
g , low level analog, g, or bias traces with RF
interconnects to avoid unwanted coupling
‹ Locate the components operating at the highest frequencies close
to board interconnects
‹ With the PC board designer
designer, check
check, and recheck the layout before
sending out for fabrication
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References
‹ Ardizzoni, John “A Practical Guide to High-Speed Printed-Circuit-
Board Layout ”
‹ Ardizzoni, John, “Keep
Keep High
High-Speed
Speed Circuit
Circuit-Board
Board Layout on Track,
Track,”
EE Times, May 23, 2005.
‹ Brokaw, Paul, “An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change,” Analog
Devices Application Note AN-202.
‹ Brokaw, Paul and Jeff Barrow, “Grounding for Low- and High-
Frequency Circuits,” Analog Devices Application Note AN-345.
‹ Buxton, Joe, “Careful Design Tames High-Speed Op Amps,” Analog
Devices Application Note AN-257.
‹ DiSanto, Greg, “Proper PC-Board Layout Improves Dynamic
Range,” EDN, November 11, 2004.
‹ Grant, Doug and Scott Wurcer, “Avoiding Passive-Component
Pitfalls,” Analog Devices Application Note AN-348
‹ Johnson, Howard W., and Martin Graham, High-Speed Digital
Design, a Handbook of Black Magic, Prentice Hall, 1993.
‹ Jung, Walt, ed., Op Amp Applications Handbook, Elsevier-Newnes,
2005 available on Amazon.com
‹ Kester, Walt, The Data Conversion Handbook, Elsevier-Newnes,
2005 available on Amazon.com
104
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References

‹ Hartley,
y Rick, “RF / Microwave PC Board Design
g and Layout”
y
‹ Reed, Dale, RF and Microwave Basics Impact PCB Design
‹ Mercer, Sean, “Minimizing RF PCB Electromagnetic Emissions,” RF
Design, January 1999.
‹ Fabian Kung Wai Lee, “Open notes on High-Speed Printed Circuit
Board (PCB) Design (August 2008) “ Available at
http://persona.mmu.edu.my/~wlkung/ADS/ads.htm”
‹ Howe,
H H
Harlan,
l “St
“Stripline
i li Circuit
Ci it Design”
D i ”
‹ Rogers Corporation, “A Low cost Laminate for Wireless
Applications,” Microwave Journal, Sept 1996
‹ Rogers Corporation,
Corporation “Microwave Impedance Calculator (MWIJ 1
1.0)”
0)”

105
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Contact Information

John Ardizzoni Dennis Falls


Analog Devices, Inc. Avnet Electronics Marketing
804 Woburn Street 9200 Indian Creek Parkway
Wilmington MA 01887-1017
Wilmington, 01887 1017 Suite 600
Overland Park, Kansas 66210
Email:
[email protected] E-mail:
[email protected]

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Thank You

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