Unit-4

Sequential Logic Circuit

Combinational Circuit –

1.In this output depends only upon present input.

2.Speed is fast.
3.It is designed easy.
4.There is no feedback between input and output.
5.This is time independent.
6.Elementary building blocks: Logic gates
7.Used for arithmetic as well as boolean operations.
8.Combinational circuits don’t have capability to store any state.
9.As combinational circuits don’t have clock, they don’t require
triggering.
10. These circuits do not have any memory element.
11. It is easy to use and handle.

Examples – Encoder, Decoder, Multiplexer, De-multiplexer etc

Block Diagram –

Sequential Logic Circuit

The word “Sequential” means that things happen in a “sequence”, one
after another and in Sequential Logic circuits, the actual clock signal
determines when things will happen next.

1. In this output depends upon present as well as past input.

2. Speed is slow.
3. It is designed tough as compared to combinational circuits.
4. There exists a feedback path between input and output.
5. This is time dependent.
6. Elementary building blocks: Flip-flops
7. Mainly used for storing data.
8. Sequential circuits have capability to store any state or to retain
earlier state.
9. As sequential circuits are clock dependent they need triggering.
10. These circuits have memory element.
11. It is not easy to use and handle.

Examples – Flip-flops, Counters and shift registers etc.

Block Diagram –

Differences between combinational and sequential logic circuit

Sr.
Key Combinational Circuit Sequential Circuit
No.
Combinational Circuit is
On other hand Sequential
the type of circuit in
circuit is the type of
which output is
circuit where output not
1 Definition independent of time and
only relies on the current
only relies on the input
input but also depends on
present at that particular
the previous output.
instant.
On other hand in case of
In Combinational circuit Sequential circuit output
as output does not relies on its previous
depend on the time feedback so output of
2 Feedback
instant, no feedback is previous input is being
required for its next transferred as feedback
output generation. used with input for next
output generation.
As the input of current
On other hand Sequential
instant is only required
circuit are comparatively
in case of Combinational
slower and has low
3 Performance circuit, it is faster and
performance as compared
better in performance as
to that of Combinational
compared to that of
circuit.
Sequential circuit.
No implementation of However on other hand
feedback makes the implementation of
combinational circuit feedback makes
4 Complexity
less complex as sequential circuit more
compared to sequential complex as compared to
circuit. combinational circuit.
Elementary building On other hand building
Elementary
5 blocks for combinational blocks for sequential
Blocks
circuit are logic gates. circuit are flip flops..
Combinational circuit On other hand Sequential
6 Operation are mainly used for circuit is mainly used for
arithmetic as well as storing data.
Sr.
Key Combinational Circuit Sequential Circuit
No.
Boolean operations.

Comparison Between Combinational & Sequential Logic

Combinational Logic Sequential Logic

Its output depends only on the current Its output depends on the current as
input well as previous input.

Designed from logic gates as well as

Only consists of digital logic gates
memory units

Its processing speed is fast Its processing speed is slow

Combinational logic designing is Its designing is complex as compared

simple & easy. to combinational logic
It is independent of the clock signal.
It updates the output only when the
Output updates as soon as the input is
clock signal is applied.
changed.

There is no feedback system involved. There is feedback from output to input.

A counter is a simple example of a

Example of combinational logic
sequential circuit as it retains and
circuits are Encoder, multiplexer &
updates its value according to the
adder etc
previous one.

Classification of Sequential Logic Circuit

The sequential circuits may be classified as synchronous sequential

circuits and asynchronous sequential circuit.

The differences between Synchronous and Asynchronous Sequential

Circuits −
Sr. Synchronous Asynchronous Sequential
Key
No. Sequential Circuits Circuits
Synchronous
sequential circuits are
On other hand Asynchronous
digital sequential
sequential circuits are digital
circuits in which the
sequential circuits in which
1 Definition feedback to the input
the feedback to the input for
for next output
next output generation is not
generation is
governed by clock signals.
governed by clock
signals.
In Synchronous
On other hand un-clocked
sequential circuits,
flip flop or time delay is used
Memory the memory unit
2 as memory element in case of
Unit which is being get
Asynchronous sequential
used for governance
circuits.
is clocked flip flop.
On other hand there are
chances for the
The states of
Asynchronous circuits to
Synchronous
enter into a wrong state
3 State sequential circuits are
because of the time
always predictable
difference between the
and thus reliable.
arrivals of inputs. This is
called as race condition.
However on other hand the
presence of feedback among
It is easy to design
logic gates causes instability
4 Complexity Synchronous
issues making the design of
sequential circuits
Asynchronous sequential
circuits difficult.
Due to the
Since there is no clock signal
propagation delay of
delay, these are fast
5 Performance clock signal in
compared to the Synchronous
reaching all elements
Sequential Circuits
of the circuit the
Sr. Synchronous Asynchronous Sequential
Key
No. Sequential Circuits Circuits
Synchronous
sequential circuits are
slower in its
operation speed
On other hand Asynchronous
circuits are used in low
power and high speed
Synchronous circuits
operations such as simple
are used in counters,
6 Example microprocessors, digital
shift registers,
signal processing units and in
memory units.
communication systems for
email applications, internet
access and networking.

FLIP-FLOPS

Flip flop is formed using logic gates, which are in turn made of
transistors. Flip flop are basic building blocks in the memory of
electronic devices. Each flip flop can store one bit of data. Flip – flops
have two stable states and hence they are bistable multivibrators. The
two stable states are High (logic 1) and Low (logic 0).

The term flip – flop is used as they can switch between the states
under the influence of a control signal (clock or enable) i.e. they can
‘flip’ to one state and ‘flop’ back to other state.

 Flip – flops are a binary storage device because they can store
binary data (0 or 1).
 Flip – flops are edge sensitive or edge triggered devices i.e. they
are sensitive to the transition rather than the duration or width
of the clock signal.
 They are also known as signal change sensitive devices which
mean that the change in the level of clock signal will bring
change in output of the flip flop.
  A Flip – flop works depending on clock pulses.
 Flip flops are also used to control the digital circuit’s
functionality. They can change the operation of a digital circuit
depending on the state.

Some of the most common flip – flops are SR Flip – flop (Set –
Reset), D Flip – flop (Data or Delay), JK Flip – flop and T Flip – flop.

Latch: The term Latch is used for certain flip-flops or the simplest
type of flip-flop is called an S-R Latch. It refers to non-clocked flip-
flops, because these flip flops latch on to 1 or a o immediately upon
receiving the input pulse called SET or RESET. A latch may be an
active High input latch or an active low input latch. Using two NOR
gates, an active high S-R latch can be considered and using two
NAND gates an active LOW S-R latch can be considered. The Latch
has two inputs as S and R and two outputs as Q and Q̅.

Latches vs Flip-Flops
Latches and flip – flops are both 1 – bit binary data storage devices.
The main difference between a latch and a flip – flop is the triggering
mechanism. Latches are transparent when enabled ,whereas flip –
flops are dependent on the transition of the clock signal i.e. either
positive edge or negative edge.

The NOR gate S-R Latch(Active high S-R Latch)

Truth Table
S R Qn Qn+1 State
0 0 Last State
0 1 0 1 ( Reset)
1 0 1 0 (Set)
1 1 Invalid

Characteristics Table
S R Qn Qn+1 State

0 0 0 0 No Change (NC)
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 X Indeterminate(Invalid)
1 1 1 X

S-R Latch Using NAND Gate(Active Low Latch)

Truth Table
S R Qn Qn+1 State

0 0 0 X Indeterminate(Invalid )
0 0 1 X
0 1 0 1 Set
0 1 1 1
1 0 0 0 Reset
1 0 1 0
1 1 0 0 No Change or
1 1 1 1 Last State
The operation of the NAND latch is the reverse of the operation of
the NOR gate latch. That is why it is called an active low S-R latch.

Active High latch using NAND gates.

An active low NAND latch can be converted into an active High

NAND Latch by inserting the inverters at the S and R inputs.
Clock Pulse Transition

The movement of a trigger pulse is always from a 0 to 1 and then 1 to

0 of a signal. Thus it takes two transitions in a single signal. When it
moves from 0 to 1 it is called a positive transition and when it moves
from 1 to 0 it is called a negative transition. To understand more take
a look at the images below.

What is Edge Triggering

In a sequential circuit, if the output changes when the signal transits

from a high level to a low level or from a low level to a high level, we
call it edge triggering. Here, the edge that changes the voltage from
low level to the high level is called rising edge (positive edge). And,
the edge that changes the voltage from high level to the low level is
called falling edge (negative edge). Thus, when an event is triggered
at the rising edge or falling edge, we call it edge triggering.

Positive Edge Triggering

When a flip flop is required to respond at a LOW to HIGH transition

state, positive edge triggering method is used. It is mainly identified
from the clock input lead along with a triangle. Take a look at the
symbolic representation shown below.
Negative Edge Triggering

When a flip flop is required to respond during the HIGH to LOW

transition state, a negative edge triggering method is used.. It is
mainly identified from the clock input lead along with a low-state
indicator and a triangle. Take a look at the symbolic representation
shown below.
What is Level Triggering

In the sequential circuit, if the output changes during the high voltage
period or low voltage period, it is called level triggering. In other
words, the output changes during either high voltage or low voltage
period- not during the edges like in edge triggering. Thus, when an
event triggers at the clock level, we call it level triggering. Two types
of level triggering i.e high level triggering and low level triggering.

1. High Level Triggering

When a flip flop is required to respond at its HIGH state, a HIGH

level triggering method is used. It is mainly identified from the
straight lead from the clock input. Take a look at the symbolic
representation shown below.

2.Low Level Triggering

When a flip flop is required to respond at its LOW state, a LOW

level triggering method is used.. It is mainly identified from the clock
input lead along with a low state indicator bubble. Take a look at the
symbolic representation shown below.
S-R Flip-flop

Block diagram of S-R Flip -Flop

Working

SR flip – flop works during the transition of clock pulse either from
low – to – high or from high – to – low (depending on the design) i.e.
it can be either positive edge triggered or negative edge triggered.

For a positive edge triggered SR flip – flop, suppose, if S input is at

high level (logic 1) and R input is at low level (logic 0) during a low –
to – high transition on clock pulse, then the SR flip – flop is said to be
in SET state and the output of the SR flip – flop is SET to 0.
Truth table

Characteristics Table
clk S R Qn Qn+1 State
↑ 0 0 0 0 Last state
↑ 0 0 1 1
↑ 0 1 0 0 Reset
↑ 0 1 1 0
↑ 1 0 0 1 Set
↑ 1 0 1 1
↑ 1 1 0 X Invalid
↑ 1 1 1 X

The characteristic equation :This specifies the value of the next

state as a function of the present state and input.
K.map for Qn+1

R̅Q̅n R̅Qn RQn RQ̅n

S̅ 1
S 1 1 X X

Characteristic equation for S-R Flip-Flop

Qn+1 = S + R̅Qn

Excitation Table: The i/p signals which command the flip-flop to

change state are called excitations. Excitation table indicates the
inputs required to be applied to the F-F to take it from present state
to the next state.

Excitation table of S-R flip flop

States Inputs
Present(Qn) Next(Qn+1) S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

Gated or Clocked SR Flip-Flop Using NOR gate.

When the Enable input “EN” is at logic level “0”, the outputs of the
two AND gates are also at logic level “0”, (AND Gate principles)
regardless of the condition of the two inputs S and R, latching the two
outputs Q and Q̅ into their last known state. When the enable input
“EN” changes to logic level “1” the circuit responds as a normal SR
bistable flip-flop with the two AND gates becoming transparent to the
Set and Reset signals.

This additional enable input can also be connected to a clock timing

signal (CLK) adding clock synchronisation to the flip-flop creating
what is sometimes called a “Clocked SR Flip-flop“. So a Gated
Bistable SR Flip-flop operates as a standard bistable latch but the
outputs are only activated when a logic “1” is applied to its EN input
and deactivated by a logic “0”.

JK Flip-flop : It is named after its inventor, Jack Kilby. The JK flip-

flop is the most widely used of all the flip-flop designs as it is
considered to be a universal device.

 1. The Set = 0 and Reset = 0 condition (S = R = 0) must always

be avoided
 2. If Set or Reset change state while the enable (EN) input is
high the correct latching action may not occur.

Then to overcome these two fundamental design problems with the

SR flip-flop design, the JK flip Flop was developed.

This simple JK flip Flop is the most widely used of all the flip-flop
designs and is considered to be a universal flip-flop circuit. The two
inputs labelled “J” and “K” are not shortened abbreviated letters of
other words, such as “S” for Set and “R” for Reset, but are themselves
autonomous letters chosen by its inventor Jack Kilby to distinguish
the flip-flop design from other types.

The sequential operation of the JK flip flop is exactly the same as for
the previous SR flip-flop with the same “Set” and “Reset” inputs. The
difference this time is that the “JK flip flop” has no invalid or
forbidden input states of the SR Latch even when S and R are both at
logic “1”.

The JK flip flop is basically a gated SR flip-flop with the addition of

a clock input circuitry that prevents the illegal or invalid output
condition that can occur when both inputs S and R are equal to logic
level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change” and
“toggle”.

The Basic JK Flip-flop

Truth table
CLK J K Qn+1
↑ 0 0 Last stage
↑ 0 1 0(Reset)
↑ 1 0 1(Set)
↑ 1 1 Complement of the
last state(Toggle)

The Truth Table for the JK Function

Clock Input Output

Description
Clk J K Qn Qn+1

↑ 0 0 0 0
Memory
no change
↑ 0 0 1 1

↑ 0 1 0 0
Reset( Qn+1= 0)
↑ 0 1 1 0

↑
1 0 0 1
↑ Set (Qn+1 =1)

↑ 1 0 1 1

1 1 0 1
↑
Toggle
↑ 1 1 1 0

Characteristic Equation
K̅Q̅n K̅ Qn KQn KQ̅n
J̅ 1
J 1 1 1

Qn+1=JQ̅ n + K̅Qn
Excitation table

States Inputs
Present Next J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Race Around Condition In JK Flip-flop – For J-K flip-flop, if

J=K=1, and if clk=1 for a long period of time, then Q output will
toggle as long as CLK is high, which makes the output of the flip-flop
unstable or uncertain. This problem is called race around condition in
J-K flip-flop. This problem (Race Around Condition) can be avoided
by ensuring that the clock input is at logic “1” only for a very short
time. This introduced the concept of Master Slave JK flip flop.

Master-Slave JK Flip-flop

The master-slave flip-flop eliminates all the timing problems by using

two JK flip-flops connected together in a series configuration. One
flip-flop acts as the “Master” circuit, which triggers on the leading
edge of the clock pulse while the other acts as the “Slave” circuit,
which triggers on the falling edge of the clock pulse. This results in
the two sections, the master section and the slave section being
enabled during opposite half-cycles of the clock signal.

The Master-Slave Flip-Flop is basically two gated JK flip-flops

connected together in a series configuration with the slave having an
inverted clock pulse. The outputs from Q and Q̅ from the “Slave” flip-
flop are fed back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the “Slave”
flip flop. This feedback configuration from the slave’s output to the
master’s input gives the characteristic toggle of the JK flip flop as
shown below.

The Master-Slave JK Flip Flop

Working of a master slave flip flop –

1. When the clock pulse goes to 1, the slave is isolated; J and K

inputs may affect the state of the system. The slave flip-flop is
isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and
output is obtained.
2. Firstly the master flip flop is positive level triggered and the
slave flip flop is negative level triggered, so the master responds
before the slave.
3. If J=0 and K=1, the high Q̅ output of the master goes to the K
input of the slave and the clock forces the slave to reset, thus the
slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J
input of the slave and the Negative transition of the clock sets
the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock
and thus the slave toggles on the negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains
unchanged.

Timing Diagram of a Master flip flop –

1. When the Clock pulse is high the output of master is high and
remains high till the clock is low because the state is stored.
2. Now the output of master becomes low when the clock pulse
becomes high again and remains low until the clock becomes
high again.
3. Thus toggling takes place for a clock cycle.
4. When the clock pulse is high, the master is operational but not
the slave thus the output of the slave remains low till the clock
remains high.
5. When the clock is low, the slave becomes operational and
remains high until the clock again becomes low.
6. Toggling takes place during the whole process since the output
is changing once in a cycle.
When the clock is “LOW”, the outputs from the “master” flip flop are
latched and any additional changes to its inputs are ignored. The gated
“slave” flip flop now responds to the state of its inputs passed over by
the “master” section.

Then on the “Low-to-High” transition of the clock pulse the inputs of

the “master” flip flop are fed through to the gated inputs of the
“slave” flip flop and on the “High-to-Low” transition the same inputs
are reflected on the output of the “slave” making this type of flip flop
edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is “HIGH”,
and passes the data to the output on the falling-edge of the clock
signal. In other words, the Master-Slave JK Flip flop is a
“Synchronous” device as it only passes data with the timing of the
clock signal.
D- Flip-Flop

The D Flip Flop is by far the most important of the clocked flip-flops
as it ensures that inputs S and R are never equal to one at the same
time. The D-type flip flop are constructed from a gated SR flip-flop
with an inverter added between the S and the R inputs to allow for a
single D (Data) input.

Then this single data input, labelled “D” and is used in place of the
“Set” signal, and the inverter is used to generate the complementary
“Reset” input there by making a level-sensitive D-type flip-flop from
a level-sensitive SR-latch as now S = D and R = not D as shown.

Truth table

Clk D Qn Description
Memory
↓»0 X Q
no change
↑»1 0 0 Reset Q » 0
↑»1 1 1 Set Q » 1
Characteristic table for the D-type Flip Flop

Clk D Qn Qn+1
↑ 0 0 0
↑ 0 1 0
↑ 1 0 1
↑ 1 1 1

Note that: ↓ and ↑ indicates direction of clock pulse as it is assumed D-type flip flops are
edge triggered

Characteristic Equation

Q̅ n Qn
D̅
D 1 1

Qn+1=D

Excitation table

States Input

Present(Qn) Next(Qn+1) D

0 0 0

0 1 1

1 0 0

1 1 1

T Flip-Flop
Truth table

CLK T Qn+1
↑ 0 Qn(Last state)
↑ 1 Toggle

Characteristic Table

Clk T Qn Qn+1
↑ 0 0 0
↑ 0 1 1
↑ 1 0 1
↑ 1 1 0

Q̅n Qn
T̅ 0 1
T 1 0

Qn+1 = T̅Qn + TQ̅n

Excitation Table

States Input
Present Next T
0 0 0
0 1 1
1 0 1
1 1 0
The applications of Flip-flops are as specified below.

 Counters
 Frequency Dividers
 Shift Registers
 Storage Registers

Asynchronous input

The normal data inputs to a flip flop (D, S and R, or J and K) are
referred to as synchronous inputs because they have an effect on the
outputs (Q and not-Q̅) only in step, or in sync, with the clock signal
transitions.

These extra inputs are called asynchronous because they can set or
reset the flip-flop regardless of the status of the clock signal.
Typically, they’re called preset and clear:

Sometimes the designations “PRE” and “CLR” will be shown with

inversion bars above them, to further denote the negative logic of
these inputs:
PRESET(PRE) is also known as Direct Set(SD) or DC Set.
CLEAR (CLR) is also known as Direct Reset (RD) or DC Reset.
An active level on the PRESET input will SET the Flip-Flop.
An active level on the CLEAR input will RESET the flip-flop.
When DC set and DC reset conditions are not used in any application,
they must be held at their inactive level.

(PRE)' (CLR)' Flip-Flop Response

0 0 Not used
1 0 Q=0
0 1 Q=1
1 1 Clocked Operation
 Flip Flop Conversion

Excitation table

Conversion of J-K Flip-Flop into T Flip-Flop:

Step-1:
Construct the characteristic table of T flip-flop and excitation table of
J-K flip-flop.

Step-2:
Using K map, find the boolean expression for J and K in terms of T.

J=T K=T

Step-3:
Construct the circuit diagram for the conversion of J-K flip-flop into
T flip-flop.

Conversion of J-K Flip-Flop into D Flip-Flop:

Step-1:
We construct the characteristic table of D flip-flop and excitation
table of JK flip-flop.

Step-2:
Using the K-map we find the boolean expression of J and K in terms
of D.

J=D K =D'

Step-3:
We construct the circuit diagram of the conversion of JK flip-flop into
D flip-flop.

Conversion of D Flip Flop to J-K Flip Flop

Conversion of S-R Flip-Flop into D Flip-Flop :

 Step-1:
We construct the characteristic table of D flip-flop and
excitation table of S-R flip-flop.

Step-2:
Using the K-map we find the boolean expression of S and R in terms
of D.

S=D R = D'
Step-3:
We construct the circuit diagram of the conversion of S-R flip-flop
into D flip-flop.

Conversion of D Flip-Flop into S-R Flip-Flop:

Conversion of S-R Flip-Flop into J-K Flip-Flop:
Conversion of J-K Flip-Flop into S-R Flip-Flop:

Conversion of D to T flip-flop
Conversion of T to D flip-flop
Shift Register

Flip-flop is a 1 bit memory cell which can be used for storing the
digital data. To increase the storage capacity in terms of number of
bits, we have to use a group of flip-flop. Such a group of flip-flop is
known as a Register. The n-bit register will consist of n number of
flip-flop and it is capable of storing an n-bit word.

The binary data in a register can be moved within the register from
one flip-flop to another. The registers that allow such data transfers
are called as shift registers. There are four mode of operations of a
shift register.

 Serial Input Serial Output

 Serial Input Parallel Output
  Parallel Input Serial Output
 Parallel Input Parallel Output

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2

= Q1 = Q0 = 0. If an entry of a four bit binary number 1 1 1 1 is
made into the register, this number should be applied to Din bit
with the LSB bit applied first. The D input of FF-3 i.e. D3 is
connected to serial data input Din. Output of FF-3 i.e. Q3 is
connected to the input of the next flip-flop i.e. D2 and so on.

Block Diagram

Operation

Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply

LSB bit of the number to be entered to Din. So Din = D3 = 1. Apply the
clock. On the first falling edge of clock, the FF-3 is set, and stored
word in the register is Q3 Q2 Q1 Q0 = 1000.
Apply the next bit to Din. So Din = 1. As soon as the next negative
edge of the clock hits, FF-2 will set and the stored word change to Q3
Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As
soon as the third negative clock edge hits, FF-1 will be set and output
will be modified to Q3 Q2 Q1 Q0 = 1110

Similarly with Din = 1 and with the fourth negative clock edge
arriving, the stored word in the register is Q3 Q2 Q1 Q0 = 1111.

Truth Table
Waveforms

Serial Input Parallel Output

 In such types of operations, the data is entered serially and taken

out in parallel fashion.
 Data is loaded bit by bit. The outputs are disabled as long as the
data is loading.
 As soon as the data loading gets completed, all the flip-flops
contain their required data, the outputs are enabled so that all the
 loaded data is made available over all the output lines at the
same time.
 4 clock cycles are required to load a four bit word. Hence the
speed of operation of SIPO mode is same as that of SISO mode.

Block Diagram

Parallel Input Serial Output (PISO)

 Data bits are entered in parallel fashion.

 The circuit shown below is a four bit parallel input serial output
register.
 Output of previous Flip Flop is connected to the input of the
next one via a combinational circuit.
 The binary input word B0, B1, B2, B3 is applied though the same
combinational circuit.
 There are two modes in which this circuit can work namely -
shift mode or load mode.

Load mode

When the shift/load bar line is low (0), the AND gate 2, 4 and 6
become active they will pass B1, B2, B3 bits to the corresponding flip-
flops. On the low going edge of clock, the binary input B0, B1, B2, B3
will get loaded into the corresponding flip-flops. Thus parallel loading
takes place.
Shift mode

When the shift/load bar line is low (1), the AND gate 2, 4 and 6
become inactive. Hence the parallel loading of the data becomes
impossible. But the AND gate 1,3 and 5 become active. Therefore the
shifting of data from left to right bit by bit on application of clock
pulses. Thus the parallel in serial out operation takes place.

Block Diagram

Parallel Input Parallel Output (PIPO)

In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data
inputs D0, D1, D2, D3 respectively of the four flip-flops. As soon as a
negative clock edge is applied, the input binary bits will be loaded
into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load
all the bits.

Block Diagram

Bidirectional Shift Register

 If a binary number is shifted left by one position then it is

equivalent to multiplying the original number by 2. Similarly if
a binary number is shifted right by one position then it is
equivalent to dividing the original number by 2.
 Hence if we want to use the shift register to multiply and divide
the given binary number, then we should be able to move the
data in either left or right direction.
  Such a register is called bi-directional register. A four bit bi-
directional shift register is shown in fig.
 There are two serial inputs namely the serial right shift data
input DR, and the serial left shift data input DL along with a
mode select input (M).

Block Diagram

Operation

S.N. Condition Operation

If M = 1, then the AND gates 1, 3,
5 and 7 are enabled whereas the
remaining AND gates 2, 4, 6 and 8
will be disabled.
With M = 1 − Shift right
1 The data at DR is shifted to right bit
operation
by bit from FF-3 to FF-0 on the
application of clock pulses. Thus
with M = 1 we get the serial right
shift operation.
 When the mode control M is
connected to 0 then the AND gates
2, 4, 6 and 8 are enabled while 1, 3,
5 and 7 are disabled.
With M = 0 − Shift left
2 The data at DL is shifted left bit by
operation
bit from FF-0 to FF-3 on the
application of clock pulses. Thus
with M = 0 we get the serial right
shift operation.

Applications of Shift Register:

1) Ring Counter
2) Johnson (Twisted Ring) Counter
 Counter Design
Counter is a sequential circuit. A digital circuit which is used for a
counting pulses is known counter. Counter is the widest application of
flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types.

 Asynchronous or ripple counters.

 Synchronous counters.

Following are the important differences between Synchronous and

Asynchronous Counter.
Sr.
Key Synchronous Counter Asynchronous Counter
No.
In case of Synchronous
On other hand in case of
Counter, as the name
Asynchronous Counter
suggests all the constituent
1 Trigger there is triggering of
flip flops are triggered
different flip flops with
with same clock
different clock.
simultaneously.
As mentioned above in
case of Synchronous On other hand in case of
Counter all flip flops are Asynchronous Counter
triggered altogether hence operation speed is
2 Speed
operation speed of counter comparatively slower
become faster as compared than Synchronous
to that of Asynchronous counter.
counter.
Synchronous Counter is While on other hand
less error prone and hence Asynchronous Counter is
3 Error Prone
hardly produces any more error prone and
decoding error in the produces decoding error
Sr.
Key Synchronous Counter Asynchronous Counter
No.
system. in the system.
On other hand as output
As all flip flops are being
of one flip flop
coordinating with the clock
performing as input of
hence the design and
4 Complexity next flip flop the design
implementation is complex
and implementation is
as compared to that of
quite simple in case of
Asynchronous Counter.
Asynchronous counter.
Synchronous Counter
On other hand
could be operated in any
Asynchronous counter
desired count sequence as
5 Sequence could operate only in
it could get manipulated by
fixed count sequence i.e.,
changing the clock
UP and DOWN.
sequence.
However on other hand
there is a subsequent
There is no propagation
propagation delay from
6 Delay delay observed in case of
one flip flop to another
Synchronous Counter.
in case of Asynchronous
Counter.

Classification of counters

Depending on the way in which the counting progresses, the

synchronous or asynchronous counters are classified as follows −

 Up counters
 Down counters
 Up/Down counters
UP/DOWN Counter

Up counter and down counter is combined together to obtain an

UP/DOWN counter. A mode control (M) input is also provided to
select either up or down mode. A combinational circuit is required to
be designed and used between each pair of flip-flop in order to
achieve the up/down operation.

Modulus Counter (MOD-N Counter)

The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple
counter is called as MOD-8 counter. So in general, an n-bit ripple
counter is called as modulo-N counter. Where, MOD number = 2n.

Type of modulus

 2-bit up or down (MOD-4)

 3-bit up or down (MOD-8)
 4-bit up or down (MOD-16)

Application of counters

 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.
Asynchronous Counter Design
Two-bit Ripple Up-Down Counter using negative edge triggered
flip-flops

Two-bit Ripple Down Counter using positive edge triggered flip-

flops
Two-bit Ripple Up-Down Counter using positive edge triggered
flip-flops
Modulus Counter Design
 ◄
544 FUNDAMENTALS OF DIGITAL CIRCUITS

We see that these equations are the same as the equations obtained by the direct design of the
up/down cou ntt'.'r. So. the cir cuit will be the same as that shown in Figure 12.15 .

12.5.5 Design of a Synchronous Modulo-1 O up/down Counter Using T FFs

Step I. The number of flip -flops : A modulo-IO counter has 10 states and so it requires 4 FFs.
( l0 ~2 4) .
4-FFs can have 16 states. So out of 16, six states ( 1010 through 1111) are invalid. The entries
for ex.citations corresponding to invalid states are don't cares. For selecting up and down modes a
control or mode signal is required. Let us say it counts up when the mode signal M = 1 and counts
down when M = 0. The clock signal is applied to all the FFs simultaneously.
Step 2. The state diagram: The state diagram of the mod-10 up/down counter is drawn as shown
in Figure 12.20a.
Step 3. The type offlip-flops and the excitation table: T flip-flops are selected and the excitation
table of the modulo- IO up/down counter using T FFs is drawn as shown in Figure 12.16b.
1
PS Mode NS Required excitations
04 03 02 01 M T4 T3 T2 T1
0 0 0 0 0 1 0 0 1 1 0 0 1
0 0 0 0 1 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 0 0 1 0 0 1 1
0 0 1 0 1 0 0 1 1 0 0 0 1
0 0 1 1 0 0 0 1 0 0 0 0 1
0 0 1 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 0 0 1 1 0 1 1 1
0 1 0 0 1 0 1 0 1 0 0 0 1
0 1 0 1 0 0 1 0 0 0 0 0 1
0 1 0 1 1 0 1 1 0 0 0 1 1
0 1 1 0 0 0 1 0 1 0 0 1 1
0 1 1 0 1 0 1 1 1 0 0 0 1
0 1 1 1 0 0 1 1 0 0 0 0 1
1 1 0 1 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 1 1 0 0 1 0 0 0 1
1 0 0 1 0 1 0 0 0 0 0 0 1·
1 1 0 0 1 1 0 0 0 0 1 0 0 1
(a) State diagram (b) Excitation table
Figure 12.20 Synchronous mod-10 up-down counter.

Step 4. The minimal expressions: From the excitation table we observe that T = 1 because all
the entries for T I are either 1 or X. The K-maps for T and T based on the excitafion table and the
3
minimal expressions obtained from them are shown i~ Figure 12.21. Also drawing and minimizing
the K-maps for T2, we get
T2 = Q4QIM + ~QIM + Q2Q1M + Q3QIM
Step 5. The logic diagram: The logic diagram based on those minimal expressions is drawn as
shown in Figure 12.22.
 couNTEAS

1
0
QM
1 .
1
01 11 10
02 00 01 11 10 02 00 ,.-19 18
17
1 3 2
00 I
10 00 11'6 1
22
21 23
4 5 7 6 20 X
X X
01 X
01
30
12 13 14 28 29 d1 ...
11
~1 5
11 X X
~- X

25 27 26
8 9 11 10 24
X X X
10 X
10 .__

QM
1 0 1

02 02 00 01 11 10
00 01 11 10
-16 17 19 18
0 1 3 2
00 00 1

20 21 _23 22
4 5 - 7 6
X X X
01 1 01 X

14 28 29 31 30
12 13 15
X X X X
11 1 11

11 10 24 25 27 26
9 X
118 10 X X X
10 -
T3= O4O,M + O2O1M+ os<'.5)5,M
Figure 12.21 K-maps for excitations T4 and T3 of a mod-10 up-down counter.

0 40 1M O3O261M O3O261M
040 1M O4O1M 0 40 1M
0 201M 0 20 1M 0 30 20 1M
0 30,M
T2 02 T3 03 T4 04
T,
FF2 FF3 FF4

02 03 04

CLK
Figure 12.22 Logic diagram of synchronous mod-10 up-down counter.
In the K-maps, the remaining minterms are don't cares Cui ( 20, 21 , 22, 23, 24, 25, 26, 27,
28, 29, 30, 31)).
From the excitation table we can see that T1= 1 and the expressions for T4, T 3 and T2 are·.
T ::: l:m(0, 15, 16, 19) + d( 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
4
T l:m(7, 8, 15, 16) + d( 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
:::
3
r = l:m(3, 4, 7, 8, 11, 12, 15, 16) + d ( 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 )
2
 646 l=UNOA.MENTAL S OF DIGITAL CIRCUITS

12.5 .6 Desi gn a Modulo~ 9 synchronous Counter

Using T FFs
StPp l . The wnhrr nf flip -j1ops: We know that the coun
11 ting sequence for a mod ulo-9 counter i
()()()(). 0001. (l()l o. O(ll I. 0100. oIO 1, oJ Io. O111. I 000.
0000 , ... . It has 9 states. So it requires :
Ffs(9 :S _2 4). 4 flip-flops can have 16 states. 7 states _IOOl
, _1010_. lOll , llOO, ll_Ol , 111 0, and
111 1are invalid. The entties for ex.citations corre sponding
to rnvahd states are don t cares .
Step 2. The state diagram~· The state diagram for the mod- 9 counter is drawn as shown in Figure 12_23a_
S1ep 3. !he type offlip-flops and the excitation table: T ?ip~flops
are selected and the excitation
table of a mod-9 counter using T FFs is drawn as show
n m Figure 12.23b.
PS NS Requ ired Excita tions
0 4 03 02 o, 0 4 0 3 0 2 o, T4 T3 T2 T,
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 1 0 0 0
(a) State diagram
(b) Excitation table
Figure 12.23 A synchronous mod-9 coun ter.

Step 4. The minimal expressions: The K-maps for excit

ations T 4 , T 3, T 2 , and T 1 in terms of the
outputs of the FFs ~ . Q , Q , and Q , their minimization
3 2 1 and the minimal expressions for excitations
obtained from them are shown in Figure 12.24.
020, 0 201
03 00 01 11 10 03 00 01 11 10
0 1 3 2 0 1 - 3 2
00 00 1
5
01
4
-1 7 6
01
4 5 7 6
1
12 13 15 14 12 13 15 14
11 X X X X 11 X X X X
-
B 9 11 10 8 9 11 10
10 1 X X X 10 X X X
-
002 1 0 20 1
03 00 01 11 10 03 00 01 11 10
0 1 3 2 0 1 3 2
00 1 1 00 1 1 1 1
4 5 7 6 4 5 7 6
01 1 1 01 1 1 1 1
12 13 15 14 12 13 15 14
11 X X X X
11 X X X X

8 9 11 10 8 9 11 10
10 X X X
10 X X X

T2= 0, T -Q
Figu re 12.2 4 K-maps for excitations of synchronous 4
mod-9 c~:nter using T flip-fl ops.

,,
 COUN TERS 547
Srep "· Tltt logic du,1,vam: The logic diagr am based on those
sh<)\H l in h gure l 2.25 .
rninim <1l expre ssion s is drawn a~,

PRE
PRE PRE

T2
02 T3 04
FF2
FF4
02 03 6"
CLK CLR CLR CLR CLR
Figure 12.25 Logic diagram of the synchronous mod-9 counter using
T flip-flops.

12.5.7 Design of a Synchronous Modulo-6 Gray Code Coun

ter
Step 1. The number offlip-flops : We know that the counting
sequence for a modulo-6 Gray code
counter is 000, 0()1 , 011, 010, 110 and 111. It requires n = 3 FFs
(N ~ 2n, i.e. 6 ~ 23) . 3 FFs can have
8 state s. So the remaining two states 10 l and 100 are
invalid. The entries fo r excitations
corresponding to invalid states are don't cares .
Step 2. The state diag ram: The state diagram of the mod-6 Gray
code counter is drawn as shown
in Figure 12.26a.
Step 3. Type of flip -flop s and the excitation table: T flip-f
lops are selected and the excitation
table of the mod-6 Gray code counter using T flip-flops is writte
n as shown in Figure 12.26b.

PS NS Required Excitations
03 02 o, 03 02 01 T3 T2 T,
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 0 1
0 1 0 1 0 1 0 0
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

(a) State diagram (b) Excitation table

figur e 12.26 Synchronous mod-6 Gray code counter.

. , .. ,. The K-maps for excitations of FFs T , T and T in

Step 4. The mini mal e.xpr;~s~n\heir minimization and the 3 2 1 terms of
minimal expressions for ex.cit ation s
outputs of FFs Q3, Q2 a I'_ p· 12•27
obtai ned from them are sh own 1n 1oure0 ·
. ..
T h 0 gic diagram based on those mrn1 . .
mal expressions 1s drawn as.
Step 5. The log ic diagram: 1
e
show n in Figure 12.28 .
548 FUND AMENTALS OF DIGITA L CIRCUITS

QQ
. ~ , Q2Q1
Q3
00 01 11 10 a3 00 01 11 10 01 11
0 ~1 3 2
Q
0 1
3 IJJ2 0 1 0

7 6 4 5
.: 5 7 6 4 5 7
1 X Ix 1I 1 X IX 1 I X X

T3 = 0 30 , + 0 30 i 51 T2 = 0301 + 0 20, T, = 0 3 + 020, + Oi~,

Figure 12.27 K-maps for excitations of a synchronous mod-6 Gray code counter.

0301 0301
03
020, 0 3020 ,
0 20 ,
02'5, T, o, T2 02 T3 03
FF 1 FF2 FF 3

o, 02 03 -

CLK

Figure 12.28 Logic diagram of a synchronous mod-6 Gray code counter.

12.5.8 Design of a Synchronous Modulo-10 Gray Code Counter

Step I. The numb er of flip-flops: We know that the counting sequence for a modulo-10 Gray
code counter is 0000, ()()1)1, 0011 , 0010, 0110, 0111 , 0101 , 01 00, 1100, 1101, 0000 .... It has
4 have 16 states. So the
10 states and so it requires n = 4 FFs (N $ 2n, i.e. 10 $ 2 ). Four FFs can
entries for excitations
remai ning six states 1111 , 1110, 1010, 1011 , 1001 and 1000 are invalid. The
corresponding to these invalid states are don't cares.
Step 2. The state diagr am: The state diagram of the mod- IO Gray
code counter is drawn as
shown in Figure 12.29a.
Step 3. The type offlip-fl ops and the excitation table: T flip-flops
are selected and the excitation
Figure 12.29b.
table of the mod-IO Gray code counter using T FFs is written as shown in
PS NS Required Excitations

04 0 3 02 o, 04 03 02 o, T4 T3 T2 T,
0 0 1
0 0 0 0 0 0 0 1 0
0 1 0
0 0 0 1 0 0 1 1 0 1
1 0 0 0 0
0 0 1 1 0 0 0
0 0 1 0
0 0 1 0 0 1 1 1
1 0 0 0
0 1 1 0 0 1 1
1 0
0 1 0 1 0 0
0 1 1 1 0 1
1 0 0 0 0
0 1 0 1 0 0 0
1 0 0 1 0
0 1 0 0 1 0 1
0 1 0 0
1 1 0 0 1 1 0 _J_
0 0 1 1
1 1 0 1 0 0
(b) Excitation table
(a) State diagram
Figure 12.29 Synchronous mod-1O Gray code counter.
►

COUNTERS 549

S1ep 4. :n,e minimal expressions: Th

l,utputs of FFs Q , Q , Q and Q h .e K~~a~s f~r excitations of FFs T4, T3, T2 and TI in terms of
4 3
t)brnined from them are shown -1' Ft. eir nummization, and the minimal expressions for excitations
_ m igure 12.30.
Srep 5. The logic diagram: Th e 1og1c . . . . drawn as
shown .m p·1gure 12.3 I. diagram bas ed on those nurumal
. . express10ns 1s

o201 0 201
03 00 01 11 10 03 00 01 11 10
0 1 3 2
00 0 1 3 2
00 1
.___
5 7
01 [Ii4 6
01
4 5 7 6

12 13 15 ,. 14 12 13 15 14
11 1 X X 11 1 X X

8 9 11 10 8 9 11 10
10 X X X X 10 X X X
r7
I I

00
2 1

10 03 00 01 11 10
1 3 2
00
3 2
00 1 lo 1
'---

7 6 4 - 5 7 - 6
01 01 1 1
13 15 14 12 13 15 14
12
11 X X

10
11 1
8
1
'--

9 rx71
X
- X

10

10 X
X 10 xi X X
I
I I

T = 0 30 20 1 + OsC)20, T, = 0 4 + 0 30 20 1 + 0 30 20 1
2
+ 630 20 1 + ci3cii~,

figure 12.30 K-maps for excitations of a synchronous mod-1 OGray code counter.

04
ai.520 1 030201 0401 0 401
0 30 i 5, - ----1 a i 52a , 03020 1 0403020,
0 30 201 02 T3 03 04
a, T2
6/:5201 T1
FF3 FF4
FF2
FF1
02 03 04
a,

CLK . f synch ronous mod-10 Gray code counter using T FFs.

Logic diagram o
Figure 12.31
S50 ruNOAcMENTALS OF DIGITAL CIRCUITS

12.5.9 Design of 8 Synchronous BCD Counter Using J-K FFs

Step 1. 11ie number()!fl ip-flops: A BCD counter is nothing but a mod-IO counter. It is ad
counter. It ha!- 10 states (0000 through lt requires n = 4 FFs (N ~ 2n, i.e. 10 S 24).
1001). Fou:c;!e
can baYe 16 states. After the tenth clock pulse, the counter resets. So, states 10 IO through, 111 s
. \'1d. The entries for excitations corresponding
mvn · to mva
· l'd1 states are don ' t cares. l are
Stt'/ 1 2. Th e state diagram : The state diagram of the BCD counter is drawn as sho .
Figure 12.32a. wn 1n
S1ep 3. The type offlip-flops and the excitation table: JK flip-flops are selected and the excit t'
table of the BCD counter using J-K FFs is drawn as shown in Figure 12.32b. a ion
Step 4. ~he min imal expressions: The K-maps for the excitations of FFs J4, K~, 13, K , J , 1½, J
3 2
and K m
. . 1. .
terms of the outputs of the FFs C2i, Q 3, Q2 anJi Q 1, based on the exc1tation table, therr.1
muum1zat1on and the minimal expressions obtained from them are shown in Figure 12.33.

(a) State diagram

PS NS Required excitations
0 4 0 3 0 2 01 04 0 3 0 2 0 1 J4 K4 J3 K3 J2 K2 J, K1
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
0 0 1 0 0 0 0 X 1 0 X 0 X X 1
(b) Excitation table
Figure 12.32 Synchronous BCD (mod-1 O) counter.

oa
2 1 00
2 1 0 20 1
Q403 00 01 11 10 o403 00 01 11 10 o403 00 01 11 10
0 1 3 2 0 1 3 2 2
0 1 - 3
00 00 X X X X 00 1
4 5 ...- 7 6 4 5 7 6 4 5 7
- 6
01 1 01 X X X X 01 X X X
)(

12 13 15 14 12 13 15 13 15 14
14 12 )(
11 X X )( X 11 )(
- X X X X 11 X X

11
~
1(
8 9 11 10 8 11 9
)(
9 10 8 )(
10 X X )(
10
-=---
X
1 )( X 10

J4 = aaa,p, K" = o, J3= o2a ,

Figure 12.33 K-maps for excitations of synchronous BCD counter using J-K flip-flops (Contd.J. ..
 COUNTERS 551
0 20 ,
OQ
2 1 QO
0 ~Ql 00 01
2 1
11 10 03
0 1 00 01 11 10 03 00 01 11 10
3 2
00 1 X 0 1 3 2 0 1 ..-- 3 2
X
00 X X 1 00 )( X X )(

o, 4 s 7 6
1 X X 4 s 7 6 4 5 7 6
01 X X 1 01 1
12 13 15
11 X 14
X )( 12 13 14
X 15 14 12 13 15
11 X X X X
8
X 11 X X X
9 11 10
10 X 8 9 11
X 10 8 9 11 10
10 X X

J2 = 0 40 , - X X 10 X X
-X X

~=0 , ~ = ~0,
Figure 12.33 K-rnaps fo
r exc1•t at1on
.
s of synchronous BCD coun ter using J-K flip-fl ops.
Srep 5 · The logic diagram: The logic diagram based on those minimal expressio
show n in Figu re 12.30. ns is drawn as

J1 01 J2 02 J3 03 04
FF 1
FF 2 FF 3 FF4
K1 a, K2 02 K3 03 K4 04
CU<

Figure 12.34 Logic diagram of synchronous BCD counter using

J-K flip-flops .
The state diag ram and the table to check for lock-out
are show n in Figure 12.35 . The table to
chec k for lock -out show s that, if the counter finds
itself in an invalid state initially, it moves to a
valid state after one or two clock pulses and then counts
in the normal way. Therefore, the counter
is self- starting.

PS Present inputs NS
a,. 03 0 2 a1
1 0 1 0 0 0 O O O 0 1 1 1 0 1 1
1 0 1 1 0 1 1 1 0 1 1 0 0 0
0 0 O O O 0 1 0 1
0 0
1 0 1 O O O 1 1 1 0 0 0
1 1 0
O O O .0 1 1 1 1 1 1
1 1 1 0 0 0
1 0 1 1 1 0 0 0 0
1 1 1 1 1 1
k for lock-out (b) State diagram
(a) Table to c hec
. f k out of Sync hronous BCD counter using J-K flip-fl ops.
Figu re 12.35 Checking or Ioc

hronous Mod-6 cou nter Using J-K FFs

12.5.1o Design of a Sync
. .
.. W>k ow that the countrng sequ ence for a mod-6 counter 1.s
Step l . The number of flip -flops. ~ : , six states. So it requires n = 3 FFs (N $ 2", i.e. 6 ~ 23) .
000 00 J () J() O11. 100. 10 l. OOO, · · · · t as , , . g two state
' ' • , st, , , So the remain10 s 110 and 111 are invalid. The entries
Three FFs can have eigh t ates. . . . , . , e don't cares. ·
. . d' to invalid states ar
for excitations corr espo n mg
552 FU NDAMENTALS OF DIGITAL CIRCU ITS

The state diagram for the mod-6 counter is drawn as shown in Figure 12 _
Ster 2. 771,• .,·tace Jiagrom:
. .36a
Step 3 The type' offlip -J1ops and the excitation table: JK fli p-flops are selected and the ex . . ·
. p· 12 36 cnat1on
lu b le of a mod-6 counter usi ng J-K FFs is drawn as shown m 1gure . b. (States 110 and 1
can be removed from the state diagram if it is not required to determine whether the counter.1s, self lt
.
starting or not) .
PS NS Required excitations
03 02 01 03 0 2 01 J3 K3 J2 ~ J1 K,
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0- X X 1

(a) State diagram (b) Excitation table

Figure 12.36 Synchronous mod-6 counter using J-K flip-flops.

Step 4. The minimal expressions: The K-maps for excitations of FFs J 3 , K3 , J 2 , Kz. J 1 and K 1 in
terms of the outputs of FFs Q3, Q2 and Q 1, their minimization, and the minimal expressions for
excitations obtained from them are shown in Figure 12.37.
0201 Q2Q 1 Q 2Q 1
03 00 01 11 10 Q3 00 01 11 10 Q3 00 01 11 10
0 3 2 0 1 3 2 0 1 3 2
0 0 X X X X 0 I 1 xi X

4 5 7 6 4 5 7 6 4 5 7 6
1 X X X X 1 1 X X 1 X X

QO
2 1
00
2 1 00
2 1
03 01 11 10 03 00 01 11 10 03 00 01 11 10
00
0 1 3 2 0 1 3 2 0 1 3 2
0 X X 1 0 1 X X 1 0 X 1 1 X

7 6 4 5 7 6 4 5 7 6
4 5
1 1 1 X X
1 X X X X X X X 1 X

K2 = 0 1 J1 =1 K1 = 1
Figure 12.37 K-maps for excitations of synchronous mod-6 counter using J-K fl ip-flops.

Step 5. The logic diagram: The logic diagram based on those minimal expressions is drawn as
shown in Figure J 2.38.
1

FF1

K, .___- ---'--I K3
L-- --
CLK
Figure 12.38 Logic diagram of synchronous mod-6 counter using J-K flip-flops.