Instruction Set

Q. 1 : Explain the addressing modes of 8085 ?

Ans : There are five types of addressing modes .
1) Direct addressing mode :
1) In this addressing mode the address of the operand is given in the instruction itself.
2) In direct addressing modes the address appears after opcode of instruction in
program memory.
3) This is generally 3 mbyte instruction. Byte 1 opcode of instruction, byte 2 is lower
address and 3 byte for higher order address.
4) For ex. LDA 9FFFF H
2) Register addressing mode :
1) In this addressing mode the operand is given in the general purpose register whose
name is given in the instruction itself.
2) The general purpose registers are B,C, D, E, H and L.
3) This is generally one byte instruction.
4) For ex. MOV A,B
3) Register Indirect addressing modes :
1) In this addressing mode the opearnd is give in the memory whose address is
specified by H-L pair.
2) This is generally one byte instruction.
3) For ex. ADD M
4) Immediate addressing mode :
1) In this addressing mode the actual data is given in the instruction itself.
2) In this addressing mode the instruction is ending with letter ‘I’.
3) For ex. MVI A,05 H
5) Implicit or Impplied addressing mode :
1) In this addressing mode the operand is given in the accumulator itself.
2) Most of the logical group instructions belong to this addressing modes.
3) Most of the logical group instructions to this addressing mode.
4) For ex. CMA

1..
1) Data Transfer Intructions
In data transfer intructions the contents of source are copied into destination
without modifying the content of source. The data data transfer intructions do not affect
the flags. These intructions are mentioned below:

1) MOV r1, r2 (Move register)

(r1) < (r2)
1) The content of register r2 is moved to register r1.
2) r1 and r2 can be of one of the registers A, B, C, D, E , H & L.
3) The addressing mode is Register addressing mode.
4) This is one byte instruction.
For example : MOV A, B
Contents of register B are moved to register A (i.e. accumulator).
2) MOV r, M (Move from memory)
(r) < (H) (L)
1) The contents of memory location, whose address is in registers H and L, is moved
to register r.
2) r can be any one of the registers A, B, C, D, E, H & L.
3) This is Register Indirect addressing mode.
4) This is one byte intruction.
For example : MOV B, M
The content of memory whose address is specified by HL pair is moved to B.
3) MOV M, r (Move to Memory)
((H) (L)) < (r)
1) The contest of register r is moved to the memory location whose address is in
registers H and L.
2) r can be any one of the registers A, B, C, D, E, H, L.
3) This is Register Indirect addressing mode.
4) This in one byte instruction.
For example : MOV M, C.
Here content of register C are moved to memory whose address is specified
by HL pair.

2..
4) MVI r, data (Move Immediate 8 bit )
(r) < (byte 2)
1) The contents of byte 2 (data) of instruction is moved to register r.
2) r can be any one of the registers A, B, C, D, E, H & L.
3) This is Immediate Addressing mode.
4) This is two byte instruction.
For example: MVI A, 82 H
The data 82 is moved to accumulator.
5) MVI M, data (Move immediate to memory )
((H) (L)) < (byte 2)
1) The content of byte 2 of the instruction is moved to memory location whose
address is in registers H and L.
2) This is Immediate Addressing /Register addressing mode.
3) This is two byte instruction.
For example: MVI M, 12 H
The data 12 is moved to memory pointed by HL pair.
6) LXI rp, 16 bit data (Load register pair immediate)
(rh) < (byte 2) (byte 3)
1) Byte 3 of the instruction is moved into the high-order register (rh) of register pair
rp. Byte 2 of the instruction is moved into the low order register (rl) of register
pair rp.
2) This is ImmediateAddressing mode.
2) This is three byte instruction.
The register pair rp can be one of the register pairs BC, DE, HL, or SP. rh is
First register in pair and rl is second (low order) register in pair.
For example: LXL H, 4000H
Here 40H is moved to H and 00H is moved to L
7) LDA addr (Load accumulator direct)
(A) < [(byte 3) (byte 2)]
1) The content of the memory location, whose addressing is specified in byte 2
and byte 3 of the instruction, is moved to register A.
2) This is Direct Addressing mode.
3) This is three byte instruction.
For example: LDA C000H
The contect of memory location C000H is moved to register A. 3..
8) STA addr (Store Accumulator Direct)
[(byte 3) (byte 2)] < (A)
1) The contect of accumulator is moved to the memory location whose address is
specified in byte 2 and byte 3 of instruction.
2) This is Direct Addressing mode.
3) This is a three byte instruction.
For example: STA D000 H.
Contents of accumulator are moved to D000.
9) LHLD addr(Load H and L register direct)
(L) < [(byte 3) (byte 2)]
(H) < [(byte 3) (byte2)+1]
1) The content of memory location whose address is specified in the byte 2 and
byte 3 of the instruction, is moved to register L. The content of memory
location at the succeeding address is moved to register H.
2) This is Direct Addressing mode.
3) This is a three byte instruction
For example: LHLD 2100 H
The content of 2100 are moved to L and 2101 to H.
10) SHLD addr (Store H and L register direct)
[(byte 3) (byte 2)] < (L)
[(byte 3) (byte 2) +1] < (H)
1) The contect of register L is moved to the memory location whose address is
specified in the byte 2 and byte 3. The content of register H is moved to
succeeding memory location.
2) This is Direct Addressing mode.
3) This is a three byte instruction
For example: SHLD 3520 H.
The contect of L are moved to3520 and that of H to 3521.

4..
11) LDAX rp (Load accumulator indirect)
(A) < [(rp)]
1) The content of memory location, whose address is in register pair rp, is moved
to register A.
2) rp can be (i.e. B and C) or D (ie D and E)
3) This is Register Indirect addressing mode.
4) This is one byte instruction.
For example : LDAX B
The content of memory location pointed by BC pair is moved to accumulator.
12) STAX rp (Store accumulator indirect)
[(rp)] < (A)
1) The content of register A is moved to the memory location whose address is in
register pair rp.
2) rp is (ie BC pair) or D (ie DE pair).
3) This is Register Indirect addressing mode.
4) This is one byte instruction.
For example : STAX D
The content of A are moved to memory pointed by DE pair.
13) XCHG (Exchange H and L with D and E)
(H) < > (D)
(L) < > (E)
1) The content of register H are exchanged with that of register D the content of
register L are exchanged with that of register E.
3) This is Register addressing mode.
4) This is one byte instruction.
For Ex. [H] = 23 H and [L] = 32 H [D] = 53H and [E] = 55 H
[H] = 53 H and [L] = 55 H [D] = 23H and [E] = 32 H

5..
Arithmetic Instructions
The 8085 arithmetic instructions performs various arithmetic operations, such as addition,
ubtraction, increment and decrement. These instructions flags and they are discussed
below:
1) ADD r (ADD Register)
(A) < (A) + (r)
1) The content of accumulator is added to the contents of the register r.
The result is placed in accumulator.
2) This is Register addressing mode.
3) This is one byte instruction.
For example : ADD B
The content of accumulator added to contents of register B.
2) ADD M (ADD memory content to accumulator)
(A)< (A) + ((H) (L))
1) The content of accumulator is added to the contents of memory location whose
address is contained in the H and L register . The result is placed in accumulator.
3) This is Register Indirect addressing mode.
4) This is one byte instruction.
3) ADI data (ADD Immediate to accunulator)
(A) < (A) + (byte 2 )
1) The content of accumulator is added to the second byte of the instruction
The result is placed in accumulator.
2) This is Immediate Addressing mode.
3) This is Two byte instruction.
For examplel : ADI 05 H
The content of accumulator is added to the data 05.
4) ADC r (ADD register to accumulator with carry)
(A) < (A) + (r) + (cy)
1) The content of accumulator are added to the content of register r and the content
of the carry bit . The result is placed in accumulator.
2) This is Register addressing mode.
3) This is one byte instruction.
For example : ADC B
Content of register r along with carry bit are added to accumulator.
6..
5) ADC M (ADD memory content to accumulator with Carry)
(A) < (A) + ((H) (L)) + (cy)
1) The content of accumulator are added to contents memory location whose
address is contained in H and L registers and content of carry flag .
The result is placed in accumulator.
3) This is Register Indirect addressing mode.
4) This is one byte instruction.
6) ACI data (ADD Immediate to accumulator with Carry)
(A) < (A) + (byte 2) + (cy)
1) The content of accumulator are added to the contect of second byte of the
instruction and the contents of carry flag. The result is placed in accumulator.
2) This is Immediate Addressing mode.
3) This is Two byte instruction.
For examplel : ACI 05 H
The data 05 and carry flag bit is added to the content of accumulator.
7) SUB r (Subtract Register from accumulator)
(A) < (A) - (r)
1) The content of register r is subtracted from the content of accumulator.
The result is placed in accumulator.
2) This is Register addressing mode.
3) This is one byte instruction.
For example : SUB B
Content of register b is subtracted from content of accumulator.
8) SUB M (Subtract memory from accumulator)
(A) < (A) - ((H) (L))
1) The content of memory location whose address is contained in H and L
registers is subtracted from the content of accumulator.
The result is placed in accumulator.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.

7..
9) SUI data (Subtract immediate from accumulator)
(A) < (A) - (byte 2)
1) The content of second byte of the instruction is subtracted from the contents of
the accumulator. The result is placed in accumulator.
2) This is Immediate addressing mode.
3) This is Two byte instruction.
For examplel : SUI 05 H
The 05 H is subtracted from accumulator
10) SBB r ( Subteact register and borrow from accumulator)
(A) < (A) - (r) - (cy)
1) The content of register r and carry bit are subtracted from content of
accumulator. The result is placed in accumulator.
2) This is Register addressing mode.
3) This is one byte instruction.
11) SBB M (Subtract Memory content and borrow from accumulator)
(A) < (A) - [(H) (L)] - (cy)
1) The content of memory location whose address is stored in HL pair along with
carry flag are subtracted from content of accumulator.
The result is placed in accumulator.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.
12) SBI data (Subtract immediate with borrow)
(A) < (A) - (byte 2) - (cy)
1) The content of second byte of the instruction and the contents of carry flag are
both subtracted from the accumulator. The result is placed in accumulator.
2) This is Immediate Addressing mode.
3) This is Two byte instruction.
13) INR r ( Increment register content by one )
[r] < [r] + 1
1) The contents of register r is incremented y one and result is palced in same palce.
2) r can be any A , B , C , D , E , H & L.
3) This is Register addressing mode.
4) This is One byte instruction.
For Ex. INR B
The contents of register B is incremented by one. 8..
14) INR M (Increment memmory content by one)
[(H) (L)] < [(H) (L)] + 1
1) The content of memory location whose address is contained in H and L register
is incremented by one. Result is placed in same place.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.
15) INX rp (Increment register pair by 1)
[rp]< [rp] + 1
1) The content of register pair rp is incremented by one. No condition flag are
affected.
2) This is Register addressing mode.
3) This is one byte instruction.
16) DCR r (Decrement Register by 1)
(r) < (r) - 1
1) The content of register r is decremented by one and result is placed in the same
place.
2) This is Register addressing mode.
3) This is one byte instruction.
17) DCR M (Decrement Memory by 1)
[(H) (L)] < [(H) (L)] - 1
1) The content of memory location whose address is contained in H and L register
is decremented by one and result is placed in same place.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.
18) DCX rp (Decrement register pair by 1)
[rp]< [rp] - 1
1) The content of register pair rp is decremented by one. No condition flag are
affected.
2) This is Register addressing mode.
3) This is one byte instruction.
19) DAD rp (Add register pair to H and L)
(H) (L) < (H) (L) + (rh) (rl)
1) The content of register pair rp is added to the content of the register pair H and
L. The result is placed in register H and L. Only Cy flag is affected.
2) This is Register addressing mode. 3) This is one byte instruction. 9..
 20) DAA (Decimal Adjust Accumulator)
1) The Eight bit number in accumulator is adjusted to from two four - bit Binary -
coded -Decimal digits by the following process.
a) If the value of the least significant 4 bit of the accumulator is grater than 9
or if the AC flag is set, 6 added to the lower order 4 bits of accumulator.
b) If the value of the most significant 4 bit of the accumulator is greater than
9, or if the CY flag is set, 6 added to the most significant 4 bit of the
accumulator. All flags are affected.
c) If both 4 LSB’s and 4 MSB’s of accumulator are greater than 9 or AC and
carry flag are set respectively then 66 is added to the accumulator.
2) This is Implied addressing mode.
3) This is one byte instruction.
Logical Instructions
1) ANA r ( Logically AND with Accumulator )
(A) < (A)
^(r)
1) The content of accumulator is logically ANDed with the content of register r.
The result is placed in accumulator. The S , Z and P flags are modified.
the cary flag is reset and AC flag is set.
2) This is Register addressing mode.
3) This is one byte instruction.
For example : ANA B
The content of A are ANDed with the content of B.
If A = FFH = 1111 1111
B = 02H = 0000 0010
ANA B = 0000 0010
02 H
2) ANA M ( Logically AND with memory)
(A) < (A)
^ ((H) (L))
1) The content of accumulator s logically ANDed with the content memory location
whose address is contained in the H and L registers. The result is placed in
accumulator.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.

10..
 3) ANI data (AND Immediate with accumulator)
(A) < (A)
^ (byte 2)
1) The content of accumulator is logically ANDed with the content of the second
byte of the instruction .The result is placed in accumulator. The S , Z and P flags
are modified. The cary flag is cleared and AC flag is set.
2) This is Immediate Addressing mode.
3) This is Two byte instruction.
4) ORA r (Logically OR with accumulator)
^
< (A) < (A) r
1) The content of of the accumulator is OR’d with content of register r.
The result is placed in accumulator. The CY and AC flags are cleared.
2) This is Register addressing mode.
3) This is one byte instruction.
For example : ORA B
The content of A are ANDed with the content of B.
If A = FFH = 1111 1111
B = 02H = 0000 0010
ORA B = 1111 1111
FF H
5) ORA M (Logically OR with memory)
^
(A) < (A) ((H) (L))
1) The content of the accumulator is OR’ed with the contents of memory location
whose address is contained in the H and L. The result is placed in accumulator.
The CY and AC flags are cleared.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.
For example : ORA M
6) ORI data (Logically OR Immediate)
^
(A) < (A) (byte 2)
1) The content of accumulator is OR’ed with the second byte of the instruction and
result is placed in accumulator. The CY and AC flags are
2) This is Immediate Addressing mode.
3) This is Two byte instruction.
For example : ORI 05 H
11..
7) XRA r (Exclusive OR with accumulator)
^
(A) < (A) (r)
1) The content of accumulator is exclusive OR’ed with content of register r .
The result is placed in accumulator. The CY and AC flags are cleared.
2) This is Register addressing mode.
3) This is one byte instruction.
For example : XRA B
For example :
The content of A are EX- ORed with the content of B.
If A = FFH = 1111 1111
B = 02H = 0000 0010
ANA B = 1 1 11 1 1 0 1
FD H
8) XRA M (Exclusive OR with memory)
^
(A) < (A) ((H) (L))
1) The content of content of the accumulator is exclusive EX - OR’ed with
memory location whose address is contained in the H and L registers .
The result is placed in accumulator.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.
9) XRI data (Exclusive OR immediate with accumulator)
^
(A) < (A) (byte 2)
1) The content of the accumulator is exclusive OR’ed with second byte of the
instruction. The result is placed in accumulator. The CY and AC flags are reset.
2) This is Immediate Addressing mode.
3) This is Two byte instruction.
For example : XRI 03 H
10) CMP r (Compare Register with accumulator)
(A) - (r)
1) The content of register r is subtracted from the accumulator.
2) The accumulator remain unchanged.
3) This is Register addressing mode.
4) This is one byte instruction.
For Example : CMP B
12..
11) CMP M (Compare Memory with accumulator)
(A) - ((H) (L))
1) The content of memory location whose address is contained in the H and L
registers is subtracted from the accumulator.
2) The accumulator remains unchanged.
3) This is Register Indirect addressing mode.
4) This is one byte instruction.
For Example : CMP M
12) CPI data ( Compare Immediate with accumulator )
( A ) - data
1) The contens of memory location whose address is specified in two byte of the
instruction is subtracted from accumulator.
2)The contents of accumulator remains unchaged.
3) This is Immediate Addressing mode.
4) This is Two byte instruction.
For example : CPI 03 H
13) RLC (Rotate Accumulator Left)
<

<
D7 D 6 D5 D 4 D 3 D 2 D 1 D 0

< D6 D 5 D4 D 3 D 2 D 1 D 0 D 7 <
CY <

D0 < D7
CY < D7
1) The content of accumulator is rotate left one position.
2) The bit D7 is shifted to bit D0 as well as carry flag.
3) Only the CY flag is affected.
4) This is Implied or Implicit addressing mode.
5) This is one byte instruction.
For Example : If A=80 H
A=10000000
Afetr RLC A=00000001
A = 01 H

13..
 14) RRC (Rotate Accumulator Right)
<
D7 D 6 D5 D 4 D 3 D 2 D 1 D 0

<
< D 0 D 7 D 6 D 5 D 4 D 3 D 2 D1
D0
CY <

D7 < D0
CY < D0
1) The content of accumulator is rotate right one position.
2) The lower order bit i.e D0 is shifted to D7 and to carry flag.
3) Only the CY flag is affected.
4) This is Implied or Implicit addressing mode.
5) This is one byte instruction.
For Example : If A=80 H
A=10000000
Afetr RLC A=01000000
A = 40 H
15) RAL (Rotate accumulator left through carry)
<

<
D7 D 6 D5 D 4 D 3 D 2 D 1 D 0
D7 < D6 D 5 D4 D 3 D 2 D 1 D 0 C Y <
CY
<
CY < D7
D0 < CY
1) The content of accumulator is rotate left one position through the CY flag.
2) The higher order bit D7 shifetd to the CY flag and carry flag is shifted to the lower
bit D0.
4) This is Implied or Implicit addressing mode.
5) This is one byte instruction.
For Example : If A=80 H
A=10000000
Afetr RLC A=00000001
A = 01 H

14..
16) RAR (Rotate Accumulator Right through carry)
<
D7 D 6 D5 D 4 D 3 D 2 D 1 D 0

<
< D 7 D6 D 5 D 4 D 3 D 2 D 1
D0 CY

CY <
CY < D0
D7 < CY
1) The content of accumulator is rotate right on position through the CY flag.
2) The lower ordeer bit is shifted to carray flag bit and carry flag bit is shifted to
higher order bit higher order bit.
4) This is Implied or Implicit addressing mode.
5) This is one byte instruction.
For Example : If A=80 H
A=10000000
Afetr RLC A=11000000
A = C0 H
17) CMA (Complement accumulator)
(A) < (A)
1) The content of accumulator is complement (Zero bits become 1, one bits
become 0). No flags are affected.
4) This is Implied or Implicit addressing mode.
5) This is one byte instruction.
For Example : If A=80 H
A=10000000
Afetr RLC A=01111111
A = 7F H
18) CMC (Complement carry)
(cy) < (cy)
1) The carry flag is complemented. No other flags are affected.
4) This is Implied or Implicit addressing mode.
5) This is one byte instruction.
19) STC (Set carry)
(cy) < 1
1) Carry flag is set to 1. No other flags are affected.
4) This is Implied or Implicit addressing mode.
5) This is one byte instruction. 15..
Branch Instructions
1) JMP addr ( Jump uncondinally )
(PC)< addr
1) Control is transferred uncondinally to the memory location whose address is
specified in the instruction.
2) This is Immediate addressing mode.
2) This is 3 byte instruction.
For example : JMP 2000 H
2) Jcondition addr (Conditional jump)
( PC) < addr
Possible instructions are :
i) JNZ addr.......Jump on Net Zero (Z = 0)
ii) JZ addr.......Jump on Zero (Z = 1)
iii) JNC addr.......Jump on No carry (CY = 0)
iv) JC addr.......Jump on carry (CY = 1)
v)JPO addr.......Jump on odd parity (P = 0)
vi) JPE addr.......Jump on Even parity (P = 1)
vii) JP addr.......Jump on plus (S = 0)
viii) JM addr.......Jump on Minus (S = 1)
1) If the condition is satisfied then only the address of memory location specified
in the instruction is loaded in program counter.
2) The addressing mode is immediate adressing mode.
3) This is three byte instruction.
3) CALL addr ( Unconditional subroutine Call)
[(SP) - 1] < (PCH)
[(SP) - 2] < (PCL)
(SP) < (SP) - 2
(PC) < addr
1) CALL instruction is used to call a subroutine unconditionally.
2) Before the control is transferred to the subroutine the address of next instruction
to be executed the main program is stored into the stack.
3) The contents of SP is decremented by 2.
3) The addressing mode is immediate adressing mode.
4) This is three byte instruction.
16..
4) Ccondition addr (Conditional call)
[(SP) - 1] < (PCH)
[(SP) - 2] < (PCL)
(SP) < (SP) - 2
(PC) < addr
i) CC addr Call if carry
ii) CNC addr Call if no carry
iii) CZ addr Call if zero
iv) CNZ addr Call if no zero
v) CP addr Call if plus
vi) CM addr Call if minus
vii) CPO addr Call if odd parity
viii) CPE addr Call if even parity
5) RET (Return from subroutine)
(PCL)< [(SP)];
(PCH)< [(SP) + 1];
(SP) < (SP)+2
1) The content of memory location whose address is specified register SP are moved
to the lower order eight bite of register PC.
2) The content of memory location whose address is one more than contents register
SP is moved to the high order byte of program counter.
3) The content of register SP is incremented by 2.
4) This is register addressing mode.
5) This is one byte instruction.
6) Rcondition (Conditional return)
(PCL) < [(SP)]
(PCH) < [(SP) + 1]
(SP) < (SP)+2
1) If the specified condition is true, the action specified in RET are performed
otherwise control continues sequentially.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.

17..
 i) RC Return on carry ii) RNC Return on no carry
iii) RP Rturn on positive iv) RM Return on minus
v) RPE Return on even parity vi) RPO Return on odd parity
vii) RZ Return on zero viii) RNZ Return on no zero
7) RST n (Restart)
[(SP) - 1] < (PCH)
[(SP) - 2] < (PCL)
(SP) < (SP) - 2
(PC) < 8* (n)
1) Control is transferred to the instruction whose address is 8 times the content of n.
These instruction are used with interrupts.
2) This is Register Indirect addressing mode.
3) This is one byte instruction.
8) PCHL ( Load program counter with HL)
(PCH) < (H)
(PCL) < (L)
1) The content of register H is moved to the high order byte program counter.
2) The content of register L is moved to the low order byte program counter.
3) This is register addressing mode.
4) This is one byte instruction.

Machine Control Instructions

A) Stack Operation
1) PUSH rp (Push register pair on stack)
[(SP) - 1] < (rh)
[(SP) - 2] < (rl)
(SP) < (SP) - 2
1) The content of the higher order register of register pair rp is moved to memory
location whose address is one less than the content of register SP.
2) The content of the low order register of register pair rp is moved to memory
location whose address is two less than the content of register SP.
The content of SP is decremented by two.
3) This is Register indirect addressing mode.
4) This is one byte instruction.
For example : PUSH B 18..
 2) PUSH PSW (Push accumulator and flag register on stack)
[(SP) - 1] < (A)
[(SP) - 2]0 < (cy), [(SP) - 2]1 < x
[(SP) - 2]2 < (P), [(SP) - 2]3 < x
[(SP) - 2]4 < (AC), [(SP) - 2]5 < x
[(SP) - 2]6 < (z), [(SP) - 2]7 < (S)
(SP) < (SP) -2 x : undefined
1) The content of accumulator are moved to the memory location whose address
is one less than the contents of stack pointer.
2) The contents of processor status word are moved to the memory location
whose address is two less than the contents of stacj pointer.
3) The stack pointer is decremented by two.
4) This is Register indirect addressing mode.
5) This is one byte instruction.
3) POP rp ( Pop of stack to register pair)
[ rl ] < [ SP ]
[ rh ] < [ SP ] + 1
[ SP ] < [ SP ] + 2
1) The contents of memory location whose address is specified by the stack pointer
are moved to lower order register of register pair rp.
2) The contents of memory location whose address is one more than the contents of
stack pointer are moved to higher order register of register pair rp.
3) The stack pointer is incremented by two.
4) This is Register indirect addressing mode.
5) This is one byte instruction.
For example : POP B
4) POP PSW (POP of stack to accumulator and flag register )
(CY) < [(SP)]0
(P) < [(SP)]2 (AC) < [(SP)]4
(Z) < [(SP)]6 (S) < [(SP)]7
(A) < [(SP) + 1] (SP) < (SP) + 2

19..
 1) The content of memory location whose address is specified by the content of
register SP are used to the restore the condition flags.
2) The content of memory location whose address is one more than SP is moved to
accumulator.
3) The content of SP are incremented by 2.
4) This is Register indirect addressing mode.
5) This is one byte instruction.
5) XTHL (Exchange stack top with and l)
(L) < > [(SP)]
(H) < > [(SP) +1)
1) The content of the L register is exchanged with the content of memory location
whose address is stored in stack pointer.
2) The content of H register is exchanged with the content of memory location
whose address is one more than the content of register SP.
3) This is Register indirect addressing mode.
4) This is one byte instruction.
6) SPHL (Move HL to SP)
(SPL) < (L)
(SPH) < (H)
1) The content of register L is cpoied to lower order byte of stack pointer and the
contents of register H into hogher order byte of stack pointer.
2) The contents of H and L are not affected.
3) This is Register addressing mode.
4) This is one byte instruction.
B) Other instruction (I/O)
7) IN port (Input 8 bit data from an input port to accumulator)
(A) < (data)
1) The data placed on the eight bit bidirectional data bus by the specified port is
moved to register A.
2) This is direct addressing mode.
3) This is two byte instruction.
For example : IN 10 H

20..
8) OUT port (Output)
(data) < (A)
1) The content of register A is placed on the eight bit bidirectional data bus is
transfer to the specified port.
2) This is direct addressing mode.
3) This is two byte instruction.
For example : OUT 11 H
9) EI (Enable Interrupt)
1) The interrupt system is enable following the execution of the next instruction
to EI and all interrupts are enable.
2)This is one byte instruction.
10) DI (Disable Interrupts)
1) As soon as DI instruction is executed , the interrupt system is disabled.
2)This is one byte instruction.
11) HLT (Halt)
1) The processor is stopped.
2) The registers and flags are unaffected.
3) This is used to stop MPU. It is waiting for peripheral device to finish its task and
interrupt the processor.
4) This is one byte instruction.
12) NOP (NO Operation)
1) NO operation is performed.
2) The registers and flags are unaffected.
3) This instruction is useful as a time delay in timing loop.
4) This is one byte instruction.
13) RIM ( Read Interrupt Mask)
1) This is a multipurpose instrucion used to read the status of interrupts 7.5 , 6.5 , 5.5
and read serial data input bit. The instrution loads eight bits in the accumulator.
2) This is one byte instruction.
14) SIM ( Set Interrupt Mask)
1) This is a multipurpose instrucion used to implement the 8085 interrupts 7.5 , 6.5 ,
5.5 and serial data output.
2) This is one byte instruction.

21..
Problems :
An accumulator conteins DF H data and register C contains 67 H data.
What will be the contents of acumulator after execution of following
instructions.
1) ADD C 2) ADI 15 H 3) SUB C 4) SUI 24 H
5) ANA C 6) ANI 85 H 7) ORA C 8) ORI 88 H
9) XRA C 10) XRI FD H 11) CMA 12) CMP C
13) RLC 14) RRC 15) RAL 16) RAR
17) SUB A 18) INR C 19) DCR C

1) ADD C
A = DF H = 11011111
C= 67 H = 01100111
Discard < 1 01000110
4 6
ADD C = 46 H

2) ADI 15 H
A = DF H = 11011111
15 H = 00010101
11110100
F 4
ADI 15 H = F4 H

3) SUB C
A = DF H = 11011111
C= 67 H = 01100111
01111000
7 8
SUB C = 78 H

22..
4) SUI 24 H
A = DF H = 11011111
24 H = 00100100
10111011
B B
SUI 24 H = BB H

5) ANA C
A = DF H = 11011111
C= 67 H = 01100111
01000111
4 7
ANA C = 47 H

6) ANI 85 H
A = DF H = 11011111
85 H = 10000101
10000101
8 5
ANI 85 H = 85 H

7) ORA C
A = DF H = 11011111
C= 67 H = 01100111
11111111
F F
ORA C = FF H

8) ORI 88 H
A = DF H = 11011111
88 H = 10001000
11011111
D F
ORI 88 H = DF H
23..
9) XRA C
A = DF H = 11011111
C= 67 H = 01100111
10111000
B 8
XRA C = B8H

10) XRI FD H
A = DF H = 11011111
FD H = 11111101
00100010
2 2
XRI FD H = 22 H

11) CMA
A = DF H = 11011111
00100000
2 0
CMA = 20 H

12) CMP C
A = DF H = 11011111
CMP C = DF H
Accumulator ramains unchanged.

13) RLC
A = DF H = 11011111
10111111
B F
RLC = BF H

24..
14) RRC
A = DF H = 11011111
11101111
E F
RRC = EF H
15) RAL
A = DF H = 11011111
10111111
B F
RAL = BF H

16) RAR
A = DF H = 11011111
11101111
E F
RAR = EF H
17) SUB A
A = DF H = 11011111
11011111
00000000
0 0
SUB A = 00 H
18) INR C
A = DF H = 11011111
1
11100000
E 0
INR C = E0 H
19) DCR C
A = DF H = 11011111
1
11011110
D E
DCR C = DE H
25..
Q. 1 : Select correct alternative and rewrite the following.
1) Zero flag is not affected in ____ instruction.
a) XRA A b) SUB A c) CMP A d) MVI A,00 H
Ans : d) MVI A,00 H
2) LXI H,addr is _____ byte instruction.
a) 1 b) 2 c) 3 d) None of these
Ans : c) 3
3) _____ is not an example of logical operation of 8085 microprocessor.
a) Rotate b) Complement c) Increment d) Compare
Ans : c) Increment
4) The instruction MOV M,C has _______addressing mode.
a) register b) direct c) register indirect d) implicit
Ans : c) register indirect
5) The length of instruction MVI reg. data is _______.
a) 1 byte b) 2 byte c) 3 byte d) 4 byte
Ans : b) 2 byte
6) The first byte of an 8085 instruction always contains_______
a) Opcode b) Data c) Address d) None of these
Ans : a) Opcode
7) _______instruction is a arithematic group of instruction.
a) MOV reg. reg. b) RRC c) NOP d) Add reg.
Ans : d) Add reg.
8) The instructin PCHL belongs to ______group.
a) Data transfer b) Logical c) Arithematic d) Branching
Ans : d) Branching
9) _____ is 3 byte instructin of 8085.
a) CMA b) ADI c) XCHG d) LDA
Ans : d) LDA
10) ANA r instruction comes under ______group.
a) Arithematic b) Logical c) Branch d) Data Transfer
Ans : b) Logical
11) In MOV A, M instruction _______is used to point the memory location.
a) HL b) PC c) SP d) PSW
Ans : a) HL
26..
12) ________ instructin does not affect the flag.
a) RAR b) CMP C c) XRA d) MOV A, B
Ans : d) MOV A, B
13) ______ flag is affected in CMA instruction.
a) All b) No c) Carry d) Zero
Ans : b) No
14) ______ flag is always reset in ANA instruiction.
a) Carry b) Parity c) Sign d) Zero
Ans : a) Carry
15) The instruction JNZ of 8085 microprocessor is ______ type of instruction.
a) Branching b) Conditional Branching
c) Arithematic d) Data transfer
Ans : b) Conditional Branching
16) During PUSH instruction of 8085 , the stack pointer _______
a) Incremented by 1 b) Incremented by 2
c) Decremented by 1 d) Decremented by 2
Ans : d) Decremented by 2
17) In case of 8085 instructions STC is an example of _________addressing mode.
a) Direct b) Register c) Implied d) Immediate
Ans : c) Implied
18) XCHG instruction exchanges 16 bit data between_________
a) DE and HL register pair b) BC and HL register pair
c) BC and DE register pair d) All of the above register pair
Ans : a) DE and HL register pair
19) The instruction _____ will affect the zero flag without changing the contents of the
accumulator.
a) MVI A,00 H b) SUB A c) XRA A d) CMP A
Ans : d) CMP A
20) Insruction uses flags
a) Datra transfer b) Arithematic c) Conditional jump d) Logical
Ans : c) Conditional jump
21) The full form of DAA is ______
a) Double add accumulator b) Decimal add accumulator
c) Double adjust accumulator d) Decimal Adjust accumulator
Ans : d) Decimal Adjust accumulator 27..
22) The instruction which affects only carry flag is ______
a) OR b) XRI c) ADI d) DAD
Ans : d) DAD
23) The instruction ________ will affect the zero flag without changing the contents of the
accumulator.
a) MVI A, 00 H b) SUB A c) XRA A d) CMP A
Ans : d) CMP A
24) PSW is acombination of ________ registers.
a) M ans F b) H and F c) L and F d) A and F
Ans : d) A and F
25) _______ instruction rotates the contents of ACC left through carry by 1 bit
a) RLC b) RRC c) RAR d) RAL
Ans : d) RAL
26) There is no branch instruction based upon the _____ flag.
a) CY b) S c) AC d) P
Ans : c) AC
27) In 8085 microprocessor flag register is not affected after the execution of _____ instruction.
a) INR r b) DCR r c) ADD r d) INX rp
Ans : d) INX rp
28) AC contents remain unchanged on execution of instruction _____.
a) LDAX rp b) MOV A,M c) CMA d) CMP B
Ans : d) CMP B
30) ______ instructin is used for 16 bit addition.
a) ADD b) ADI c) ADC d) DAD
Ans: d) DAD
31) After the execution of POP rp instruction , SP gets _____
a) Incremented by 1 b) Decremented by 1
c) Incremented by 2 d) DEcremented by 2
Ans : c) Incremented by 2
32) The instruction that can affect the stack pointer is _____
a) SHLD b) XCHG c) LXI d) LDAX
Ans : c) LXI
33) ____ of the following instruction is branching instruction.
a) ADD r b) JMP addr c) CMP M d) CMA
Ans : b) JMP addr 28..