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COURSE CODE: CPP 110

COURSE DESCRIPTION: INTRODUCTION TO HDL

COURSE INTENDED On the completion of the course, student is expected to be able to do the
LEARNING OUTCOMES: following:

1. The ability to code and simulate any digital function in HDL.

2. Understand library modeling, behavioral code and the differences
between them.
3. Understand the differences between simulator algorithms as well
as Logic verification using HDL software tool
4. Learn good coding techniques per current industrial practices

LEARNING MATERIAL FOR 2

WEEK NUMBER:

I. TITLE: Levels of Design Description

II. OBJECTIVES: By the end of this module you should be able to:

1. To know the behavioral modeling of combinational and simple

sequential circuits.
2. To know the behavioral modeling of algorithmic state machines.
3. To know the synthesis of combinational and sequential
descriptions.
III. INTRODUCTION:
The purpose of this module is to introduce what Verilog is. A hardware
description language is a language used to describe a digital system: for
example, a network switch, a microprocessor or a memory or a simple
flip-flop. This just means that, by using a HDL, one can describe any
(digital) hardware at any level.

IV. CONTENTS:

Lesson Coverage:

- Different Levels of Design Abstractions

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DESIGN DESCRIPTIONS

Verilog language has the capability of designing a module in several coding styles. Depending on the needs of a
design, internals of each module can be defined at four level of abstractions. Irrespective of the internal abstraction
level, the module would behave exactly in the similar way to the external environment.

Following are the four different levels of abstraction which can be described by four different coding styles of
Verilog language:

• Behavioral or Algorithmic level

• Dataflow level
• Gate level or Structural level
• Switch level

Levels of Description

• Switch Level:
– layout of the wires, resistors and transistors on an IC chip
– Easiest to synthesize, very difficult to write, not really used

• Gate (Structural) Level:

– logical gates, flip flops and their interconnection
– Very easy to synthesize, a text based schematic entry system

• RTL (dataflow) Level

– The registers and the transfers of vectors of information between registers.
– Most efficiently synthesizable level
– Uses the concept of registers with combinational logic

• Behavioral (algorithmic) Level

– Highest level of abstraction
– Description of algorithm without hardware implementation details
– easiest to write and debug, most difficult to synthesize

Example CODE

//A first digital model in Verilog

module simple;
// Simple Register Transfer Level (RTL) example to demo Verilog.
// The register A is incremented by one. Then first four bits of B is
// set to "not" of the last four bits of A. C is the "and" reduction
// of the last two bits of A. declare registers and flip-flops
reg [0:7] A, B;
reg C;
// The two "initial"s and "always" will run concurrently
initial begin: stop_at
// Will stop the execution after 20 simulation units.
#20 $stop;
end
// These statements done at simulation time 0 (since no #k)
initial begin: Init
// Initialize the register A. The other registers have values of "x"
A = 0;

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// Display a header
$display("Time A B C");
// Prints the values anytime a value of A, B or C changes
$monitor(" %0d %b %b %b", $time, A, B, C);
end
//main_process will loop until simulation is over always begin: main_process
always begin: main_process
#1 A = A + 1; // #1 means do after one unit of simulation time
#1 B[0:3] = ~A[4:7]; // ~ is bitwise "not" operator
#1 C = &A[6:7]; // bitwise "and" reduction of last two bits of A
end
endmodule

CLARIFICATION OF THE CODE ABOVE

In module simple, we declared A and B as 8-bit registers and C a 1-bit register or flip flop.

Inside of the module, the one "always" and two "initial" constructs describe three threads of control, i. e., they
run at the same time or concurrently.

Within the initial construct, statements are executed sequentially much like in C or other traditional imperative
programming languages.

The always construct is the same as the initial construct except that it loops forever as long as the simulation
runs.

The notation #1 means to execute the statement after delay of one unit of simulated time.

Therefore, the thread of control caused by the first initial construct will delay for 20 time units before calling the
system task $stop and stop the simulation.

The $display system task allows the designer to print a message much like printf does in the language C.

Every time unit that one of the listed variables' value changes, the $monitor system task prints a message.

The system function $time returns the current value of simulated time.

OUTPUT of the Above CODE

Time A B C
0 00000000 xxxxxxxx x
1 00000001 xxxxxxxx x
2 00000001 1110xxxx x
3 00000001 1110xxxx 0
4 00000010 1110xxxx 0
5 00000010 1101xxxx 0
7 00000011 1101xxxx 0
8 00000011 1100xxxx 0
9 00000011 1100xxxx 1
10 00000100 1100xxxx 1
11 00000100 1011xxxx 1
12 00000100 1011xxxx 0
13 00000101 1011xxxx 0

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14 00000101 1010xxxx 0
16 00000110 1010xxxx 0
17 00000110 1001xxxx 0
19 00000111 1001xxxx 0
Stop at simulation time 20

Lexical Conventions

Keywords, e. g., module, are reserved and in all lower-case letters. Verilog is case sensitive. Spaces are
important in that they delimit tokens in the language.

Numbers are specified in the traditional form of a series of digits with or without a sign but also in the following
form: <size><base format><number>

<size>: number of bits (optional)

<base format>: is the single character ' followed by one of the following characters b, d, o and h, which stand
for binary, decimal, octal and hex, respectively.

<number>: contains digits which are legal for the <base format>

Examples:

549 // decimal number

'h 8FF // hex number
'o765 // octal number
4'b11 // 4-bit binary number 0011
3'b10x // 3-bit binary, least significant bit unknown
5'd3 // 5-bit decimal number
-4'b11 // 4-bit two's complement of 0011 or 1101

String: is a sequence of characters enclosed in double quotes. "this is a string"

Operators (some examples:)

▪ Arithmetic: +, - ! ~ * /
▪ Shift: << >> Relational: < <= > >= == != === !==
▪ Logical && ||.

Identifier: Equivalent to variable names: Identifiers can be up to 1024 characters.

Program Structure

A digital system as a set of modules where each module has an interface to other module (connectivity). GOOD
PRACTICE: place one module per file ( not a requirement) , Modules may run concurrently where usually one
top level module which invokes instances of other modules. And usually called a stimulus block.

MODULES

Represent bits of hardware ranging from simple gates to complete systems, e. g., a microprocessor. Can either
be specified behaviorally or structurally (or a combination of the two)

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The structure of a module is the following:

– module <module name> (<port list>);

– <declares>
– <module items>
– Endmodule

<module name>: is an identifier that uniquely names the module.

<port list> is a list of input, inout and output ports which are used to connect to other modules.

<declares> section specifies data objects as registers, memories and wires as wells as procedural constructs
such as functions and tasks.

<module items> may be initial constructs, always constructs, continuous assignments or

instances of modules.

Example :

Behavioral Example: NAND

Here is a behavior specification of a module NAND

// Behavioral Model of a Nand gate

// By Dan Hyde, August 9, 1995
module NAND(in1, in2, out);
input in1, in2;
output out;
// continuous assign statement
assign out = ~(in1 & in2);
endmodule

Explanation of the above code:

• The ports in1, in2 and out are labels on wires.

• The continuous assignment assign continuously watches for changes to variables in its right hand side
and whenever that happens the right hand side is re-evaluated and the result immediately propagated to
the left hand side (out).

• The continuous assignment statement is used to model combinational circuits where the outputs change
when one wiggles the input.

• Here is a structural specification of a module AND obtained by connecting the output of one NAND to
both inputs of another one.

Structural Example: AND

module AND(in1, in2, out);

// Structural model of AND gate from two NANDS
input in1, in2;
output out;
wire w1;

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// two instances of the module NAND

NAND NAND1(in1, in2, w1);
NAND NAND2(w1, w1, out);

Endmodule

This module has two instances of the NAND module called NAND1 and NAND2 connected together by an
internal wire w1.

Ports

Ports in Verilog Module

Port_list is a vital component of verilog module. Ports provide a way for a module to speak with the external
world through input and output. Every port within the port list must be declared as input, output or inout.

All ports declared together of the above is assumed to be a wire by default, to declare it otherwise it's necessary
to declare it again. as an example within the D-type flip flop we wish the output to carry on to its value until the
following clock edge so it's to be a register.

module d_ff(q,d,reset,clock); // all ports must be declared as input or output

output q;
input d, reset, clock;
reg q; // the ports can be declared again as required

.......

endmodule

Note: by convention, outputs of the module are always first in the port list. This convention is also used in the
predefined modules in Verilog.

A different way ports can be declared as below other than the above one:

module d_ff(
output reg q,
input d,reset,clock);

.......

endmodule

Different Coding Styles of Verilog Language

The order of abstraction mentioned above are from highest to lowest level of abstraction. The top three would
be explained using a 4:1 mux.

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Behavioral or Algorithmic level

This is the highest level of abstraction provided by Verilog HDL.

A module can be implemented in terms of the desired design
algorithm without concern for the hardware implementation details.

It specifies the circuit in terms of its expected behavior.

It is the closest to a natural language description of the circuit
functionality, but also the most difficult to synthesize.

https://www.researchgate.net/figure/MUX-graphical-symbol-a-truth-table-b_fig1_257799438

http://www.vlsifacts.com/wp-content/uploads/2016/01/Mux-behavioral.png
Verilog Code
module Mux_4to1(
input [3:0] i,
input [1:0] s,
output reg o
);

always @(s or i)
begin
case (s)
2'b00 : o = i[0];
2'b01 : o = i[1];
2'b10 : o = i[2];
2'b11 : o = i[3];
default : o = 1'bx;
endcase
end
endmodule

• The output port is declared as data type “reg”.

• Combination of “always” block and “case” procedural statement is used to implement the multiplexer.
• All inputs are added as part of the sensitivity list.
• Select signal “s” is used as condition here.
• Based on value of select signal “s”, any one of the input signal will be selected.

Here we are implementing the functionality of multiplexer at higher-level of abstraction without looking into
internal details of the design as in “Structural Modeling”

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Dataflow level

At this level, the module is designed by specifying the data

flow. Looking towards this design, one can realize how data
flows between hardware registers and how the data is
processed in the design.

This style is similar to logical equations. The specification is

comprised of expressions made up of input signals and
assigned to outputs. In most cases, such an approach can be
quite easily translated into a structure and then implemented.

http://www.vlsifacts.com/wp-content/uploads/2016/01/Mux-dataflow.png

Verilog Code

module Mux_4to1_df(
input [3:0] i,
input [1:0] s,
output o
);

assign o = (~s[1] & ~s[0] & i[0]) | (~s[1] & s[0] & i[1]) | (s[1] & ~s[0] & i[2]) | (s[1] & s[0] & i[3]);
endmodule

In this approach “assign” statement is used.

• Assign statement is a continuous statement where in any changes in signals on right hand side will
update the output signal.

• Any changes in the input signals will execute the assign statement and the updated value will be
reflected on the output “o”.

• Changes in the inputs are continuously monitored.

Gate level or Structural level

The module is implemented in terms of logic gates and interconnections between these gates.

It resembles a schematic drawing with components

connected with signals.

A change in the value of any input signal of a

component activates the component. If two or more
components are activated concurrently, they will
perform their actions concurrently as well.

http://www.vlsifacts.com/wp-content/uploads/2016/01/Mux-structural.png

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A structural system representation is closer to the physical implementation than behavioral one but it is more
involved because of large number of details.

Since logic gate is most popular component, Verilog has a predefined set of logic gates known as primitives.

Any digital circuit can be built from these primitives.

Verilog Code

module Mux_4to1_gate(
input [3:0] i,
input [1:0] s,
output o
);

wire NS0, NS1;

wire Y0, Y1, Y2, Y3;
not N1(NS0, s[0]);
not N2(NS1, s[1]);
and A1(Y0, i[0], NS1, NS0);
and A2(Y1, i[1], NS1, s[0]);
and A3(Y2, i[2], s[1], NS0);
and A4(Y3, i[3], s[1], s[0]);
or O1(o, Y0, Y1, Y2, Y3);
endmodule

• In this approach, the multiplexer is represented in gate-level representation. It consists of ‘4’ AND gates,
‘2’ NOT gates and ‘1’ OR gate. Intermediate signals “NS1”, “NS0”, “Y3”, “Y2”, “Y1”, and “Y0” are
declared as wires.

• In this AND, OR and NOT gates are basic Verilog inbuilt primitives.

• These primitives are instantiated and connected in such a way, to get the functionality of multiplexer.

• This type of modeling of multiplexer is known as “Structural Modeling”.

• In this internal details of the circuit are known to model it.

Switch level

This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of
transistors, switches, storage nodes, and the interconnections between them.

In Verilog HDL transistors are known as Switches that can either conduct or open. Design at this level requires
knowledge of switch-level implementation details. Verilog supports design that can be represented in different
modeling levels.

Describing the design at different levels is known as Mixed-level Modeling. Simulating the design consisting of
different modeling levels is known as Mixed-level Simulation.

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Data Types

A driver is a data type which can drive a load. Basically, in a physical circuit, a driver would be anything that
electrons can move through/into.

Driver that can store a value (example: flip-flop). Driver that can not store value, but connects two points
(example: wire). The first type of driver is called a reg in Verilog (short for "register"). The second data type is
called a wire (for... well, "wire"). You can refer to tidbits section to understand it better.

There are lots of other data types - for instance, registers can be signed, unsigned, floating point... as a newbie,
don't worry about them right now.

Examples :

wire and_gate_output; // "and_gate_output" is a wire that only outputs

reg d_flip_flop_output; // "d_flip_flop_output" is a register; it stores and outputs a value
reg [7:0] address_bus; // "address_bus" is a little-endian 8-bit register

Operators

Verilog operators operate on several data types to produce an output , not all Verilog operators are synthesible
(can produce gates) , some operators are similar to those in the C language , remember, you are making gates, not
an algorithm (in most cases)

Arithmetic Operators

There are two types of operators: binary and unary

Binary operators:

Add (+)
Subtract (-)
Multiply (*)
Divide (/)
Power ( ** )
Modulus (%)

//suppose that: a = 4’b0011;

// b = 4’b0100;
// d = 6; e = 4; f = 2;
//then,

a+b //add a and b; evaluates to 4’b0111

b-a //subtract a from b; evaluates to 4’b0001
a*b //multiply a and b; evaluates to 4’b1100
d/e //divide d by e, evaluates to 4’b0001. Truncates fractional part
e ** f //raises e to the power f, evaluates to 4’b1111

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//power operator is most likely not synthesible

If any operand bit has a value” x”, the result of the expression is all” x”. If an operand is not fully known the
result cannot be either

Modulus operator yields the remainder from division of two numbers. It works like the modulus operator in C

Modulus is synthesible

3 % 2; //evaluates to 1
16 % 4; //evaluates to 0
-7 % 2; //evaluates to -1, takes sign of first operand
7 % -2; //evaluates to 1, takes sign of first operand

Unary operators

Operators ”+” and ”-” can act as unary operators , and they indicate the sign of an operand i.e.,

-4 // negative four
+5 // positive five

!!! Negative numbers are represented as 2’s compliment numbers!!!

!!! Use negative numbers only as type integer or real!!!

!!! Avoid the use of <sss>’<base><number >in expressions!!!

!!! These are converted to unsigned 2’s compliment numbers!!!

!!! This yields unexpected results in simulation and synthesis!!!

The logic gate realization depends on several variables

• coding style
• synthesis tool used
• synthesis constraints (more later on this)

So, when we say ”+”, is it a...

• ripple-carry adder
• look-ahead-carry adder (how many bits of lookahead to be used?)
• carry-save adder

When writing RTL code, keep in mind what will eventually be needed continually thinking about structure,
timing, size, power.

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Logical Operators

Verilog Logical Operators

• logical-and(&&) //binary operator

• logical-or(||) //binary operator
• logical-not(!) //unary operator

//suppose that: a = 3 and b = 0, then...

(a && b) //evaluates to zero
(b || a) //evaluates to one
(!a) //evaluates to 0
(!b) //evaluates to 1
//with unknowns: a = 2’b0x; b = 2’b10;
(a && b) // evaluates to x
//with expressions...
(a == 2) && (b == 3) //evaluates to 1 only if both comparisons are true

Logical operators evaluate to a 1 bit value

• 0 (false), 1 (true), or x (ambiguous)

Operands not equal to zero are equivalent to one. Logical operators take variables or expressions as operators.

greater-than (>)
less-than (<)
greater-than-or-equal-to (>=)
less-than-or-equal-to (<=)

Relational operators return logical 1 if expression is true, 0 if false

//let a = 4, b = 3, and...
//x = 4’b1010, y = 4’b1101, z = 4’b1xxx

a <= b //evaluates to logical zero

a>b //evaluates to logical one
y >= x //evaluates to logical 1
y<z //evaluates to x

!!! Note: These are expensive and slow operators at gate level !!!

Equality Operators - ”LT” is big and slow

//8-bit less than detector if a is less than b, output is logic one

module less8(
input [7:0] a,b,
output z
);

assign z = (a < b) ? 1’b1 : 1’b0;

endmodule

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Equality Operators

• logical equality (== )

• logical inequality (!= )
• logical case equality (===)
• logical case inequality (!==)

Equality operators return logical 1 if expression is true, else 0 . Operands are compared bit by bit , zero filling is
done if operands are of unequal length (Warning!)
Logical case inequality allows for checking of x and z values, checking for X and Z is most definitely non-
synthesible! .

//let a = 4, b = 3, and...
//x = 4’b1010, y = 4’b1101,
//z = 4’b1xxz, m = 4’b1xxz, n = 4’b1xxx

a == b //evaluates to logical 0
x != y //evaluates to logical 1
x == z //evaluates to x
z === m //evaluates to logical 1
z === n //evaluates to logical 0
m !== n //evaluates to logical 1

Bitwise Operators

• negation (∼), and(&), or(|), xor(^), xnor(^- , -^)

• Perform bit-by-bit operation on two operands (except ∼)
• Mismatched length operands are zero extended
• x and z treated the same

bitwise AND bitwise OR bitwise XOR bitwise XNOR

01x 01x 01 x 01x
0000 001x 001x 010x
101x 1111 110x 101x
x0xx xx1x xxxx xxxx

bitwise negation result

0 1
1 0
x x

Logical operators result in logical 1, 0 or x

Bitwise operators results in a bit-by-bit value

//let x = 4’b1010, y = 4’b0000

x|y //bitwise OR, result is 4’b1010

x || y //logical OR, result is 1

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Reduction Operators

And ( & ),
Nand ( ∼& ),
Or ( | ),
Nor ( ∼| ) xor ( ^ ),
Xnor ( ^∼,∼^ )

• Operates on only one operand

• Performs a bitwise operation on all bits of the operand
• Returns a 1-bit result
• Works from right to left, bit by bit

//let x = 4’b1010

&x //equivalent to 1 & 0 & 1 & 0. Results in 1’b0

|x //equivalent to 1 | 0 | 1 | 0. Results in 1’b1
^x //equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1’b0

A good example of the XOR operator is generation of parity

Shift Operators

• right shift (>>)

• left shift (<<)
• arithmetic right shift (>>>)
• arithmetic left shift (<<<)

Shift operator shifts a vector operand left or right by a specified number of bits, filling vacant bit positions with
zeros. Shifts do not wrap around.

Arithmetic shift uses context to determine the fill bits.

// let x = 4’b1100

y = x >> 1; // y is 4’b0110
y = x << 1; // y is 4’b1000
y = x << 2; // y is 4’b0000

Arithmetic Shift Operators

arithmetic right shift (>>>)

Shift right specified number of bits, fill with value of sign bit if expression is signed, otherwise fill with zero.

arithmetic left shift (<<<)

Shift left specified number of bits, filling with zero.

Concatenation Operator {,}

• Provides a way to append busses or wires to make busses

• The operands must be sized

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• Expressed as operands in braces separated by commas

//let a = 1’b1, b = 2’b00, c = 2’b10, d = 3’b110

y = {b, c} // y is then 4’b0010
y = {a, b, c, d, 3’b001} // y is then 11’b10010110001
y = {a, b[0], c[1]} // y is then 3’b101

Replication Operator { { } }

• Repetitive concatenation of the same number

• Operands are number of repetitions, and the bus or wire

//let a = 1’b1, b = 2’b00, c = 2’b10, d = 3’b110

y = { 4{a} } // y = 4’b1111
y = { 4{a}, 2{b} } // y = 8’b11110000
y = { 4{a}, 2{b}, c } // y = 8’b1111000010

Conditional Operator ?:

Operates like the C statement

conditional expression ? true expression : false expression ;

The conditional expression is first evaluated

If the result is true, true expression is evaluated

If the result is false, false expression is evaluated
If the result is x:

both true and false expressions are evaluated,...

their results compared bit by bit,...
returns a value of x if bits differ, OR...
the value of the bits if they are the same.

This is an ideal way to model a multiplexer or tri-state buffer.

More Lexical Conventions

• The ”assign” statement places a value (a binding) on a wire
• Also known as a continuous assign
• A simple way to build combinatorial logic
• Confusing for complex functions
• Must be used outside a procedural statement (always)

//two input mux, output is z, inputs in1, in2, sel

assign z = (a | b);
assign a = in1 & sel;
assign b = in2 & ~sel;

Some More Lexical Conventions

• The order of execution of the assign statements is unknown

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• We must fake parallel execution... gates operate in parallel

• The assign statements ”fire” when the RHS variables change
• RHS = a, b, in1, in2, sel
• The values of a, b, and z are updated at the end of the timestep
• In the next time step if variables changed the next result is posted
• This repeats until no further changes occur
• Then...... time advances

//two input mux, output is z, inputs in1, in2, sel

assign z = (a | b);
assign a = in1 & sel;
assign b = in2 & ~sel;

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V. REFERENCES: Roth, C.H. Jr. And John, L. K. (2018). Digital Systems Design Using VHDL (3rd
ed.). Texas, USA: Cengage Unlimited

Brown, S. and Vranesic, Z. (2009). Fundamentals of Digital Logic with VHDL

Design. (3rd ed.). New York, NY: McGraw-Hill

Online Readings and Guide

Hardware Description Language | VLSI Tutorial | Mepits

VHDL || Electronics Tutorial (electronics-tutorial.net)

Index of /ece232/pdf (umass.edu)

VI. ASSESSMENT TASK:

See Attached file given by the instructor

LECTURE NOTES COMPILATION Page 17 of 17

1st Semester A.Y. 2022-2023