Testability of VLSI

Lecture 4: Logic Simulation

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Simulation for Design Verification

True-value means that the simulator will compute the response for given input stimuli without
injecting any faults in the design. The input stimuli are also based on the specification.
A frequently used strategy is to exercise all functions with only critical data patterns. This is
because the simulation of the exhaustive set of data patterns can be too expensive
8/13/2023 2

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Simulation for Design Verification

1. Why learn Design verification now?

2. Many concepts of verification like event driven simulation etc. representation of

unknown as X etc. is used in Fault simulation algorithms also.

8/13/2023 3

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 True Value Simulation

1. A design can be first simulated at a higher behavior level (such as C).

Netlist not required
Does not contain the detailed timing information.
No electrical behavior
2, Once this design is verified, higher-level blocks are replaced by logic-level netlists.
At this point, a logic simulator is used for verification.
3. The process may be repeated by replacing some or all portions by transistor-level or
circuit-level implementations.

Simulation is used in this way for verifying very large electronic systems.

The weakness of this method is its dependence on the designer’s heuristics used
in generating the input stimuli.

8/13/2023 4

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder. How Many Test vectors Required?

The first seven vectors

cover all stuck-at faults.
One may, therefore, use
only the first seven vectors
in the manufacturing test.

Note: This optimization is possible because of same blocks (FA) being used
8/13/2023
and each test vector verifying similar faults in all blocks 5

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Simulation for Design Verification
Logic design of a 32-bit ripple-carry adder.

Timing analysis of 2 followed by 6 or 3 followed by 7 where carry propagates through the

chain . Only Possible for Modular Structure

8/13/2023 6

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Fault simulation for test generation

8/13/2023 7

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Circuits for Simulation
1. Function or Behaviour Level

8/13/2023 8

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Circuits for Simulation
2. Logic Level

Gate Level Modelling

module Simple_circuit (input A, input B, input C,

output x, output y);
wire w1;

and g1 (w1,A,B); // and gate instance

not g2 (y,C);
or g3 (x,w1,y);

endmodule
8/13/2023 9

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Circuits for Simulation
3. Switch Level MOS transistors, which are treated as ideal switches

8/13/2023 10

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Circuits for Simulation
4. Circuit Level

This is the lowest level and represents the ultimate in accuracy for the simulation of
electronic systems. The circuit is assumed to be composed of electrical elements such
as resistors, capacitors, inductors, and transistors. Equations relating branch or loop
currents and node voltages are developed and solved by numerical methods

8/13/2023 11

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Circuits for Simulation
5. Timing Level That is, the connectivity of transistors, their sizes and types, and node
capacitances are needed. In addition, technology data specifying the
transistor voltage-current characteristics are also used to compute
charging or discharging currents for the nodes.

Transistor level Modelling

8/13/2023 12

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Why Circuit Level Modeling Is Important

If both control inputs are turned on, If both control inputs are turned on, as,
Results in High Currents the 1 input will dominate.

8/13/2023 13

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Signal States

8/13/2023 14

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -1

Z = ABCD

module Sample (
input A, B, C, D,
output Z,
inout w1, w2, w3 );
and g1(w1,A,B);
and g2 (w2, C,D);
and g3 (Z,w1,w3);
endmodule

15

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -1

Z = ABCD

initial begin
A = 0;
B = 0;
C = 0;
D = 0;
#10;
A = 1;
B = 1;
C = 1;
D = 1;
#10;
$finish;
end
16

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -1

Z = ABCD

X (in red) stands for Forcing Unknown. 17

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -2

Z = AB+CD

module Sample (
input A, B, C, D,
output Z,
inout w1, w2, w3 );
and g1(w1,A,B);
and g2 (w2, C,D);
or g3 (Z,w1,w3);
endmodule

18

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -2

Z = AB+CD

initial begin
A = 0;
B = 0;
C = 0;
D = 0;
#10;
A = 1;
B = 1;
C = 1;
D = 1;
#10;
$finish;
end
19

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -2
Z = AB+CD

How is the Simulation tool identifying State X ??

20

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -3

module mux_2_1(
input sel,
input i0, i1,
output y);
assign y = sel ? i1 : i0;
endmodule

21

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -4

module tristate_buffer(
input x,
input enable,
output y);
assign y = enable? x : 'bz;
endmodule

22

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Example -4

module Mux_using_buffer
(input x1,x2,s1,s2,
output y);
tristate_buffer g1 (x1,s1,y);
tristate_buffer g2 (x2,s2,y);
endmodule

23

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Gates for Z and X inputs

24

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling XOR/NOR Gate

25

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Limitation in Simulation

Simulation

Testing

26

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Design for Testing

27

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Circuits for Simulation

28

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Modeling Circuits for Simulation

1. Zero Delay Model

2. Unit Delay Model
3. Multiple Delay Model
Tr and Tf different for each type of gate
4. Min. Max Delay

Digital circuit simulators tend to either ignore

the fine grain variations (transients) between
those meaningful values or model the
transients

29

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Algorithms for True-Value Simulation

30

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Compiled-Code Simulation

Normally in an HDL such as VHDL or Verilog

1. Circuit Simplification
2. Circuit Levelized
3. Signals are treated as variables in the code
4. For every input vector, the code is repeatedly executed until all variables
have attained steady values
5. Compiled-code simulators are very effective where two-state (0,1)
simulation suffices
6. Timing are not modeled in a compiled-code simulator

31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Compiled-Code Simulation

Circuit Simplification

Video lectures by Professor James Chien-Mo Li

32

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Compiled-Code Simulation
Levelisation

33

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Compiled-Code Simulation
Levelisation

34

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Compiled-Code Simulation
Levelisation
module Full_adder_df (
input a, b, cin, wire q, r, output p, cout, sum);
assign sum = p^cin;
assign p = a^b ;
assign r = a&b ;
assign q = p&cin ;
assign cout = r | q;
endmodule

35

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Compiled-Code Simulation

Compiled-code simulation: convert gates into codes for

evaluation
 Optimization: simplifies logic
 Levelization: sort gates in order (i.e. topological sort of
graph)
 Code generated: 1.high-level, 2.machine, 3.interpreted
☺ Pros
 Simple to implement
 Can speed-up by parallelism
 see parallel simulation
 Cons
 Only cycle-based accuracy, no timing (zero gate delay)
 Need to evaluate whole circuit even only small portion
changed
 see event-driven simulation

36

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Event-driven Simulation

 Zero delay
 Nominal delay Event-driven Faster then CC
 Data structure

It is based on the recognition that any signal change (event) must have
a cause, which is also an event. Thus, an event causes new events, which in turn may
cause more events. An event-driven simulator follows the path of events.
Gates whose inputs now have events are called active and are placed in
an activity list. The simulation proceeds by removing a gate from the activity list
and evaluating it to determine whether its output has an event.

An event-driven simulator only does the

necessary amount of work.
For logic
circuits, in which typically very few signals change at a time, this can result in significant
savings of computing effort. However, the biggest advantage of this technique
is in its ability to simulate any arbitrary delays. This is done by a procedure known
as event scheduling. 37

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Event-driven Simulation

Suppose the circuit is simulated with two consecutive input vectors,

(0,0,0,0) and (0,0,0,1). Since A, B, and C have not changed, it is not necessary to
simulate gates G1 and G2. Since neither G1 nor G2 have been simulated, it is not
necessary to test X1 or X2 for changes. The simulation of G4 can be bypassed without
testing X1 or X2.

38

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Event-driven Simulation

39

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Event-driven Simulation
Zero-delay Event-driven Sim

[2]. Video lectures by Professor James Chien-Mo Li 40

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Event-driven Simulation
Nominal delay

[2]. Video lectures by Professor James Chien-Mo Li 41

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Event-driven Simulation

G3 taken
as 1

G2 taken
as 1
G2 taken
as 0

42

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

Lab. of Dependable Systems Graduate Institute of Electronics Engineering
National Taiwan University
https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-
SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

43

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION