21CS43 MCES Module4
21CS43 MCES Module4
18CS44
MODULE – IV
EMBEDDED SYSTEM COMPONENTS
• Apollo Guidance Computer (AGC) developed (during 1960) by MIT Instrumentation Laboratory
for the lunar expedition is the first recognized modern embedded system.
• The first mass-produced embedded system was the guidance computer, Autonetics D-17, for the
Minuteman-I missile in 1961; built using discrete transistor logic and a hard-disk for main
memory.
• The first microprocessor, the Intel 4004, was designed for calculators and other small systems;
but still required many external memory and support chips.
• First microcontroller, TMS 1000, developed in 1974 by Texas Instruments. It had ROM, RAM,
and clock circuitry on the chip along with the processing chip.
• In 1980, Intel introduced 8051 MCU (multipoint control unit) and called it MCS-51 architecture.
• Laser and Inkjet printers emerged during 1980s; and early 1990, cell phones having five or six
DSPs and CPUs emerged.
o They usually contain a high performance Real Time Operating System (RTOS) for task
scheduling, prioritization, and management.
• Digital CRO, digital multi-meters, and logic analyzers are examples of monitoring embedded
systems.
5. Control
• Sensors and actuators are used for controlling the system.
o Sensors are connected to the input port for capturing the changes in
environmental variable or measuring variable.
o Actuators connected to output port are controlled according to the changes in
input variable.
• Air conditioner system used in our home to control the room temperature to a specified
limit is a typical example for embedded system for control purpose. The air conditioner’s
compressor unit (actuator) is controlled according to the current room temperature
(sensor) and the desired room temperature set by the user.
6. Application Specific User Interface
• These are embedded systems with application-specific user interfaces like buttons,
switches, keypad, lights, bells, display units, etc.
• Mobile phone is an example for this. In mobile phone, the user interface is provided
through the keypad, graphic LCD module, system speaker, vibration alert, etc.
Microprocessors: A Microprocessor is a silicon chip representing a central processing unit (CPU), which
is capable of performing arithmetic as well as logical operations. In general, the CPU contains the
Arithmetic and Logic Unit (ALU), control unit and working registers. A microprocessor is a dependent
unit and it requires the combination of' other hardware like memory, timer unit, and interrupt controller,
etc., for proper functioning.
Microcontrollers: A Microcontroller is a highly integrated chip that contains a CPU, scratch pad RAM,
special and general purpose register arrays, on chip ROM/ FLASH memory for program storage, timer
and interrupt control units and dedicated I/O ports. Microcontrollers can be considered as a super set of
microprocessors.
Digital Signal Processors (DSPs): Digital Signal Processors are powerful special purpose 8/ 16/ 32 bit
microprocessors designed specifically to meet the computational demands and power constraints of
today’s embedded audio, video, and communications applications.
Digital signal processors are 2 to 3 times faster than the general purpose microprocessors in signal
processing applications. This is because of the architectural difference between the two. DSPs implement
A typical digital signal processor incorporates the following four key units:
1. Program Memory: Memory for storing the program required by DSP to process the data.
2. Data Memory: Working memory for storing temporary variables and data/ signal to be processed.
3. Computational Engine: Performs the signal processing in accordance with the stored program
memory.
4. I/O Unit: Acts as an interface between the outside world and DSP. It is responsible for capturing
signals to be processed and delivering the processed signals.
Audio video signal processing, telecommunication and multimedia applications are typical examples
where DSP is employed.
Digital signal processing employs a large amount of real-time calculations. Sum of Products (SOP)
calculation, Convolution, Fast Fourier Transform (FFT), Discrete Fourier Transform (DFT), etc, are some
of the operations performed by digital signal processors.
RISC versus CISC Processors/ Controllers: The term RISC stands for Reduced Instruction Set
Computing. As the name implies, all RISC processors/ controllers possess lesser number of instructions,
typically in the range of 30 to 40.
CISC stands for Complex instruction Set Computing. From the definition itself it is clear that the
instruction set is complex and instructions are high in number.
From a programmers point of view RISC processors are comfortable, since s/ he needs to learn only a few
instructions, whereas for a CISC processor s/ he needs to learn more number of instructions and should
understand the context of usage of each instruction.
Atmel AVR microcontroller is an example for a RISC processor and its instruction set contains only 32
instructions. The original version of 8051 microcontroller (e.g.AT 89C51) is a CISC controller and its
instruction set contains 255 instructions.
Harvard versus Von-Neumann Processor/ Controller Architecture: The terms Harvard and Von-
Neumann refers to the processor architecture design.
The following Figure explains the Harvard and Von-Neumann architecture concept.
Big-Endian versus Little-Endian Processors/ Controllers: Endianness specifies the order in which the
data is stored in the memory by processor operations in a multi-byte system (Processors whose word size
is greater than one byte).
Suppose the word length is two byte; then data can be stored in memory in two different ways:
1. Higher order of data byte at the higher memory and lower order of data byte at location just
below the higher memory – Little-Endian. E.g.: a 4 byte long integer Byte3 Byte2 Bytel Byte0
will be stored in the memory as follows:
2. Lower order of data byte at the higher memory and higher order of data byte at location just
below the higher memory – Big-Endian. E.g.: a 4 byte long integer Byte3 Byte2 Bytel Byte0 will
be stored in the memory as follows:
Load Store Operation and Instruction Pipelining: As mentioned earlier, the RlSC processor instruction
set is orthogonal, meaning it operates on registers. The memory access related operations are performed
by the special instructions load and store. If the operand is specified as memory location, the content of it
is loaded to a register using the load instruction. The instruction store stores data from a specified register
to a specified memory location. The concept of Load Store Architecture is illustrated with the following
example:
Suppose x, y and z are memory locations and we want to add the contents of x and y and store the result in
location z. Under the load store architecture the same is achieved with 4 instructions as shown in
following Figure.
The first instruction load Rl, x loads the register R1 with the content of memory location x, the second
instruction load R2, y loads the register R2 with the content of memory location y. The instruction add R3,
R1, R2 adds the content of register R1 and R2 and store the result in register R3. The next instruction store
R3, z stores the content of register R3 in memory location z.
Depending on the stages involved in an instruction (fetch, read register and decode, execute instruction,
access an operand in data memory, write back the result to register, etc.), there can be multiple levels of
instruction pipelining.
The following Figure illustrates the concept of Instruction pipelining for single stage pipelining.
ASICs can be pre-fabricated for a special application or it can be custom fabricated by using the
components from a re-usable 'building block' library of components for a particular customer application.
ASIC based systems are profitable only for large volume commercial productions. Fabrication of ASICs
requires a non-refundable initial investment (known as Non-Recurring Engineering Charges (NRE), a
one-time expense) for the process technology and configuration expenses.
General Purpose Processor (GPP) versus Application-Specific Instruction Set Processor (ASIP): A
General Purpose Processor or GPP is a processor designed for general computational tasks. The
processor running inside your laptop or desktop (Pentium 4/ AMD Athlon, etc.) is a typical example for
general purpose processor. They are produced in large volumes, and hence, the per unit cost for a chip is
low compared to ASIC or other specific ICs.
A typical general purpose processor contains an Arithmetic and Logic Unit (ALU) and Control Unit
(CU). On the other hand, Application Specific Instruction Set Processors (ASIPs) are processors with
architecture and instruction set optimized to specific-domain/ application requirements, like network
processing, automotive, telecom, media applications, digital signal processing, control applications, etc.
ASIPs incorporate a processor and on-chip peripherals, demanded by the application requirement,
program and data memory.
o On the other hand, Programmable Logic Devices (PLDs) offer customers a wide range of logic
capacity, features, speed, and voltage characteristics; and these devices can be re-configured to
perform any number of functions at any time.
Advantages of PLDs: Programmable logic devices offer a number of advantages over fixed logic devices,
including:
• PLDs offer customers much more flexibility during the design cycle because design iterations are
simply a matter of changing the programming file, and results of design changes can be seen
immediately in working parts.
• PLDs do not require long lead times for prototypes or production parts-the PLDs are already on a
distributor's shelf and ready for shipment.
• PLDs do not require customers to pay for large NRE costs and purchase expensive mask sets-
PLD suppliers incur those costs when they design their programmable devices.
• PLDs allow customers to order just the number of parts they need, when they need them,
allowing them to control inventory.
• PLDs can be reprogrammed even after a piece of equipment is shipped to a customer.
CPLDs and FPGAs: The two major types of programmable logic devices are Field Programmable Gate
Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Of the two, FPGAs offer the
highest amount of logic density, the most features, and the highest performance. The largest FPGA now
shipping part of the Xilinx Virtex™.
CPLDs FPGAs
1. Logic blocks are used for construction of
1. PLD is used for construction of CPLD
FPGA
2. CPLD is non-volatile & less costly 2. FPGA is volatile & costly
3. Delays are much more predictable in CPLDs 3. Prediction of delay is difficult in FPGA
4. Operating speed is low & is suitable for control 4. Operating speed is high & is suitable for
circuit timing circuit
5. FPGA has more flexibility as well as design
5. CPLD has less flexibility and design capacity
capacity
6. FPGA could not work until the configuration
6. CPLD could work immediately after power up
is done
7. CPLDs are considered as ‘coarse-grain’
7. FPGAs are considered as ‘fine-grain’ devices
devices
The code memory retains its contents even after the power to it is turned off. It is generally known as non-
volatile storage memory. Depending on the fabrication, erasing and programming techniques, they are
classified into the following types:
1. Masked Memory (MROM): Masked ROM is a one-time programmable device. Masked ROM
makes use of the hardwired technology storing data. The device is factory programmed by
masking and metallization process at the time of production itself, as per the data provided by the
end user.
o The primary advantage of this is low cost for high volume production. They are the least
expensive type of solid state memory. Different mechanisms are used for the masking
process of the ROM, like
(1) Creation of an enhancement or depletion mode transistor through channel implant.
(2) By creating the memory cell either using a standard transistor or a high threshold
transistor.
o Masked ROM is a good candidate for storing the embedded firmware for low cost
embedded devices. Once the design is proven and the firmware requirements are tested
and frozen, the binary data (The firmware cross compiled/assembled to target processor
specific machine code) corresponding to it can be given to the MROM fabricator.
o The limitation with MROM based firmware storage is the inability to modify the device
firmware against firmware upgrades. Since the MROM is permanent in bit storage, it is
not possible to alter the bit information.
2. Programmable Read Only Memory (PROM)/ One Time Programmable Memory (OTP):
PROM is not pre-programmed by the manufacturer. The end user is responsible for programming
these devices.
o This memory has nichrome or polysilicon wires arranged in a matrix. These wires can be
functionally viewed as fuses. It is programmed by a PROM programmer which
selectively burns the fuses according to the bit pattern to be stored. Fuses which are not
blown/ burned, represents logic "1"; whereas fuses which are blown/ burned represents a
logic "0". The default state is logic "1".
o OTP is widely used for commercial production of embedded systems whose proto-typed
versions are proven and the code is finalized. It is a low cost solution for commercial
production. OTPs cannot be reprogrammed.
o Limitations: OTPs are not useful and worth for development purpose. During the
development phase, the code is subject to continuous changes and using an OTP each
time to load the code is not economical.
3. Erasable Programmable Read Only Memory (EPROM): EPROM gives the flexibility to
reprogram the same chip.
o EPROM stores the bit information by charging the floating gate of an FET. Bit
information is stored by using an EPROM programmer, which applies high voltage to
charge the floating gate.
o EPROM contains a quartz crystal window for erasing the stored information. If the
window is exposed to ultraviolet rays for a fixed duration, the entire memory will be
erased.
o Limitations: Even though the EPROM chip is flexible in terms of re-programmability, it
needs to be taken out of the circuit board and put in a UV eraser device for 20 to 30
minutes. So it is a tedious and time-consuming process.
reprogrammed in-circuit. These chips include a chip erase mode and in this mode they can be
erased in a few milliseconds.
o It provides greater flexibility for system design.
o The only limitation is their capacity is limited (only few kilobytes) when compared with
the standard ROM.
5. FLASH: FLASH is the latest ROM technology and is the most popular ROM technology used in
today's embedded designs. FLASH memory is a variation of EEPROM technology. It combines
the re-programmability of EEPROM and the high capability of standard ROMs.
o FLASH memory is organized as sectors (blocks) or pages. FLASH memory stores
information in an array of floating gate MOSFET transistors. The erasing of memory can
be one at sector level or page level without affecting the other sectors or pages. Each
sector/ page should be erased before re-programming. The typical erasable capacity of
FLASH is 1000 cycles.
6. NVRAM: Non-volatile RAM is a random access memory with battery backup. It contains static
RAM based memory and a minute battery for providing supply to the memory in the absence of
external power supply. The memory and battery are packed together in a single package.
o The life span of NVRAM is expected to be around 10 years. DSJ644 from Maxim/ Dallas
is an example of 32KB NVRAM.
1. Static RAM (SRAM): Static RAM stores data in the form of voltage. They are made up of flip-
flops. Static RAM is the fastest form of RAM available.
o In typical implementation, an SRAM cell (bit) is realized using six transistors (or 6
MOSFETs). Four of the transistors are used for building the latch (flip-flop) part of the
memory cell and two for controlling the access.
o SRAM is fast in operation due to its resistive networking and switching capabilities.
o In simplest representation an SRAM cell can be visualized as shown in the following
Figure:
o This implementation in its simpler form can be visualized as two-cross coupled inverters with
read/ write control through transistors. The four transistors in the middle form the cross-
coupled inverters. This can be visualized as shown in the following Figure:
o From the SRAM implementation diagram, it is clear that access to the memory cell is
controlled by the line Word Line, which controls the access transistors (MOSFETs) Q5 and
Q6. The access transistors control the connection to bit lines B & B\.
o In order to write a value to the memory cell, apply the desired value to the bit control
lines (For writing 1, make B = 1 and B\ =0; For writing 0, make B = 0 and B\ =1) and
assert the Word Line (Make Word line high). This operation latches the bit written in
the flip-flop.
o For reading the content of the memory cell, assert both B and B\ bit lines to 1 and set
the Word line to 1.
o The major limitations of SRAM are low capacity and high cost. Since a minimum of six
transistors are required to build a single memory cell, imagine how many memory cells we
can fabricate on a silicon wafer.
2. Dynamic RAM (DRAM): Dynamic RAM stores data in the form of charge. They are made up of
MOS transistor gates.
o The advantages of DRAM are its high density and low cost compared to SRAM.
o The disadvantage is that, since the information is stored as charge it gets leaked off with
time; and to prevent this, they need to be refreshed periodically. Special circuits called
DRAM controllers are used for the refreshing operation. The refresh operation is done
periodically in milliseconds interval. The following Figure illustrates the typical
implementation of a DRAM cell.
o The MOSFET acts as the gate for the incoming and outgoing data, whereas the capacitor acts as
the bit storage unit.
SRAM Cell DRAM Cell
1. Made up of 6 CMOS transistors (MOSFET) 1. Made up of a MOSFET and a Capacitor
2. Doesn’t require refreshing 2. Requires refreshing
3. More expensive 3. Less expensive
4. Slow in operation due to refresh requirement,
4. Fast in operation, typical access time is 10 ns typical access time is 60 ns; write operation is
faster than read operation
3. NVRAM: Non-volatile RAM is a random access memory with battery backup. It contains static
RAM based memory and a minute battery for providing supply to the memory in the absence of
external power supply. The memory and battery are packed together in a single package.
o The life span of NVRAM is expected to be around 10 years. DSJ644 from Maxim/ Dallas
is an example of 32KB NVRAM.
Memory Shadowing:
Generally the execution of a program or a configuration from a Read Only Memory (ROM) is very slow
(120 to 200 ns) compared to the execution from a random access memory (40 to 70 ns). From the timing
parameters, it is obvious that RAM access is about three times as fast as ROM access.
• The memory requirement for an embedded system in terms of RAM and ROM
(EEPROM/FLASH/NVRAM) is solely dependent on the type of the embedded system and the
applications for which it is designed.
• There is no hard and fast rule for calculating the memory requirements. Lot of factors need to be
considered when selecting the type and size of memory for embedded system.
o For example, if the embedded system is designed using SoC or a microcontroller with on-
chip RAM and ROM (FLASH/EEPROM), depending on the application need the on-chip
memory may be sufficient for designing the total system.
• As a rule of thumb, identify your system requirement and based on the type of processor (SoC or
microcontroller with on-chip memory) used for the design, take a decision on whether the on-chip
memory is sufficient or external memory is required.
▪ Also, the entire memory range supported by the processor/ controller may not be
available to the memory chip alone. It may be shared between I/O, other ICs and
memory.
o Word size of the memory: The word size refers to the number of memory bits that can be
read/write together at a time. 4, 8, 12, 16, 24, 32 etc., are the word sizes supported by
memory chips. Ensure that the word size supported by the memory chip matches with the
data bus width of the processor/ controller.
• FLASH memory is the popular choice for ROM (program storage memory) in embedded
applications. It is a powerful and cost-effective solid-state storage technology for mobile
electronics devices and other consumer applications.
• FLASH memory comes in two major variants, namely, NAND and NOR FLASH.
o NAND FLASH is a high-density low cost non-volatile storage memory; on the other
hand, NOR FLASH is less dense and slightly expensive. But NOR FLASH supports the
Execute in Place (XIP) technique for program execution.
▪ The XIP technology allows the execution of code memory from ROM itself
without the need for copying it to the RAM as in the case of conventional
execution method.
• The EEPROM data storage memory is available as either serial interface or parallel interface
chip. If the processor/ controller of the device supports serial interface and the amount of data to
write and read to and from the device is less, it is better to have a serial EEPR0M chip. The serial
EEPROM saves the address space of the total system. The memory capacity of the serial
EEPROM is usually expressed in bits or Kilobits: 512 bits, 1Kbits, 2Kbits, 4Kbits, etc. are
examples for serial EEPROM memory representation.
If the embedded system is designed for monitoring purpose only, then there is no need for including an
actuator in the system. For example, take the case of an ECG machine. It is designed to monitor the heart
beat status of a patient and it cannot impose a control over the patient's heart beat and its order. The
sensors used here are the different electrode sets connected to the body of the patient. The variations are
captured and presented to the user (may be a doctor) through a visual display or some printed chart.
Sensors Actuators
1. Sensor is an input device 1. Actuator is an output device
2. Convert a physical parameter to an electrical
2. Convert an electrical signal to a physical output
output
3. A device that detects events or changes in the
3. A component of a machine that is responsible
environment and send the information to
for moving and controlling mechanisms
another electronic device
4. Sensor help to monitor the changes in the 4. Actuator helps to control the environment or
environment physical changes
3.9 Light Emitting Diode (LED): LED is an important output device for visual indication in any
embedded system. LED can be used as an indicator for the status of various signals or situations.
• Typical examples are indicating the presence of power conditions like 'Device ON', 'Battery Low'
or 'Charging of Battery' for a battery operated handheld embedded devices.
Light Emitting Diode is a p-n junction diode and it contains an anode and a cathode. For proper
functioning of the LED, the anode of it should be connected to +ve terminal of the supply voltage and
cathode to the –ve terminal of supply voltage. A resister is used in series between the power supply and
the LED to limit the current through the LED. The ideal LED interfacing circuit is shown in the following
Figure.
LEDs can be interfaced to the port pin of a processor/ controller in two ways.
• In the first method, the anode is directly connected to the port pin and the port pin drives the
LED. In this approach, the port pin 'sources' current to the LED when the port pin is at logic High
(Logic '1').
• In the second method, the cathode of the LED is connected to the port pin of processor/ controller
and the anode to the supply voltage through a current limiting resistor. LED is turned on when the
port pin is at logic Low (Logic '0').
3.10 7-Segment LED Display: The 7-segment LED display is an output device used for
displaying alpha- numeric characters. It contains 8 light-emitting diode (LED) segments arranged in a
special form. Out of the 8 LED segments, 7 are used for displaying alpha-numeric characters and 1 is
used for representing ‘decimal point'. The following Figure explains the arrangement of LED segments in
7-segment LED display.
The LED segments are named A to G and the 'decimal point LED segment is named as DP. For
displaying the number 4, the segments F, G, B and C are lit. For displaying 3, the segments A, B, C, D, G
are lit. All these 8 LED segments need to be connected to one port of the processor/ controller for
displaying alpha-numeric digits.
The 7-segment LED displays are available in two different configurations, namely; Common Anode and
Common Cathode.
• In common anode configuration, the anodes of the 8 segments are connected commonly
• In common cathode configuration, the 8 LED segments share a common cathode line.
The following Figure illustrates the Common Anode and Cathode configurations.
Optocoupler: Optocoupler is a solid state device to isolate two parts of a circuit. Optocoupler combines
an LED and a photo-transistor in a single housing (package). The following Figure illustrates the
functioning of an optocoupler device.
In electronic circuits, an optocoupler is used for suppressing interference in data communication, circuit
isolation, high voltage separation, simultaneous separation and signal intensification, etc. Optocouplers
can be used in either input circuits or in output circuits.
Vanishri.V.S ISE DEPT Page 29
Microcontroller and Embedded systems [21CS43]-2023 Module 4
The following Figure illustrates the usage of optocoupler in input circuit and output circuit of an
embedded system with a microcontroller as the system core.
Optocoupler is available as ICs from different semiconductor manufacturers. The MCT2M IC from
Fairchild semiconductor is an example for optocoupler IC.
3.11 Stepper Motor: A stepper motor is an electro-mechanical device which generates discrete
displacement (motion) in response, to de electrical signals. It differs from the normal DC motor in its
operation. The DC motor produces continuous rotation on applying DC voltage, whereas a stepper motor
produces discrete rotation in response to the DC voltage applied to it.
Stepper motors are widely used in industrial embedded applications, consumer electronic products and
robotics control systems. The paper feed mechanism of a printer/ fax makes use of stepper motors for its
functioning.
Based on the coil winding arrangements, a two-phase stepper motor is classified into two. They are:
1. Unipolar: A unipolar stepper motor contains two windings per phase. The direction of rotation
(clockwise or anticlockwise) of a stepper motor is controlled by changing the direction of current
flow. Current in one direction flows through one coil and in the opposite direction flows through
the other coil. It is easy to shift the direction of rotation by just switching the terminals to which
the coils are connected. The following Figure illustrates the working of a two-phase unipolar
stepper motor.
The coils are represented as A, B, C and D. Coils A and C carry current in opposite directions for
phase 1 (only one of them will be carrying current at a time). Similarly, B and D carry current in
opposite directions for phase 2 (only one of them will be carrying current at a time).
2. Bipolar: A bipolar stepper motor contains single winding per phase. For reversing the motor
rotation the current flow through the windings is reversed dynamically. It requires complex
circuitry for current flow reversal.
The stepping of stepper motor can be implemented in different ways by changing the sequence of
activation of the stator windings. The different stepping modes supported by stepper motor are explained
below:
Full Step: In the full step mode both the phases are energized simultaneously. The coils A, B, C and D are
energized in the order, as shown in the following Table.
Wave Step: In the wave step mode, only one phase is energized at a time and each coils of the phase is
energized alternatively. The A, B, C and D are energized in the order, as shown in the following Table.
Full Step Wave Step
Step
Coil A Coil B Coil C Coil D Coil A Coil B Coil C Coil D
1 H H L L H L L L
2 L H H L L H L L
3 L L H H L L H L
4 H L L H L L L H
Half Step: It uses the combination of wave and full step. It has the highest torque and stability. The coil
energizing sequence for half step is given in the Table below.
Step Coil A Coil B Coil C Coil D
1 H L L L
2 H H L L
3 L H L L
4 L H H L
5 L L H L
6 L L H H
7 L L L H
8 H L L H
Two-phase unipolar stepper motors are the popular choice for embedded applications. The current
requirement for stepper motor is little high and hence the port pins of a microcontroller/ processor may
not be able to drive the directly. Also the supply voltage required to operate stepper motor varies normally
in the range 5V to 24V. Depending on the current and voltage requirements, special driving circuits are
required to interface the stepper motor with microcontroller/ processors.
ULN2803 is an octal peripheral driver array available from Texas Instruments and ST microelectronics
for driving a 5V stepper motor. Simple driving circuit can also be built using transistors.
The following circuit diagram illustrates the interfacing of a stepper motor through a driver circuit
connected to the port pins of a microcontroller/ processor.
The Single Pole Single Throw configuration has only one path for information flow. The path is either
open or dosed in normal condition.
• For normally open Single Pole Single Throw relay, the circuit is normally open and it becomes
closed when the relay is energized.
• For normally closed Single Pole Single Throw configuration, the circuit is normally closed and it
becomes open when the relay is energized.
For Single Pole Double Throw Relay, there are two paths for information flow and they are selected by
energizing or de-energizing the relay.
The Relay is normally controlled using a relay driver circuit connected to the port pin of the processor/
controller. A transistor is used for building the relay driver circuit. The following Figure illustrates the
same.
Piezo Buzzer: Piezo buzzer is a piezoelectric device for generating audio indications in embedded
application.
o A piezoelectric buzzer contains a piezoelectric diaphragm which produces audible sound in
response to the voltage applied to it.
Piezoelectric buzzers are available in two types. 'Self- driving' and 'External driving'.
• The 'Self-driving' circuit contains all the necessary components to generate sound at a predefined
tone. It will generate a tone on applying the voltage.
• External driving piezo buzzers supports the generation of different tones. The tone can be varied
by applying a variable pulse train to the piezoelectric buzzer.
A piezo buzzer can be directly interfaced to the port pin of the processor/ control. Depending on the
driving current requirements, the piezo buzzer can also be interfaced using a transistor based driver circuit
as in the case of a 'Relay'.
3.12 Push Button Switch: Push button switch is an input device. Push button switch comes in two
configurations, namely 'Push to Make' and 'Push to Break'.
• In the 'Push to Make' configuration, the switch is normally in the open state and it makes a circuit
contact when it is pushed or pressed.
• In the 'Push to Break' configuration, the switch is normally in the closed state and it breaks the
circuit contact when it is pushed or pressed.
o The push button stays in the 'closed' (for Push to Make type) or 'open' (For Push to Break type)
state as long as it is kept in the pushed state and it breaks/ makes the circuit connection when it is
released.
• Push button is used for generating a momentary pulse. In embedded application push button is
generally used as reset and start switch and pulse generator. The Push button is normally
connected to the port pin of the host processor/ controller.
Depending on the way in which the push button interfaced to the controller, it can generate either a
'HIGH' pulse or a 'LOW' pulse.
The following Figure Illustrates how the push button can be used for generating 'LOW' and 'HIGH'
pulses.
3.13 Keyboard: Keyboard is an input device 'HIGH' Pulse generator for user interfacing.
• If the number of keys required is very limited, push button switches can be used and they can be
directly interfaced to the port pins for reading.
• However, there may be situations demanding a large number of keys for user input (e.g. PDA
device with alpha-numeric keypad for user data entry).
o In such situations it may not be possible to interface each keys to a port pin due to the
limitation in the number of general purpose port pins available for the processor/
controller in use and moreover it is wastage of port pins.
o Matrix keyboard is an optimum solution for handling large key requirement. It greatly
reduces the number of interface connections.
• For example, for interfacing 16 keys, in the direct interfacing technique, 16 port pins are required,
whereas in the matrix keyboard only 8 lines are required. The 16 keys are arranged in a 4 column
x 4 Row matrix. The following Figure illustrates the connection o keys in a matrix keyboard.
Programmable Peripheral Interface (PPI): Programmable Peripheral Interface devices are used for
extending the I/O capabilities of processors/ controllers. Most of the processors/ controllers provide very
limited number of I/O and data ports and at times it may require more number of I/O ports than the one
supported by the controller/ processor.
A programmable peripheral interface device expands the I/O capabilities of the processor/ controller.
8255A is a popular PPI device for 8-bit processors/ controllers.
8255A supports 24 I/O pins, and these I/O pins can be grouped as either three 8-bit parallel ports (Port A,
Port B and Port C) or two 8-bit parallel ports (Port A and Port B) with Port C in any one of the following
configurations:
(1) As 8 individual I/O pins
(2) Two 4-bit ports; namely Port CUPPER (Cu) and Port CLOWER (CL).
This is configured by manipulating the control register of 8255A. The control register holds the
configuration for Port A, Port B and Port C. The bit details of control register is given in the following
Figure:
o The external communication interface can be either a wired medium or a wireless media and it can
be a serial or a. parallel interface.
o Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi), Radio Frequency waves (RF), GPRS/ 3G/
4GLTE, etc. are examples for wireless communication interface.
o RS-232C/ RS-422/ RS-485, USB, Ethernet IEEE 1394 port, Parallel port, CF-II interface, SDIO,
PCMCIA/ PCIex, etc., are examples for wired interfaces.
Inter Integrated Circuit (I2C) Bus: The Inter Integrated Circuit Bus (I2C-Pronounced 'I square C') is a
synchronous bidirectional half duplex (one-directional communication at a given point of time) two wire
serial interface bus.
• The concept of I2C bus was developed by 'Philips Semiconductors' in the early 1980s. The
original intention of I2C was to provide an easy way of connection between a microprocessor/
microcontroller system and the peripheral chips in television sets.
• The I2C bus comprise of two bus lines, namely; Serial Clock-SCL and Serial Data-SDA.
o SCL line is responsible for generating synchronization clock pulses.
o SDA is responsible for transmitting the serial data across devices.
• I2C bus is a shared bus system to which many number of I2C devices can be connected.
• Devices connected to the I2C bus can act as either 'Master' device or 'Slave' device.
o The 'Master' device is responsible for controlling the communication by initiating/
terminating data transfer, sending data and generating necessary synchronization clock
pulses.
o 'Slave' devices wait for the commands from the master and respond upon receiving the
commands.
• 'Master' and 'Slave' devices can act as either transmitter or receiver; regardless whether a master
is acting as transmitter or receiver, the synchronization clock signal is generated by the 'Master'
device only.
• I2C supports multi-masters on the same bus.
• The following Figure shows bus interface diagram, which illustrates the connection of master and
slave devices on the I2C bus.
The address to various I2C devices in an embedded device is assigned and hardwired at the time of
designing the embedded hardware.
The sequence of operations for communicating with an I2C slave device is listed below:
1. The master device pulls the clock line (SCL) of the bus to 'HIGH '
2. The master device pulls the data line (SDA) 'LOW', when the SCL line is at logic 'HIGH' (This is
the 'Start' condition for data transfer)
3. The master device sends the address (7-bit or 10-bit wide) of the 'slave' device to which it wants
to communicate, over the SDA line. Clock pulses are generated at the SCL line for synchronizing
the bit reception by the slave device. The MSB of the data is always transmitted first. The data in
the bus is valid during the 'HIGH' period of the clock signal
4. The master device sends the Read or Write bit (Bit value = 1 Read operation; Bit value = 0 Write
operation) according to the requirement
5. The master device waits for the acknowledgement bit from the slave device whose address is sent
on the bus along with the Read/ Write operation command. Slave devices connected to the bus
compares the address received with the address assigned to them
6. The slave device with the address requested by the master device responds by sending an
acknowledge bit (Bit value = 1) over the SDA line
7. Upon receiving the acknowledge bit, the master device sends the 8-bit data to the slave device
over SDA line, if the requested operation is 'Write to device'. If the requested operation is 'Read
from device', the slave device sends data to the master over the SDA line
8. The master device waits for the acknowledgement bit from the device upon byte transfer
complete for a write operation and sends an acknowledge bit to the Slave device for a read
operation
9. The master device terminates the transfer by pulling the SDA line ‘HIGH' when the clock line
SCL is at logic 'HIGH' (Indicating the 'STOP' condition).
Serial Peripheral Interface (SPI): Serial Peripheral Interface Bus (SPI) is asynchronous bi-directional
full duplex four-wire serial interface bus. The concept of SPI was introduced by Motorola.
• SPI is a single master multi-slave system. It is possible to have a system where more than one SPI
device can be master, provided the condition only one master device is active at any given point
of time, is satisfied.
• SPI requires four signal lines for communication. They are:
o Master Out Slave In (MOSI): Signal line carrying the data from master to slave device. It
is also known as Slave Input/Slave Data In (SI/SDI).
o Master In Slave Out (MISO): Signal line carrying the data from slave to master device. It
is also known as Slave Output (SO/ SDO).
o Serial Clock (SCL): Signal line carrying the clock signals
o Slave Select (SS): Signal line for slave device select. It is an active low signal.
The bus interface diagram is shown in the following Figure, illustrates the connection of master and slave
devices on the SPI bus.
In addition to the serial data transmission function, UART provides hardware handshaking signal support
for controlling the serial data flow.
UART chips are available from different semiconductor manufacturers. National Semiconductor's 8250
UART chip is considered as the standard setting UART. It was used in the original IBM PC.
1- Wire Interface: 1-wire interface is an asynchronous half-duplex communication protocol developed by
Maxim Dallas Semiconductor. It is also known as Dallas 1-Wire® protocol. It makes use of only a single
signal line (wire) called DQ for communication and follows the master-slave communication model.
• One of the key feature of 1-wire bus is that it allows power to be sent along the signal wire as
well. The 1-wire slave devices incorporate internal capacitor (typically of the order of 800 pF) to
power the device from the signal line.
• The 1-wire interface supports a single master and one or more slave devices on the bus.
The bus interface diagram shown in the following Figure illustrates the connection of master and slave
devices on the 1-wire bus.
Parallel Interface: The on-board parallel interface is normally used for communicating with peripheral
devices which are memory mapped to the host of the system.
• The host processor/ controller of the embedded system contains a parallel bus and the device
which supports parallel bus can directly connect to this bus system. The communication through
the parallel bus is controlled by the control signal interface between the device and the host.
• The 'Control Signals' for communication includes 'Read/ Write' signal and device select signal.
The device normally contains a device select line and the device becomes active only when this
line is asserted by the host processor.
• The direction of data transfer (Host to Device or Device to Host) can be controlled through the
control signal lines for 'Read' and 'Write'. Only the host processor has control over the 'Read' and
'Write' control signals.
• The device is normally memory mapped to the host processor and a range of address is assigned
to it. An address decoder circuit is used for generating the chip select signal for the device. When
the address selected by the processor is within the range assigned for the device, the decoder
circuit activates the chip select line and thereby the device becomes active. The processor then
can read or write from or to the device by asserting the corresponding control line (RD\ and WR\
respectively). Strict timing characteristics are followed for parallel communication.
RS-232 C & RS-485: RS-232 C (Recommended Standard number 232, revision C) from the Electronic
Industry Association is a legacy, full duplex, wired, asynchronous serial communication interface.
• The RS-232 interface is developed by the Electronics Industries Association (EIA) during the
early 1960s. RS-232 extends the UART communication signals for external data communication.
• UART uses the standard TTL/ CMOS logic (Logic 'High' corresponds to bit value 1 and Logic
'Low' corresponds to bit value 0) for bit transmission; whereas RS-232 follows the EIA standard
for bit transmission.
o As per the EIA standard, a logic '0' is represented with voltage between +3 and +25V and
a logic' 1' is represented with voltage between -3 and -25V. In EIA standard, logic '0' is
known as 'Space' and logic '1' as 'Mark'.
• The RS-232 interface defines various handshaking and control signals for communication apart
from the 'Transmit' and. 'Receive' signal lines for data communication.
• RS-232 supports two different types of connectors:
o DB-9: 9-Pin connector and
o DB-25: 25-Pin connector.
• The following Figure illustrates the connector details for DB-9 and DB-25.
RS-232 is a point-to-point communication interface and the device involved in RS-232 communication
are called 'Data Terminal Equipment (DTE)' and 'Data Communication Equipment (DCE)'.
• The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data. The
Data Set Ready (DSR) is activated by DCE when it is ready for establishing a communication
link. DTR should be in the activated state before the activation of DSR.
• The Data Carrier Detect (DCD) control signal is used by the DCE to indicate the DTE that a good
signal is being received.
• RS-232 supports only point-to-point communication and not suitable for multi-drop
communication. It uses single ended data transfer technique for signal transmission and thereby
more susceptible to noise and it greatly reduces the operating distance.
• RS-422 is another serial interface standard from EIA for differential data communication. It
supports data rates up to l00Kbps and distance up to 400 ft. RS-422 supports multi-drop
communication with one transmitter device and receiver devices up to 10.
• RS-485 is the enhanced version of RS-422 and it supports multi-drop communication with up to
32 transmitting devices (drivers) and 32 receiving devices on the bus. The communication
between devices in the bus uses the 'addressing' mechanism to identify slave devices.
Universal Serial Bus (USB): Universal Serial Bus is a wired high speed serial bus for data
communication.
• The first version of USB (USB 1.0) was released in 1995 and was created by the USB core group
members consisting of Intel, Microsoft, IBM, Compaq, Digital and Northern Telecom.
• The USB communication system follows a star topology with a USB host at the centre and one or
more USB peripheral devices/ USB hosts connected to it.
• A USB 2.0 host can support connections up to 127, including slave peripheral devices and other
USB hosts.
The following Figure illustrates the star topology for USB device connection.
• USB transmits data in packet format. Each data packet has a standard format. The USB
communication is a host initiated one. The USB host contains a host controller which is
responsible for controlling the data communication, including establishing connectivity with USB
slave devices, packetizing and formatting the data.
• There are different standards for implementing the USB Host Control interface; namely Open
Host Control Interface (OHCI) and Universal Host Control Interface (UHCI).
• The physical connection between a USB peripheral device and master device is established with a
USB cable. The USB cable in USB 2.0 supports communication distance of up to 5 meters.
• The USB 2.0 standard uses two different types of connector at the ends of the USB cable for
connecting the USB peripheral device and host device.
o 'Type A' connector is used for upstream connection (connection with host) and Type B
connector is used for downstream connection (connection with slave device).
o The USB connector present in desktop PCs or laptops are examples for 'Type A' USB
connector.
o Both Type A and Type B connectors contain 4 pins for communication.
• The Pin details for the connectors are listed in the table given below.
Pin No. Pin Name Description
1 VBUS Carries power (5V)
2 D– Differential data carrier line
3 D+ Differential data carrier line
4 GND Ground signal line
USB uses differential signals for data transmission. It improves the noise immunity. USB interface has
the ability to supply power to the connecting devices. Two connection lines (Ground and Power) of the
USB interface are dedicated for carrying power. It can supply power up to 500 rnA at 5 V.
USB supports o r different types of data transfers, namely; Control, Bulk, Isochronous and Interrupt.
• Control transfer is used by USB system software to query, configure and issue commands to the
USB device.
• Bulk transfer is used for sending a block of data to a device. Bulk transfer supports error checking
and correction.
o Transferring data to a printer is an example for bulk transfer.
• Isochronous data transfer is used for real-time data communication. In Isochronous transfer, data
is transmitted as streams in real-time. Isochronous transfer doesn't support error checking and
retransmission of data in case of any transmission loss.
o All streaming devices like audio devices and medical equipment for data collection make
use of the isochronous transfer.
• Interrupt transfer is used for transferring small amount of data. Interrupt transfer mechanism
makes use of polling technique to see whether the USB device has any data to send. The
frequency of polling is determined by the USB device and it varies from 1 to 255 milliseconds.
o Devices like Mouse and Keyboard, which transmits fewer amounts of data, uses Interrupt
transfer.
IEEE 1394 (Firewire): IEEE 1394 is a wired isochronous high speed serial communication bus. It is also
known as High Performance Serial Bus (HPSB).
• The research on 1394 was started by Apple Inc. in 1985 and the standard for this was coined by
IEEE.
• The implementation of it is available from various players with different names.
o Apple Inc's implementation of 1394 protocol is popularly known as Firewire.
Infrared (IrDA): Infrared is a serial, half duplex, line of sight based wireless technology for data
communication between devices.
• IrDA is in use from the olden days of communication and you may be very familiar with it.
o The remote control of your TV, VCD player, etc., works on Infrared data communication
principle.
• Infrared communication technique uses infrared waves of the electromagnetic spectrum for
transmitting the data.
• IrDA supports point-point and point-to-multipoint communication, provided all devices involved
in the communication are within the line of sight.
• The typical communication range for IrDA lies in the range l0 cm to 1 m. The range can be
increased by increasing the transmitting power of the IR device.
• IR supports data rates ranging from 9600bits/second to 16Mbps. Depending on the speed of
data transmission IR is classified into Serial IR (SIR), Medium IR (MIR), Fast IR (FIR), Very
Fast IR (VFIR) and Ultra Fast IR (UFIR).
o SIR supports transmission rates ranging from 9600bps to 115.2kbps.
o MIR supports data rates of 0.576Mbps and 1.152Mbps.
o FIR supports data rates up to 4Mbps.
o VFIR is designed to support high data rates up to l6Mbps.
o The UFIR supports up to 96Mbps.
• IrDA communication involves a transmitter unit for transmitting the data over IR and a receiver
for receiving the data. Infrared Light Emitting Diode (LED) is the IR source for transmitter and at
the receiving end a photodiode acts as the receiver.
• Both transmitter and receiver unit will be present in each device supporting IrDA communication
for bidirectional data transfer. Such IR units are known as 'Transceiver'.
• Certain devices like a TV require control always require unidirectional communication and so
they contain either the transmitter or receiver unit (The remote control unit contains the
transmitter unit and TV contains the receiver unit).
Bluetooth (BT): Bluetooth is a low cost, low power, short range wireless technology for data and voice
communication.
• Bluetooth was first proposed by 'Ericsson' in 1994.
• Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses the Frequency Hopping
Spread Spectrum (FHSS) technique for communication. Literally it supports a data rate of up to
1Mbps and a range of approximately 30 to 100 feet (version dependent) for data communication.
• Like IrDA, Bluetooth communication also has two essential parts; a physical link part and a
protocol part.
o The physical link is responsible for the physical transmission of data between devices
supporting Bluetooth communication. The physical link works on the wireless principle
making use of RF waves for communication. Bluetooth enabled devices essentially
contain a Bluetooth wireless radio for the transmission and reception of data.
o The protocol part is responsible for defining the rules of communication. The rules
governing the Bluetooth communication is implemented in the 'Bluetooth protocol stack'.
• Each Bluetooth device will have a 48-bit unique identification number. Bluetooth communication
follows packet based data transfer.
• Bluetooth supports point-to-point (device to device) and point-to-multipoint (device to multiple
device broadcasting) wireless communication.
• The point-to-point communication follows the master slave relationship. A Bluetooth device can
function as either master or slave.
o When a network is formed with one Bluetooth device as master and more than one device
as slaves, it is called a Piconet. A Piconet supports a maximum of seven slave devices.
Wi-Fi: Wi-Fi or Wireless Fidelity is the popular wireless communication technique for networked
communication of devices.
• Wi-Fi follows the IEEE 802.11 standard. Wi-Fi is intended for network communication and
supports Internet Protocol (IP) based communication. It is essential to have device identities in a
multi-point communication to address specific devices for data communication.
• In an IP based communication each device is identified by an IP address, which is unique to each
device on the network.
• Wi-Fi based communications require an intermediate agent called Wi-Fi router/ Wireless Access
point to manage the communications.
o The Wi-Fi router is responsible for restricting the access to a network, assigning IP
address to devices on the network, routing data packets to the intended devices on the
network.
• Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the form
of radio signals through an antenna. The hardware part of it is known as Wi-Fi Radio.
• Wi-Fi operates at 2.4GHz or 5GHz of radio spectrum and they co-exist with other ISM band
devices like Bluetooth.
The following Figure illustrates the typical interfacing of devices in a Wi-Fi network.
For communicating with devices over a Wi-Fi network, the device when its Wi-Fi radio is turned ON,
searches the available Wi-Fi network in its vicinity and lists out the Service Set Identifier (SSID) of the
available networks. If the network is security enabled, a password may be required to connect to a
particular SSID.
Wi-Fi employs different security mechanisms like Wired Equivalency Privacy (WEP) Wireless Protected
Access (WPA), etc. for securing the data communication.
Wi-Fi supports data rates ranging from lMbps to 150Mbps (Growing towards higher rates as technology
progresses) depending on the standards (802.lla/b/g/n/ac). Depending on the type of antenna and usage
location (indoor/ outdoor), Wi-Fi offers a range of 100 to 300 feet.
ZigBee: ZigBee is a low power, low cost, wireless network communication protocol based on the IEEE
802.15.4-2006 standard.
• ZigBee is targeted for low power, low data rate and secure applications for Wireless Personal
Area Networking (WPAN).
• The ZigBee specifications support a robust mesh network containing multiple nodes. This
networking strategy makes the network reliable by permitting messages to travel through a
number of different paths to get from one node to another.
• ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400 to 2.484
GHz, 902 to 928 MHz and 868.0 to 868.6 MHz.
• ZigBee Supports an operating distance of up to 100 meters and a data rate of 20 to 250Kbps.
• In the ZigBee terminology, each ZigBee device falls under my one of the following ZigBee
device category:
• ZigBee Coordinator (ZC)/ Network Coordinator: The ZigBee coordinator acts as the root of the
ZigBee network. The ZC is responsible for initiating the ZigBee network and it has the capability
to store information about the network.
• ZigBee Router (ZR)/ Full Function Device (FFD): Responsible for passing information from
device to another device or to another ZR.
• ZigBee End Device (ZED)/ Reduced Function Device (RFD): End device containing ZigBee
functionality for data communication. It can talk only with a ZR or ZC and doesn't have the
capability to act as a mediator for transferring data from one device to another.
The following Figure gives an overview of ZC, ZED and ZR in a ZigBee network:
General Packet Radio Service (GPRS), 3G, 4G, LTE: General Packet Radio Service is a communication
technique for transferring data over a mobile communication network like GSM.
• Data is sent as packets in GPRS communication. The transmitting device splits the data into
several related packets.
• At the receiving end the data is re-constructed by combining the received data packets.
Reset Circuit: The reset circuit is essential to ensure that the device is not operating at a voltage level
where the device is not guaranteed to operate, during system power ON.
• The reset signal brings the internal registers and the different hardware systems of the processor/
controller to a known state and starts the firmware execution from the reset vector (Normally
from vector address 0x0000 for conventional processors/ controllers.
• The reset signal can be either active high (The processor undergoes reset when the reset pin of the
processor is at logic high) or active low (The processor undergoes reset when the reset pin of the
processor is at logic low).
• Since the processor operation is synchronized to a clock signal, the reset pulse should be wide
enough to give time for the clock oscillator to stabilize before the internal reset state starts.
• The reset signal to the processor can be applied at power ON through an external passive reset
circuit comprising a Capacitor and Resistor or through a standard Reset IC like MAX810 from
Maxim Dallas. Select the reset IC based on the type of reset signal and logic level (CMOS/ TTL)
supported by the processor/ controller in use.
• Some microprocessors /controllers contain built-in internal reset circuitry and they don't require
external reset circuitry.
The following Figure illustrates a resistor capacitor based passive reset circuit for active high and low
configurations. The reset pulse width can be adjusted by changing the resistance value R and capacitance
value C.
Brown-out Protection Circuit: Brown-out protection circuit prevents the processor/ controller from
unexpected program execution behavior when the supply voltage to the processor/ controller falls below a
specified voltage.
• It is essential for battery powered devices since there are greater chances for the battery voltage to
drop below the required threshold. The processor behavior may not be predictable if the supply
voltage falls below the recommended operating voltage. It may lead to situations like data
corruption.
• A brown-out protection circuit holds the processor/ controller in reset state, when operating
voltage falls below the threshold, until it rises above the threshold voltage.
• Certain processors/ controllers support built in brown-out protection circuit which monitors the
supply voltage internally.
• If the processor/ controller don’t integrate a built-in brown-out protection circuit, the same can be
implemented using external passive circuits or supervisor ICs.
The following Figure illustrates a brown-out circuit implementation using Zener diode and transistor for
processor/ controller with active low Reset logic.
The Zener diode, Dz, and transistor, Q, forms the heart of this circuit. The transistor conducts always
when the supply voltage VCC is greater than that of the sum of VBE and VZ (Zener voltage). The transistor
stops conducting when the supply voltage falls below the sum of VBE and VZ. Select the Zener diode with
required voltage for setting the low threshold value for VCC. The values of Rl, R2, and R3 can be selected
based on the electrical characteristics of the transistor in use.
• The speed of operation of a processor is primarily dependent on the clock frequency. However we
cannot increase the clock frequency blindly for increasing the speed of execution. The logical
circuits lying inside the processor always have an upper threshold value for the maximum clock
at which the system can run, beyond which the system becomes unstable and non functional.
• The total system power consumption is directly proportional to the clock frequency. The power
consumption increases with increase in clock frequency.
• The accuracy of program execution depends on the accuracy of the clock signal.
The following Figure illustrates the usage of quartz crystal/ ceramic resonator and external oscillator chip
for clock generation.
Real-Time Clock (RTC): Real-Time Clock is a system component responsible for keeping track of time.
RTC holds information like current time (In hours, minutes and seconds) in 12-hour/ 24-hour format,
date, month, year, day of the week, etc. and supplies timing reference to the system.
• RTC is intended to function even in the absence of power. RTCs are available in the form of
Integrated Circuits from different semiconductor manufacturers like Maxim/Dallas, ST
Microelectronics etc.
• The RTC chip contains a microchip for holding the time and date related information and backup
battery cell for functioning in the absence of power, in a single IC package. The RTC chip is
interfaced to the processor or controller of the embedded system.
• For Operating System based embedded devices, a timing reference is essential for synchronizing
the operations of the OS kernel. The RTC can interrupt the OS .kernel by asserting the interrupt
line of the processor/controller to which the RTC interrupt line is connected. The OS kernel
identifies the interrupt in terms of the Interrupt Request (IRQ) number generated by an interrupt
controller. One IRQ can be assigned to the RTC interrupt and the kernel can perform necessary
operations like system date time updating, managing software timers etc when an RTC timer tick
interrupt occurs.
• The RTC can be configured to interrupt the processor at predefined intervals or to interrupt the
processor when the RTC register reaches a specified value (used as alarm interrupt).
Watchdog Timer: In desktop Windows systems, if we feel our application is behaving in an abnormally
or if the system hangs up, we have the 'Ctrl + Alt + Del' to come out of the situation. What it happens to
embedded system?
• We have a watchdog to monitor the firmware execution and reset the system processor/
microcontroller when the program execution hangs up. A watchdog timer, or simply a watchdog,
is a hardware timer for monitoring the firmware execution. Depending on the internal
implementation, the watchdog timer increments or decrements a free running counter with each
clock pulse and generates a reset signal to reset the processor if the count reaches zero for a down
counting watchdog, or the highest count value for an up counting watchdog.
• If the watchdog counter is in the enabled state, the firmware can write a zero (for up counting
watchdog implementation) to it before starting the execution of a piece of code and the watchdog
will start counting. If the firmware execution doesn't complete due to malfunctioning, within the
time required by the watchdog to reach the maximum count, the counter will generate a reset
pulse and this will reset the processor. If the firmware execution completes before the expiration
of the watchdog, you can reset the count by writing a 0 (for an up counting watchdog timer) to the
watchdog timer register.
• If the processor/ controller doesn't contain a built in watchdog timer, the same can be
implemented using an external watchdog timer IC circuit. The external watchdog timer uses
hardware logic for enabling/ disabling, resetting the watchdog count, etc., instead of the firmware
based 'writing' to the status and watchdog timer register. The microprocessor supervisor IC DS
1232 integrates a hardware watchdog timer in it.
The following Figure illustrates the implementation of the external watchdog timer based microprocessor
based supervisor circuit for a small embedded system.