JSS MAHAVIDYAPEETHA

JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA

INTEGRATED CIRCUITS
KEC-501

V SEMESTER
Electronics & Communication Engineering
UNIT-4
INTEGRATED CIRCUIT TIMER
As per the syllabus of
Dr. A.P.J. Abdul Kalam Technical University, UTTAR PRADESH

JSS Academy of Technical Education,

NOIDA.

Dr. ARUN KUMAR. G

Professor & HOD, Dept. of ECE
 CONTENTS
UNIT-4: INTEGRATED CIRCUIT TIMER
4.1 555 TIMER CIRCUIT 108
4.1.1 IC 555 PIN DIAGRAM 111
4.2 ASTABLE MULTIVIBRATOR USING IC 555: 112
4.2.1 Application of Astable Multivibrator using IC 555 116
ASTABLE MULTIVIBRATOR-FORMULAE 116
ASTABLE MULTIVIBRATOR-NUMERICAL 117
4.3 MONOSTABLE MULTIVIBRATOR USING IC 555 121
4.3.1 Applications of Monostable Multivibrator using IC 555 123
MONOSTABLE MULTIVIBRATOR-FORMULAE 124
MONOSTABLE MULTIVIBRATOR-NUMERICAL 124
4.4 VOLTAGE CONTROLLED OSCILLATOR 125
4.4.1 APPLICATIONS OF VCO 127
4.5 PHASE LOCKED LOOP (PLL) 127
4.5.1 Applications of PLL 129
4.5.2 PLL IC (SE/NE 565) 129
4.5.3 EX-OR gate as Phase Detector 132
4.5.4 Multipliers as Phase Detectors 133
4.6 APPLICATIONS OF PLL 134
Frequency Multiplier 134
Frequency Synthesizer using PLL 134
1. Frequency Shift Keying Demodulator (FSK): 135
FM detector Using PLL 136
AM detection using PLL 136
Frequency translator using PLL 137

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Unit-5 Digital Integrated Circuit Design

UNIT
5
DIGITAL INTEGRATED CIRCUIT
DESIGN

SYLLABUS
Digital Integrated Circuit Design: An overview, CMOS logic gate circuits basic structure, CMOS
realization of inverters, AND, OR, NAND and NOR gates.
Latches and Flip flops: The latch, CMOS implementation of SR flip-flops, a simpler CMOS
implementation of the clocked SR flip-flop, CMOS implementation of J-K flipflops, D flip- flop circuits.

5.1 CMOS OVERVIEW: Classification of different IC technologies and logic families is indicated
below
1 CMOS i. Complementary
ii. Pseudo-NMOS
iii. Pass Transistor Logic
iv. Dynamic Logic
2 Bipolar i. TTL
ii. ECL
3 BiCMOS
4 GaAs

5.1.1 LOGIC GATE CHARACTERISTICS:

The logic gates characteristics are
1. Propagation delay
2. Fan-in
3. Fan-out
4. Noise Margin
5. Power dissipation
6. Figure of Merits (FOM)

Propagation delay:
Propagation delay in digital logic refers to the time it takes for a signal to travel from the input of
a digital circuit to the output. It is a critical parameter in the performance of digital circuits and is
measured in terms of time.
The delay times are measured between the 50% voltage levels of input and output waveforms.

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Fig. 5.1: Propagation delay

Where,
tpHL : When the output goes from the HIGH state to LOW state
tpLH : When the output goes from the LOW state to HIGH state

The propagation delay time of the logic gate is the average of the tpHL and tpLH i.e.

𝒕𝒑𝑯𝑳 + 𝒕𝒑𝑳𝑯
𝒕𝒑 =
𝟐
The propagation delay can also be computed as below
Delay at each gate output = Maximum input delay + Gate delay

Fan-in:
• The fan-in is the number of inputs to a gate
For example: a 3-input AND gate has a Fan-in of 3
• Logic gates with a large fan-in tend to be slow
• Increasing the Fan-in of a gate increases the gate delay
For example, a 3-input AND gate has a higher delay than a 2-input AND gate made with
the same technology

Fan-out:
• Fan-out refers to the number of output signals or connections from a particular gate or
logic element. In digital circuits, it is common for the output of one gate (called driver
gate) to be connect to the inputs of several load gates.
• Example: If the output of an AND gate is connected to (or drives) two other gates, the fan-
out of that AND gate is 2 as shown in the figure.

Fig. 5.2: Fan out

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Unit-5 Digital Integrated Circuit Design
Noise Margin:

Fig. 5.3: Noise Margin

The noise margin is defined as the difference between the minimum acceptable input voltage for a
logic level and the actual input voltage at the threshold of the logic level. There are two types of
noise margins: high-level noise margin (NMH) and low-level noise margin (NML).

High-Level Noise Margin (NMH):

NMH is the difference between the minimum acceptable HIGH input voltage (VIH) and the HIGH
output voltage (VOH) at the threshold.
NMH = VOH - VIH

Low-Level Noise Margin (NML):

NMH is the difference between the minimum acceptable HIGH input voltage (V IH) and the HIGH
output voltage (VOH) at the threshold.
NML = VIL – VOL

Power dissipation:
Power dissipation in digital logic refers to the energy consumed by digital circuits during their
operation. Power dissipation in digital logic can be broadly categorized into two main types:
dynamic power and static power.
Dynamic Power Dissipation:
Dynamic power is associated with the dynamic switching of transistors and capacitors within
digital circuits.
Static Power Dissipation:
Static power refers to the power consumed by a digital circuit when it is in a steady state, i.e.,
when there is no switching activity.

Figure of Merits (FOM):

FOM of a logic family is defined as the product of the propagation delay (tp) and the power
dissipation (PDavg).
FOM = (tp ) (PDavg)

5.1.2 MOS TRANSISTOR SYMBOLIC REPRESENTATION:

NMOS PMOS

Figure 5.4: MOS transistor Symbolic representation for Digital Circuit Design

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5.2. BASIC STRUCTURE OF CMOS LOGIC:

Fig. 5.5: Basic structure of CMOS logic gates

5.2.1 CMOS INVERTER:

Fig. 5.6: CMOS Inverter

As shown in Figure above, PMOS transistor is used as a pull-up transistor, so its source is
connected to supply voltage and drain is connected to the output node.

Similarly, the NMOS transistor is used as a pull-down transistor. That means its source terminal is
connected to ground terminal and drain is connected to output node and the gate terminals of
both PMOS and NMOS transistor is connected to the input.

WORKING OF CMOS INVERTER:

Vin Vo
0 1
1 0

Note: Logic 0 = 0V and Logic 1 = 5V

Case i: When Vin =0V

NMOS is OFF and acts as an open circuit and PMOS is ON and acts as a short circuit. Thus, V DD is
connected to V0, so output V0 =1.

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Unit-5 Digital Integrated Circuit Design

Fig. 5.7: CMOS Inverter

Case ii: When Vin =5V
NMOS is ON and acts as a short circuit and PMOS is OFF and acts as an open circuit. Thus, ground
is connected to V0, so output V0 =0.

Fig. 5.8: CMOS Inverter

5.2.2 PUN & PDN NETWORK WITH EXAMPLES:

The examples of static CMOS logic design of a pull down netwrok (PDN) comprising
of nMOS transistors is shown in the figure below. The PDN netwrok conducts when
input is high. The first circuit has two nMOS transistors connected in parallel. If any of
the transistor is fed with HIGH input, the nMOS tranistor will conduct and a
connection between output and ground gets established. (As shown in figure (a)).
𝑌̅ = 𝐴 + 𝐵 𝑜𝑟 𝑌 = 𝐴 ̅̅̅̅̅̅̅̅
+ 𝐵 Such a logic functionality represnts an OR gate.Whereas a
series combination of nMOS devices (as shown in figure (b))will not establish ground
connection unless both the nMOS transistors connected in series are ON ot their
inptu is connected to HIGH logic level. 𝑌̅ = 𝐴 ∙ 𝐵 𝑜𝑟 𝑌 = ̅̅̅̅̅̅
𝐴 ∙ 𝐵 This results in to
representation of AND logic. The figure (c)represents a log functionality as 𝑌̅ = 𝐴 +
𝐵 ∙ 𝐶 𝑜𝑟 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐴+𝐵∙𝐶
The examples of PUN comprising of pMOS transistors are shown in the figure. With
pMOS turning ON for 𝑉𝑖𝑛 = 0 and source connected to 𝑉𝐷𝐷 , the first circuit will

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Unit-5 Digital Integrated Circuit Design
establish connection between supply voltage and output if any of the two transistors
are ON. Hence it represents logical funcationlity expressed as 𝑌 = 𝐴̅+𝐵̅. The second
circuit (figure(b)) can establish connection only when both pMOS transistors are ON

𝑌̅ = 𝐴 + 𝐵 𝑌̅ = 𝐴 ∙ 𝐵 𝑌̅ = 𝐴 + 𝐵 ∙ 𝐶

. .
Fig. 5.9: Example of PDN Network
. Thus the logic functionality represenated is 𝑌 = 𝐴̅ ∙ 𝐵̅ . Finally in the circuit (c) the
output will be HIGH if either A is LOW or both B and C inputs are LOW.Thus the logic
functionality is 𝑌 = 𝐴̅+ 𝐵̅ 𝐶̅ .

Fig. 5.10: Example of PUN Network

5.3. LOGIC GATES:

A logic gate is a digital gate that allows data to be transferred. Logic gates, use logic to determine
whether or not to pass a signal.
Types of Logic Gates are AND, OR, NOT, NOR, NAND, XOR and XNOR.

5.3.1 IMPLEMENTATION OF LOGIC GATES USING CMOS LOGIC:

NOT GATE USING CMOS LOGIC:

The NOT gate is an electronic circuit
A 𝐘=𝑨̅ that produces an inverted version of
0 0 the input at its output. It is also
NOT
known as an inverter. If the input
1 0 variable is A, the inverted output is
known as NOT A.

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Unit-5 Digital Integrated Circuit Design
The CMOS logic for NAND gate implementation is as shown below
𝐘=𝑨 ̅

Fig. 5.11: CMOS logic for NOT GATE

NAND GATE USING CMOS LOGIC:

This is a NOT-AND gate which is
A B Y= A.B equal to an AND gate followed by a
0 0 1 NOT gate. The outputs of all NAND
gates are high if any of the inputs
NAND 0 1 1
are low.
1 0 1 Note: The symbol is an AND gate with
1 1 0 a small circle (Bubble) on the output.
The small circle represents inversion.

The CMOS logic for NAND gate implementation is as shown below

𝐘 = ̅̅̅̅̅̅
𝑨 .𝑩

Fig. 5.12: CMOS logic for NAND GATE

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Unit-5 Digital Integrated Circuit Design
NOR GATE USING CMOS LOGIC:

𝒀 = ̅̅̅̅̅̅̅̅
𝑨+𝑩 This is a NOT-OR gate which is equal
A B to an OR gate followed by a NOT
0 0 1 gate. The outputs of all NOR gates
NOR are low if any of the inputs are high.
0 1 0
Note: The symbol is an OR gate with a
1 0 0 small circle on the output. The small
1 1 0 circle represents inversion.
The CMOS logic for NOR gate implementation is as shown below

𝒀 = ̅̅̅̅̅̅̅̅
𝑨+𝑩

Fig. 5.13: CMOS logic for NOR GATE

OR GATE USING CMOS LOGIC:

A B Y=A + B
0 0 0 The OR gate is an electronic circuit
that gives a high output (1) if one or
OR 0 1 1
more of its inputs are high. A plus
1 0 1 (+) is used to show the OR operation.
1 1 1
The CMOS logic for OR gate implementation is as shown below
𝒀 = 𝑨+𝑩
𝑌 = ̅̅̅̅̅̅̅̅
𝐴+𝐵
𝒀 = ̅̅̅̅̅̅̅̅
(𝑨‾.𝑩 ‾)

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Unit-5 Digital Integrated Circuit Design

Fig. 5.14: CMOS logic for OR GATE

METHOD-2
To implement the OR gate, just add the inverter at the output of the NOR gate. The CMOS OR gate
is shown below.

Fig. 5.15: CMOS logic for OR GATE

AND GATE USING CMOS LOGIC:

A B Y= A B
0 0 0 The AND gate is an electronic circuit that
gives a high output (1) only if all its
AND 0 1 0
inputs are high. A dot (.) is used to show
1 0 0 the AND operation, i.e., A . B
1 1 1

The CMOS logic for AND gate implementation is as shown below

𝐘 = 𝑨 .𝑩
Y = ̅̅̅̅̅̅
𝐴 .𝐵
𝐘 = ̅̅̅̅̅̅̅̅
𝑨‾ +𝑩 ‾

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Unit-5 Digital Integrated Circuit Design

Fig. 5.16: CMOS logic for AND GATE

METHOD-2:
By connecting the inverter at the output of the NAND gate, we can implement AND gate. The
CMOS AND gate is shown below.

Fig. 5.17: CMOS logic for AND GATE

XOR GATE USING CMOS LOGIC:

A B Y= A  B The 'Exclusive-OR' gate is a circuit

0 0 0 which will give a high output if
either, but not both, of its two
EX-OR 0 1 1
inputs are high. An encircled plus
1 0 1 sign ( ) is used to show the EXOR
1 1 0 operation.

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Unit-5 Digital Integrated Circuit Design
The CMOS logic for XOR gate implementation is as shown below
Y =𝑨 ‾ 𝑩+𝑨𝑩 ‾
̅̅̅̅̅̅̅̅̅̅̅̅̅
‾ 𝑩+𝑨𝑩 ‾
=𝑨
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅
‾ 𝑩) ⋅ (𝑨̅̅̅̅̅
‾)
= (𝑨 𝑩
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (𝐴‾̅ + 𝐵‾) ⋅ (𝐴‾ + 𝐵̅‾ )
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵‾) ⋅ (𝐴‾ + 𝐵)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐴‾ + 𝐴𝐵 + 𝐴‾𝐵‾ + 𝐵𝐵‾
Y = ̅̅̅̅̅̅̅̅̅̅̅̅
𝑨𝑩 + 𝑨 ‾𝑩‾

Fig. 5.18: CMOS logic for XOR GATE

XNOR GATE USING CMOS LOGIC:

The 'Exclusive-NOR' gate circuit
A B Y= AB does the opposite to the EOR gate. It
0 0 1 will give a low output if either, but
EX-
0 1 0 not both, of its two inputs are high.
NOR
1 0 0 Note: The symbol is an EXOR gate
with a small circle on the output. The
1 1 1
small circle represents inversion.

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Unit-5 Digital Integrated Circuit Design
The CMOS logic for XNOR gate implementation is as shown below
Y =𝑨 ‾𝑩 ‾ + 𝑨𝑩
̅̅̅̅̅̅̅̅̅̅̅̅
= 𝐴‾𝐵‾ + 𝐴𝐵
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅
‾𝐵‾) ⋅ (𝐴𝐵
̅̅̅̅)
= (𝐴
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (𝐴‾̅ + 𝐵̅‾ ) ⋅ (𝐴‾ + 𝐵‾)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵) ⋅ (𝐴‾ + 𝐵‾)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐴‾ + 𝐴𝐵‾ + 𝐴‾𝐵 + 𝐵𝐵‾
Y = ̅̅̅̅̅̅̅̅̅̅̅̅
𝑨𝑩 ‾ +𝑨 ‾𝑩

Fig. 5.19: CMOS logic for XNOR GATE

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Unit-5 Digital Integrated Circuit Design
5.3.2 AOI and OAI Gates:
Apart from NAND and NOR there are few important but complex gates that find
applications in AND-OR-INVERT (AOI) and OR-AND-INVERT(OAI)fuctions that can be
implemented .These gates have propagation delay equivalent to NAND or NOR gates.
These gates are essentially the representations of SOP or POS expression formats of the
Boolean expressions. They can be used as a basic building block for a PLA or PLD.
The examples of AOI and OAI gates have been illusrtated for understanding the CMOS
realization
Consider the SOP expression 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵 + 𝐶𝐷 and its implementation using basic logic gates
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
and CMOS logic.Similarly illustration of POS expression expression 𝑌 = (𝐴 + 𝐵)(𝐶 + 𝐷) is
shown in the figure

𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵)(𝐶 + 𝐷)
𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵 + 𝐶𝐷

A B C D y A B C D y
0 X 0 X 1 1 X 1 X 0
0 X X 0 1 1 X X 1 0
X 0 0 X 1 X 1 1 X 0
X 0 X 0 1 X 1 X 1 0
X X 1 1 0 X X 1 1 1
1 1 X X 0 1 1 X X 1

Fig. 5.20: Realization of AOI and OAI functionalities using CMOS logic

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Unit-5 Digital Integrated Circuit Design
Realize Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐃 + 𝐀. (𝐁 + 𝐂) using CMOS logic

Fig. 5.21: CMOS logic for the boolean expression Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

𝐃 + 𝐀. (𝐁 + 𝐂)

Implement Y= [̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨(𝑩 + 𝑪) + 𝑫𝑬 ] using CMOS logic.

Fig. 5.22: CMOS logic for the boolean expression Y= [̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

𝑨(𝑩 + 𝑪) + 𝑫𝑬 ]

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Unit-5 Digital Integrated Circuit Design
4 Input NAND GATE:

Fig. 5.23: CMOS logic 4 Input NAND GATE

5.3.3 HALF ADDER USING CMOS LOGIC:

• A half adder is a digital logic circuit that performs binary addition of two single-bit binary
numbers. It has two inputs, A and B, and two outputs, SUM and CARRY.
• The SUM output is the least significant bit (LSB) of the result, while the CARRY output is
the most significant bit (MSB) of the result, indicating whether there was a carry-over
from the addition of the two inputs.
• The half adder can be implemented using basic gates such as XOR and AND gates.
• Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic
circuit that adds two numbers and produces a sum bit (s) and carry bit (c) both as output.

Truth-Table Individual Boolean Sum & Carry Boolean

A B SUM CARRY Expression Expression
0 0 0 0 - -
0 1 1 0 ‾
𝑨. 𝑩 ‾ . 𝑩 + 𝑨. 𝑩
‾
Sum= 𝑨
1 0 1 0 𝑨. 𝑩‾
1 1 0 1 𝑨. 𝑩 Carry = 𝑨. 𝑩

Fig. 5.24: Half adder

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Unit-5 Digital Integrated Circuit Design
Boolean expression to implement CMOS logic
SUM CARRY
Sum = 𝑨 ‾ 𝑩 + 𝑨𝑩 ‾ 𝐂𝐚𝐫𝐫𝐲 = 𝐀 . 𝑩
̅̅̅̅̅̅̅̅̅̅̅̅
= 𝐴‾𝐵 + 𝐴𝐵‾ = ̅̅̅̅̅̅
A .𝐵
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (𝐴̅̅̅̅ ̅̅̅̅‾ )
‾𝐵) ⋅ (𝐴𝐵 Carry = ̅̅̅̅̅̅̅̅̅̅
(𝑨‾ +𝑩 ‾)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (𝐴‾̅ + 𝐵‾) ⋅ (𝐴‾ + 𝐵̅‾ )
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵‾) ⋅ (𝐴‾ + 𝐵)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐴‾ + 𝐴𝐵 + 𝐴‾𝐵‾ + 𝐵𝐵‾
Sum = ̅̅̅̅̅̅̅̅̅̅̅̅
𝑨𝑩 + 𝑨 ‾𝑩‾

Fig. 5.25: Half adder using CMOS logic

5.3.4 FULL ADDER USING CMOS LOGIC:

• The half adder is used to add only two numbers. To overcome this problem, the full adder
was developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C.
• The full adder has three input states and two output states i.e., sum and carry.

Fig. 5.26: Full adder

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Unit-5 Digital Integrated Circuit Design

Fig. 5.27: Full adder using two half adder

• There are two half adder circuits that are combined using the OR gate. The first half adder
has two single-bit binary inputs A and B. As we know that, the half adder produces two
outputs, i.e., Sum and Carry.
• The 'Sum' output of the first adder will be the first input of the second half adder, and the
'Carry' output of the first adder will be the second input of the second half adder. The
second half adder will again provide 'Sum' and 'Carry'.
• The final outcome of the Full adder circuit is the 'Sum' bit. In order to find the final output
of the 'Carry', we provide the 'Carry' output of the first and the second adder into the OR
gate. The outcome of the OR gate will be the final carry out of the full adder circuit.

Fig. 5.28: Full adder

From the truth table we can write the carry expression as below
Carry = 𝑨‾ 𝑩𝑪in + 𝑨𝑩 ‾ 𝑪in + 𝑨𝑩𝑪‾in + 𝑨𝑩𝑪in

Wkt 𝑨 = 𝑨 + 𝑨 and 𝑨 = 𝑨 + 𝑨 + 𝑨 i.e. 𝐴𝐵𝐶in = 𝐴𝐵𝐶in + 𝐴𝐵𝐶in + 𝐴𝐵𝐶in

𝐶out = 𝐴‾𝐵𝐶in + 𝐴𝐵‾𝐶in + 𝐴𝐵𝐶‾in + 𝐴𝐵𝐶in + 𝐴𝐵𝐶in + 𝐴𝐵𝐶in

= 𝐵𝐶in [𝐴‾ + 𝐴] + 𝐴𝐵‾𝐶in + 𝐴𝐵𝐶‾in + 𝐴𝐵𝐶in + 𝐴𝐵𝐶in
= 𝐵𝐶in + 𝐴𝐶in [𝐵‾ + 𝐵] + 𝐴𝐵𝐶‾in + 𝐴𝐵𝐶in
= 𝐵𝐶in + 𝐴𝐶in + 𝐴𝐵[𝐶‾in + 𝐶in ]
𝐶out = 𝐴𝐵 + 𝐵𝐶in + 𝐴𝐶in

𝑪out = 𝑨𝑩 + 𝑪in (𝑨 + 𝑩)

From the truth table we can write the sum expression as below
Sum = 𝑨 ‾𝑩 ‾ 𝑩𝑪‾in + 𝑨𝑩
‾ 𝑪in + 𝑨 ‾ 𝑪‾in + 𝑨𝑩𝑪in

• For the implementation of the sum using CMOS logic, we initially require 26 transistors
(24 for the basic sum and 2 for the Inverter).
• To minimize the transistor count, we rewrite the sum truth table, considering the
complement of carry i.e. 𝑪‾out as the fourth input. This modification allows us to
implement a full adder circuit using only 16 transistors.

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Unit-5 Digital Integrated Circuit Design

Revised Truth-Table Individual

Boolean Sum boolean expression
A B 𝑪in 𝑪‾out 𝐒𝐮𝐦 expression

0 0 0 1 0 -

0 0 1 1 1 𝑪in 𝑪‾out

0 1 0 1 1 ‾ out
𝑩𝑪

0 1 1 0 0 - ‾ out + 𝑩 𝑪
‾ out + 𝑨 𝑪‾out + 𝑨 𝑩 𝑪in
Sum = 𝑪in 𝑪
1 0 0 1 1 𝑨 𝑪‾out

1 0 1 0 0 -

1 1 0 0 0 -

1 1 1 0 1 𝑨 𝑩 𝑪in
• The Sum is given by
Sum = 𝐶in 𝐶‾out + 𝐵 𝐶
‾ out + 𝐴 𝐶‾out + 𝐴 𝐵 𝐶in

Sum = 𝑪‾out [ 𝑨 + 𝑩 + 𝑪in ] + 𝑨 𝑩 𝑪in

• The implementation of the sum using CMOS logic, we require only 16 transistors (14 for
the basic sum and 2 for the Inverter).

Fig. 5.29: Full adder using CMOS logic

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Unit-5 Digital Integrated Circuit Design
5.3.5. ONE-BIT MAGNITUDE COMPARATOR:
• A magnitude digital Comparator is a combinational circuit that compares two digital or
binary numbers in order to find out whether one binary number is equal, less than, or
greater than the other binary number.
• A comparator used to compare two bits is called a single-bit comparator. It consists of two
inputs A & B and three outputs A > B, A = B and A < B condition

Fig. 5.30: One bit comparator

The truth table for a 1-bit comparator is given below.

Individual Boolean 1-bit comparator
A B A>B A<B A=B
expression Boolean expression

0 0 0 0 1 ̅B
A ̅ ̅𝐁
Y (A=B) = 𝐀 ̅ +AB

1 0 1 0 0 ̅
AB ̅
Y (A>B) = 𝐀 𝐁

0 1 0 1 0 ̅B
A ̅B
Y (A<B) = 𝐀

1 1 0 0 1 AB Clubbed with 1st row

The boolean expression to implement CMOS logic for 1-bit magnitude comparator is given below
for 𝑌(𝐴=𝐵) , 𝑌(𝐴<𝐵) and 𝑌(𝐴>𝐵)

𝒀(𝑨=𝑩) 𝒀(𝑨<𝑩) 𝒀(𝑨>𝑩)

𝒀(𝑨<𝑩) =𝑨‾𝑩 𝒀(𝑨>𝑩) = 𝐀𝑩 ‾

𝒀(𝑨=𝑩) =𝑨‾𝑩 ‾ + 𝑨𝑩 ̅̅̅̅ ̅̅̅̅
=𝑨‾𝑩 = 𝐀𝑩 ‾
̅̅̅̅̅̅̅̅̅̅̅̅
‾𝑩 ‾ + 𝑨𝑩 ̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅
=𝑨 = (𝐴‾̅ + 𝐵‾) = (𝐴‾ + 𝐵̅‾ )
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅
‾𝑩‾ ) ⋅ (𝑨𝑩
̅̅̅̅)
= (𝑨 𝒀(𝑨<𝑩) = ̅̅̅̅̅̅̅̅̅̅
(𝑨 + 𝑩 ‾) 𝒀(𝑨>𝑩) = ̅̅̅̅̅̅̅̅̅̅
(𝑨‾ + 𝑩)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (𝐴‾̅ + 𝐵̅‾ ) ⋅ (𝐴‾ + 𝐵‾)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵) ⋅ (𝐴‾ + 𝐵‾)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐴‾ + 𝐴𝐵‾ + 𝐴‾𝐵 + 𝐵𝐵‾
𝒀(𝑨=𝑩) = ̅̅̅̅̅̅̅̅̅̅̅̅
𝑨𝑩 ‾ +𝑨 ‾𝑩

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Unit-5 Digital Integrated Circuit Design

Fig. 5.31: CMOS logic for 1-bit Magnitude Comparator

5.4. FLIP-FLOP AND LATCHES:

FLIP-FLOP:
• A Flip-Flop is a basic memory unit which can store 1-bit of digital information.
• It is a Bistable Electronic Circuit i.e., it has two stable states: HIGH or LOW.
• As a flip-flop is a bistable element, its output remains in either of the stable states until an
external event (known as a trigger) is applied.
• The state of flip-flop changes at active state of clock pulses and remains unaffected when
the clock pulse is not active.

LATCHES:
• Latch is an electronic device, which changes its output immediately based on the applied
input. It is used to store either 1 or 0 at any specified time. It consists of two inputs
namely “SET” and RESET and two outputs, which are complement to each other.
• In digital logic, a latch is a bistable electronic circuit that has two stable states i.e.
low & high. Due to these states, latches also refer to as bistable-multivibrators. The
latch stores 1 -bit
• A latch is a fundamental building block in digital systems and is commonly used in
memory circuits, registers, and other sequential logic elements. The latches are level-
sensitive and respond to changes in the input signal levels.
• The primary characteristic of a latch is its ability to "latch" onto a particular state and
hold that state until a specific condition or signal causes it to change.
• Latches are classified based on their functionality and the number of inputs they have.
Common types of latches include the SR latch, D latch, and JK latch.

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Unit-5 Digital Integrated Circuit Design
5.4.1 DIFFERENCE BETWEEN FLIP-FLOP AND LATCH:
Sl. No. FLIP-FLOP LATCH

1 Flip-flop is a bistable device i.e., it has two Latch is also a bistable device whose states
stable states that are represented as 0 are also represented as 0 and 1.
and 1.

2 It checks the inputs but changes the It checks the inputs continuously and
output only at times defined by the clock responds to the changes in inputs
signal or any other control signal. immediately.

3 It is a edge triggered device. It is a level triggered device.

4 Gates like NOR, NOT, AND, NAND are These are also made up of gates.
building blocks of flip flops.

5 They are classified into asynchronous or There is no such classification in latches.

synchronous flipflops.

6 It forms the building blocks of many These can be used for the designing of
sequential circuits like counters. sequential circuits but are not generally
preferred.
7 a, Flip-flop always have a clock signal Latches doesn’t have a clock signal

8 Flip-flop can be build from Latches Latches can be build from gates

9 ex: D Flip-flop, JK Flip-flop ex: SR Latch, D Latch

5.4.2. SR FLIP-FLOP:
SR Latch based on NOR Gate:

OR

Fig. 5.32: SR Latch based on NOR Gate

If the set input (S) is equal to logic "1" and the reset input is equal to logic "0." then the output Q
will be forced to logic "1". While 𝐐 ̅ is forced to logic "0". This means the SR latch will be set,
irrespective of its previous state.
̅ is
Similarly, if S is equal to "0" and R is equal to "1" then the output Q will be forced to "0" while 𝐐
forced to "1". This means the latch is reset, regardless of its previously held state. Finally, if both
of the inputs S and R are equal to logic "1" then both outputs will be forced to logic "0" which
conflicts with the complementarity of Q and 𝐐 ̅.
Therefore, this input combination is not allowed during normal operation. Truth table of NOR
based SR Latch is given in table.

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Unit-5 Digital Integrated Circuit Design

S R Q ̅
𝐐 Operation

0 0 Q ̅
𝐐 Hold

1 0 1 0 Set

0 1 0 1 Reset

1 1 0 0 Not allowed

CMOS SR latch based on NOR latch is shown in the figure given below.

‾ = ̅̅̅̅̅̅̅̅
𝑸 𝑺+𝑸 𝐐 = ̅̅̅̅̅̅̅̅
𝑹+𝑸 ‾

Fig. 5.33: CMOS logic SR latch based on NOR

SR Latch based on NAND Gate:

Fig. 5.34: SR Latch based on NAND Gate

Block diagram and gate level schematic of NAND based SR latch is shown in the figure. The small
circles at the S and R input terminals represents that the circuit responds to active low input
signals.

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Unit-5 Digital Integrated Circuit Design
The truth table of NAND based SR latch is given in table
S R Q ̅
𝐐 Operation

0 0 X X Invalid condition.

1 0 1 0 SET

0 1 0 1 RESET

1 1 NC NC No change (HOLD)

̅ low and the latch enters Set state i.e. Q=1 & 𝐐
If S=1 & R=0; then Q goes high, pulling 𝐐 ̅ = 𝟎.
̅ high and the latch enters Set state i.e. Q=0 & 𝐐
If S=0 & R=1; then Q goes low, pulling 𝐐 ̅ = 𝟏.
If S=0 & R=0; then Invalid state
If S=1 & R=1; then No Change

CMOS SR latch based on NAND latch is shown in the figure given below.

𝐐 = ̅̅̅̅̅̅
𝑺 .𝑸 ‾ ‾ = ̅̅̅̅̅̅
𝑸 𝑹 .𝐐

Fig. 5.35: CMOS logic SR Latch based on NAND Gate

Clocked SR Latch using NOR

The figure shows a NOR-based SR latch with a clock added. The latch is responsive to inputs S and
R only when CLK is high.

Fig. 5.36: Clocked SR Latch using NOR

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Unit-5 Digital Integrated Circuit Design
When CLK is low, the latch retains its current state. Observe that Q changes state:
• When S goes high during positive CLK.
• On leading CLK edge after changes in S & R during CLK low time.
• A positive glitch in S while CLK is high
• When R goes high during positive CLK.

Fig. 5.37: CMOS logic Clocked SR Latch using NOR

CMOS AOI implementation of clocked NOR based SR latch is shown in the figure. Note that only 12
transistors required.
• When CLK is low, two series terminals in N tree N are open and two parallel transistors in
tree P are ON, thus retaining state in the memory cell.
• When clock is high, the circuit becomes simply a NOR based CMOS latch which will
respond to input S and R.

Clocked SR Latch based on NAND Gate:

Circuit is implemented with four NAND gates. If this circuit is implemented with CMOS then it
requires 16 transistors.
• The latch is responsive to S or R only if CLK is high.
• If both input signals and the CLK signals are active high: i.e., the latch output Q will be set
when CLK = "1" S = "1" and R = "0"
• Similarly, the latch will be reset when CLK = "1," S = "0," and
When CLK is low, the latch retains its present state.

OR

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Unit-5 Digital Integrated Circuit Design

Fig. 5.38: Clocked SR Latch using NAND

CMOS Implementation of Clocked SR Latch using NAND is shown in below figure.

̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐐 = (𝑺 + 𝑪𝑲) 𝑸 ‾ ‾ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑸 (𝑹 + 𝐂𝐊) 𝐐

Fig. 5.39: CMOS logic Clocked SR Latch using NAND

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Unit-5 Digital Integrated Circuit Design
CLOCKED JK FLIP-FLOP:

Fig. 5.40: Clocked JK Flip-Flop using NAND

The figure above shows a clocked JK latch, based on NAND gates. The disadvantage of an SR latch
is that when both S and R are high, its output state becomes indeterminant. The JK latch
eliminates this problem by using feedback from output to input, such that all input states of the
truth table are allowable. If J = K = 0, the latch will hold its present state.
̅= 0
If J = 1 and K = 0, the latch will set on the next positive-going clock edge, i.e. Q = 1, 𝐐
̅ = 0.
If J = 0 and K = 1, the latch will reset on the next positive-going clock edge, i.e. Q = 1 and 𝐐
If J = K = 1, the latch will toggle on the next positive-going clock edge.

The operation of the clocked JK Flip-Flop is summarized in the truth table given in table.

TRUTH-TABLE
CLK J K Q 𝐐 ̅ OPERATION
0 X X Q 𝐐 ̅
1 0 0 Q 𝐐 ̅ Previous state
1 0 1 0 1
1 1 0 1 0
1 1 1 Toggle or Race around

CMOS implementation of Clocked JK Flip-Flop using NAND gate is shown in below figure.

̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅
‾ 𝐶𝐿𝐾 )𝑄‾ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑄‾ = (𝐾𝑄
̅̅̅̅̅̅̅̅̅̅
𝐶𝐿𝐾 )𝑄
𝑄 = (𝐽𝑄

𝑸 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( 𝑱‾ + 𝐐 + ̅̅̅̅̅̅
𝑪𝑳𝑲 ) . 𝑸 ‾ ‾ = ( ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑸 𝑲‾ + 𝑸‾ + 𝑪𝑳𝑲
̅̅̅̅̅̅ ) . 𝑸

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Unit-5 Digital Integrated Circuit Design

Fig. 5.41: CMOS Logic for Clocked JK Flip-Flop using NAND

CLOCKED JK FLIP-FLOP USING NOR:

Fig. 5.42: Clocked JK Flip-Flop using NOR

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Unit-5 Digital Integrated Circuit Design
The operation of the clocked JK Flip-Flop is summarized in the truth table given in table.

TRUTH-TABLE
CLK J K Q 𝐐 ̅ OPERATION
0 X X Q 𝐐 ̅
1 0 0 Q 𝐐 ̅ Previous state
1 0 1 0 1
1 1 0 1 0
1 1 1 Toggle or Race around

CMOS implementation of Clocked JK Flip-Flop using NOR gate is shown in below figure.

̅ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑸 (𝑪𝑳𝑲 𝑱 𝑸 ̅) + 𝑸 𝑸 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝑪𝑳𝑲 𝑲 𝑸) + 𝑸 ̅

Fig. 5.43: CMOS logic for Clocked JK flip-flop using NOR

5.4.4. D FLIP-FLOP:

D FLIP FLOP FROM NAND GATES (NON-CLOCKED):

Truth Table
CLK D Q 𝐐 ̅
0 0 Q Q ̅
0 1 Q Q ̅
1 0 0 1
1 1 1 0

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Unit-5 Digital Integrated Circuit Design

Fig. 5.44: D Flip Flop from NAND Gates (Non-clocked)

• ̅.
A D flip flop stores 2 bits of information at the outputs, Q and 𝐐
• ̅
The Q and 𝐐 are always opposites of each other in terms of logic state.
̅ is the inverted value of Q. Thus, if Q=1, 𝐐
𝐐 ̅ =0.
• Case i: When D=0, the output Q=0 and 𝐐 ̅ =1.
• Case ii: When D=1, the output Q=1 and 𝐐 ̅ =0.
Note:
A D flip flop really is a SR flip flop, which is a "set-reset" flip flop. The only difference is that it has
an added NOT gate in front of it. This NOT gate prevents the hold condition and the indeterminate
condition of the SR flip flop from occurring. The indeterminate condition is an especially troubling
state for the SR flip flop because it can produce unpredictable outcomes, which of course would
want to be avoided.

CMOS implementation of D Flip Flop from NAND Gates (Non-clocked) is shown in below figure.

𝑸 = ̅̅̅̅̅
𝑫𝑸 ‾ ̅ = ̅̅̅̅̅
𝑸 𝐷‾ 𝑸

Fig. 5.45: CMOS Logic for D flip flop from NAND gates (NON-CLOCKED)

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Unit-5 Digital Integrated Circuit Design
D FLIP FLOP FROM NAND GATES (CLOCKED):
In SR flip flop, the undefined input condition of SET = "0" and RESET = "0" is forbidden. It is the
drawback of the SR flip flop. The D flip-flop is designed using a gated SR flip-flop with an inverter
connected between the inputs allowing for a single input D (Data).
The D flip flop is the most important flip flop from other clocked types. It ensures that at the same
time, both the inputs, i.e., S and R, are never equal. The Delay flip-flop is designed using a gated SR
flip-flop with an inverter connected between the inputs allowing for a single input D (Data).
So, here S=D and R= 𝐃 ̅

Fig. 5.46: D Flip-Flop using NAND gates

Truth Table
CLK D Q 𝐐 ̅
0 0 Q Q ̅
0 1 Q Q ̅
1 0 0 1
1 1 1 0

The SR flip-flop requires two inputs, i.e., one to "SET" the output and another to "RESET" the
output. By using an inverter, we can set and reset the outputs with only one input.

In SR flip flop, when both the inputs are 0, that state is no longer possible. It is an ambiguity that is
removed by the complement in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input.
• With Clock =1, and input D=0, then the output Q=0 and 𝐐 ̅ =1.
• With Clock =1, and input D=1, then the output Q=1 and 𝐐 ̅ =0.
• With Clock =1, and input D=X, then the output Q=No Change and 𝐐 ̅ = No Change.
Note:
In place of Inverter we can connect one NAND gate in the above circuit.

CMOS implementation of D FLIP FLOP FROM NAND GATES (CLOCKED) is shown in below
figure.

Q = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅
(D CLK) Q ̅ ̅ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Q ̅̅̅̅̅̅̅̅̅̅
(𝐷‾ 𝐶𝐿𝐾) Q

𝑸 = ( ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ + ̅̅̅̅̅̅
𝑫 𝑪𝑳𝑲) ⋅ 𝑸 ̅ ̅ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑸 (𝑫 + ̅̅̅̅̅̅
𝑪𝑳𝑲) . 𝑸

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Unit-5 Digital Integrated Circuit Design

Fig. 5.47: CMOS Logic for Clocked D flip flop from NAND gates

D FLIP FLOP FROM NOR GATES (CLOCKED):

Truth Table
CLK D Q 𝐐 ̅
0 0 Q Q ̅
0 1 Q Q ̅
1 0 0 1
1 1 1 0

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Unit-5 Digital Integrated Circuit Design

Fig. 5.48: Clocked D Latch using NOR gates

D flip flop is an electronic device that is known as “delay flip flop” or “data flip flop” which is
used to store single bit of data. The D flip flop has two inputs, data and clock input which controls
the flip flop.

Case i: When Clock =1 (High)

The Q Output follows input i.e.
• If D = 0 then Q will be 0.
• If D = 1 then Q will be 1.
̅ output of the flip flop is complemented by the Q output.
The 𝐐
• If Q = 0 then 𝐐 ̅ will be 1.
• If Q = 1 then 𝐐 ̅ will be 0.

Case ii: When Clock = 0 (Low)

The Q Output retains its previously stored value, and ignore changes in D.

CMOS implementation of D FLIP FLOP FROM NOR GATES (CLOCKED) is shown in below figure.
𝑸 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝑫‾ . 𝑪𝑳𝑲) + 𝑸 ‾ ‾ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑸 (𝑫 . 𝑪𝑳𝑲) + 𝑸

Fig. 5.49: CMOS logic for Clocked D Latch using NOR gates

OR

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Unit-5 Digital Integrated Circuit Design
CMOS implementation of D FLIP FLOP FROM NOR GATES (CLOCKED) is shown in below figure.
𝑸 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝑫‾ . 𝑪𝑳𝑲) + 𝑸 ‾ ‾ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑸 (𝑫 . 𝑪𝑳𝑲) + 𝑸

Fig. 5.50: CMOS logic for Clocked D Latch using NOR gates

SIMPLER D FLIP-FLOP (Using 6 Transistor):

Truth Table
CLK D Q 𝐐 ̅
0 0 Q Q ̅
0 1 Q Q ̅
1 0 0 1
1 1 1 0

Fig. 5.51 a: Block diagram of CMOS logic Clocked D Latch using only 6 transistors

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Unit-5 Digital Integrated Circuit Design

Fig. 5.51 b: CMOS logic Clocked D Latch using only 6 transistors

When CLK=0 and ̅̅̅̅̅̅

𝐂𝐋𝐊 = 𝟏, the transistor M1 will be OFF and transistor M6 will be ON. There will
be a loop. This is a state of memory (Storage).
When CLK=1 and 𝐂𝐋𝐊 ̅̅̅̅̅̅ = 𝟎, the transistor M1 will be ON and transistor M6 will be OFF. There will
not be any loop.

Case i: When CLK=1, then ̅̅̅̅̅̅

𝐂𝐋𝐊 will become 0.
̅ = 0 which is given as an input to the 2nd
If D=1, then the output of the 1st CMOS inverter i.e. 𝐐
CMOS inverter. The output of the 2 CMOS inverter i.e. Q=1.
nd

Thus, the when the input D=1 and the output Q=1.

̅̅̅̅̅̅ will become 0.

Case ii: When CLK=1, then 𝐂𝐋𝐊
̅ = 1 which is given as an input to the 2nd
If D=0, then the output of the 1st CMOS inverter i.e. 𝐐
CMOS inverter. The output of the 2 CMOS inverter i.e. Q=0.
nd

Thus, when the input D=0 and the output Q=0.

Case iii: When CLK=0, then ̅̅̅̅̅̅

𝐂𝐋𝐊 will become 1, there will be a loop and again D is stored
i.e. No change in the output.
Advantages of D Flip Flop
• D flip flop is very simple to design.
• The computation speed of D flip flop is very fast compared to other flip flops.
• D flip flop requires very few components to design which makes it simple to understand.

Disadvantages of D Flip Flop

• D flip flops are glitch prone. When input varies fast, flip flop output may glitch. Digital
circuit glitches are hard to identify and fix.

Application of D Flip Flop:

• Memory: D flip flop is used to create memory circuit for holding the data.
• Registers: D flip flop is used to create register, which can hold data in digital system. By
using the D flip flop the designer can built any size of register as per the requirement.
• Counters: D flip flops are used to create the counters which counts the number of event
occurred in the digital system.
• Synchronous System: D flip flop is having in developing the synchronous system.

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Unit-5 Digital Integrated Circuit Design
5.4.6. MASTER-SLAVE D FLIP-FLOP:

Fig. 5.52: Master Slave D Flip-Flop

Fig. 5.53: CMOS Logic of Master Slave D Flip-Flop

Fig. 5.54: Non-Overlapping Clock Pulses

• A master-slave D flip-flop is a type of flip-flop circuit that stores and transfers data.
• It consists of two interconnected D flip-flops, often referred to as the master and slave
flipflops.
• The behavior of the master-slave D flip-flop can be triggered by either a positive edge or a
negative edge of a clock signal.

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Unit-5 Digital Integrated Circuit Design
• When 𝐶𝐿𝐾1 is high and 𝐶𝐿𝐾2 is low, the input is connected to the master latch whose
feedback loop is opened, while the slave latch is isolated. Thus, the output Q remains at the
value stored previously in the slave latch whose loop is now closed. The node capacitances
of the master latch are charged to the appropriate voltages corresponding to the present
value of D.
• When 𝐶𝐿𝐾1 goes low, the master latch is isolated from the input data line. Then, when
𝐶𝐿𝐾2 goes high, the feedback loop of the master latch is closed, locking in the value of D.
Further, its output is connected to the slave latch whose feedback loop is now open. The
node capacitances in the slave are appropriately charged so that when 𝐶𝐿𝐾1 goes high
again, the slave latch locks in the new value of D and provides it at the output, 𝑄 = 𝐷.
From this description, we note that at the positive transition of clock 𝐶𝐿𝐾2 the output Q adopts
the value of D that existed on the D line at the end of the preceding clock phase, 𝐶𝐿𝐾1. This output
value remains constant for one clock period. Finally, note that during the non-overlap interval
both latches have their feedback loops open and we are relying on the node capacitances to
maintain most of their charge. It follows that the nonoverlap interval should be kept reasonably
short (perhaps one-tenth or less of the clock period, and of the order of 1 ns or so in current
practice).

Implement Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐀𝐁 + 𝐂)𝐃 using CMOS logic.

Fig. 5.55: CMOS Logic for Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅

(𝐀𝐁 + 𝐂)𝐃

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