ZCU106 IP Integrator

Application

December 2018

XTP493
Revision History
Date Version Description
12/10/18 4.0 Updated for 2018.3. Works with MTA8 and MTA4 SODIMMs. Some screenshots not updated.
06/18/18 3.0 Updated for 2018.2. AR71127 fixed.
05/22/18 2.1 Added AR71127. Update Board Flow files as detailed in this Answer Record.
05/07/18 2.0 Updated for 2018.1.
12/20/17 1.0 Initial version.

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 Overview
˃ ZCU106 Board Self Test Demo
˃ Xilinx ZCU106 Board
˃ Software Requirements
˃ ZCU106 Setup
˃ ZCU106 IPI Design
˃ Compile ZCU106 IPI Design
˃ Program ZCU106
Programming the ZCU106 with Dual QSPI
Programming the ZCU106 from Vivado
˃ Run the LwIP Ethernet Design
˃ References

Note: This presentation applies to the ZCU106

 ZCU106 IPI Design Description
˃ Description
The IP Integrator (IPI) application uses an MicroBlaze system to verify board functionality. A UART
based terminal program interface offers users a menu of tests to run.
˃ Block Design Source
RDF0448 – ZCU106 IPI Design Files (2018.3 C) ZIP file

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design Description
˃ Block Design IP
Processor and Subsystems: Zynq UltraScale+ MPSoC, Processor System Reset, Concat
AXI Bus: AXI Interconnect
Memory: DDR4 SDRAM (MIG), AXI BRAM Controller, Block Memory Generator
Peripherals: AXI IIC, AXI GPIO, AXI UART16550, System Management Wizard
Other IP: diff_freq_counter, gt_freq_counter, Clocking Wizard, ILA
‒ Vivado Design Suite Tcl Command Reference Guide (UG835)
‒ Designing IP Subsystems Using IP Integrator (UG994)

Note: Presentation applies to the ZCU106

Xilinx ZCU106 Board
 ZCU106 Software Install and Board Setup
˃ Refer to XTP497 – ZCU106 Software Install and Board Setup for details on:
Software Requirements
ZCU106 Board Setup
UART Driver Install
Optional Hardware Setup

Note: Presentation applies to the ZCU106

 ZCU106 Setup
˃ Unzip the RDF0448 - ZCU106 IPI Design Files (2018.3 C) ZIP file, and extract
to your C:\ drive:

Note: Presentation applies to the ZCU106

 ZCU106 Setup
˃ Open a Tera Term window for the Interface 0 COM Port
˃ Set the baud to 115200

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ Open a Vivado Tcl Shell:
Start → All Programs → Xilinx Design Tools → Vivado 2018.3 →
Vivado 2018.3 Tcl Shell

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ Download the blink bitstream
˃ In the Vivado Tcl Shell type:
cd C:/zcu106_ipi/ready_for_download
exec xsdb ipi_app_download.tcl

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ View the initial IPI Test screen

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ UART Test
Type “1” to start the UART Test
After each test, press any key to return to the main menu

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ LED Test
Type 2 to begin LED Test
˃ View Walking 1’s pattern on GPIO LEDs

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ IIC Test
Type 3 to begin IIC Test

Note: IIC test requires optional XM107 boards

and SFP Loopback modules
 ZCU106 IPI Design
˃ Timer/SCUGIC Test
Type 5 to begin Timer Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ CAN Bus Test
Type 6 to begin CAN Bus Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ GPIO Switch Test
Set 8-position PL DIP Switch (SW13)
Type 7 to begin GPIO Switch Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ DDR4 External Memory Test
Type 8 to begin PS DDR4 Memory Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ DDR4 External Memory Test
Type 9 to begin PL DDR4 Memory Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ BRAM Internal Memory Test
Type A to begin PL BRAM Memory Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ Button Test
Type B to begin Button Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ Clock Test
This test requires the optional SMA cables, 148.5 MHz clock source and XM107 boards
The clocks must be set up as detailed in XTP497
Type C to begin Clock Test

Note: Presentation applies to the ZCU106

ZCU106 IPI Design
˃ Clock Test
Without the proper set up, optional SMA cables, clock source, and XM107 boards, several clocks will
not show a correct frequency
The FMC HPC0 Si570 must be set to 163 MHz after a power cycle
The SFP Si5328 must be set to 163 MHz after a power cycle
The User SMA MGT clock must be connected to a 148.5 MHz clock source
 ZCU106 IPI Design
˃ PMOD Loopback Test
This test requires the optional PMOD jumpers
Type D to begin PMOD Loopback Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ PS Push Button Test (SW19)
Type E to begin PS Push Button Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ PS LED Test
Type F to begin PS LED Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ System Monitor Test
Type G to begin System Monitor Test

Note: Presentation applies to the ZCU106

 ZCU106 IPI Design
˃ PS Ethernet Test
Type H to begin PS Ethernet Loopback Test

Note: Presentation applies to the ZCU106

Compile ZCU106 IPI Design
 Compile ZCU106 IPI Design
˃ Open Vivado
Start → All Programs → Xilinx Design Tools → Vivado 2018.3 → Vivado 2018.3
˃ Select Open Project

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ Open the ZCU106 Design:
C:\zcu106_ipi\zcu106_ipi.xpr

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ The design is fully implemented; you can recompile, or export to SDK
To recompile, right-click synth_1, select Reset Runs then Generate Bitstream

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ Once done, both the Synthesis and Implementation will have green check
marks

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ The IPI Design has been implemented with IP Integrator (IPI)
˃ Click Open Block Design

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ All the IP Blocks used in the design can be seen in this view
˃ Click Open Implemented Design

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ View Implemented Design

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ Select File → Export → Export Hardware
˃ Click OK

Note: Presentation applies to the ZCU106

 Compile ZCU106 IPI Design
˃ Select File → Launch SDK
˃ Click OK

Note: Presentation applies to the ZCU106

 Compile ZCU106 Software in SDK
˃ SDK Software Compile - Build ELF files in SDK
Select Project → Clean…

Note: Presentation applies to the ZCU106

 Compile ZCU106 Software in SDK
˃ All files compiled

Note: Presentation applies to the ZCU106

Creating a BOOT Image
 Creating a BOOT Image
˃ Select blinkbist
˃ Select Xilinx → Create Boot Image

Note: Presentation applies to the ZCU106

Creating a BOOT
Image
Create the BlinkBIST MCS
Uses the default BIF file
The file paths should be in
this order:
zynq_mp_fsbl.elf
system_wrapper.bit
blinkbist.elf
If any of these files are missing,
add them
Click Create Image
 Creating a BOOT Image
˃ If necessary, select the Bootgen console

Note: Presentation applies to the ZCU106

 Creating a BOOT Image
˃ The BOOT.mcs is created

Note: Presentation applies to the ZCU106

Program ZCU106
 Programming the ZCU106 with Dual QSPI
˃ Cycle ZCU106 power
˃ Select Xilinx → Program Flash

Note: Presentation applies to the ZCU106

 Programming the ZCU106 with Dual QSPI
˃ Select the BOOT.mcs as the Image File
˃ Select qspi_dual_parallel
˃ Select the zynq_mp_fsbl.elf as the FSBL File
˃ Select Verify after Flash
˃ Click Program

Note: Presentation applies to the ZCU106

Programming the ZCU106 with Dual QSPI
˃ Set SW6 to 0100 (0 = GND, Position 1 → Position 4) (Up, Down, Up, Up) to
boot from QSPI
 Programming the ZCU106 with Dual QSPI
˃ Cycle power, and the Blink BIST program begins running
˃ Follow the steps in the UG426, ZCU106 Quick Start Guide

Note: Presentation applies to the ZCU106

 Program ZCU106 with IPI Design
˃ Once the Quick Start Guide steps are complete, you can view the IPI App in
UART0 window

Note: Presentation applies to the ZCU106

Programming the ZCU106 from Vivado
˃ Set SW6 to 0000 (0 = GND, Position 1 → Position 4) (All Up)
 Programming the ZCU106 from Vivado
˃ Copy the files to the ready_for_download directory
˃ Open a Windows CMD prompt and type:
cd C:\zcu106_ipi\ready_for_download
copy_files.bat

Note: Presentation applies to the ZCU106

 Programming the ZCU106 from Vivado
˃ Download the IPI bitstream
˃ In the Vivado Tcl Shell type:
cd C:/zcu106_ipi/ready_for_download
exec xsdb ipi_app_download.tcl

Note: Presentation applies to the ZCU106

 Programming the ZCU106 from Vivado
˃ The IPI Application runs in the terminal window

Note: Presentation applies to the ZCU106

Run the LwIP Ethernet Design
 Run the LwIP Ethernet Design
˃ Download the LwIP bitstream
˃ In the Vivado Tcl Shell type:
exec xsdb lwip_download.tcl

Note: Presentation applies to the ZCU106

 Run the LwIP Ethernet Design
˃ View LwIP echo server screen

Note: Presentation applies to the ZCU106

 Run the LwIP Ethernet Design
˃ From a DOS window on the PC Host, enter the command:
ping 192.168.1.10
Ping from PC host 192.168.1.2 to ZCU106 target 192.168.1.10

Note: Don’t ping LwIP while it is initializing

References
References
˃ IP Integrator Documentation
Vivado Design Suite Tcl Command Reference Guide – UG835
‒ https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/
ug835-vivado-tcl-commands.pdf
Designing IP Subsystems Using IP Integrator – UG994
‒ https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/
ug994-vivado-ip-subsystems.pdf
˃ Vivado Release Notes
Vivado Design Suite User Guide - Release Notes – UG973
‒ https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/
ug973-vivado-release-notes-install-license.pdf
Vivado Design Suite 2018 - Vivado Known Issues
‒ https://www.xilinx.com/support/answers/70860.html
Documentation
Documentation
˃ Zynq UltraScale+
Zynq UltraScale+ MPSoC
‒ http://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html
˃ ZCU106 Documentation
Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit
‒ https://www.xilinx.com/products/boards-and-kits/zcu106.html
ZCU106 Board User Guide – UG1244
‒ https://www.xilinx.com/support/documentation/boards_and_kits/zcu106/
ug1244-zcu106-eval-bd.pdf
ZCU106 Evaluation Kit Quick Start Guide User Guide – XTP472
‒ https://www.xilinx.com/support/documentation/boards_and_kits/zcu106/
xtp472-zcu106-quickstart.pdf