LABORATORY 2 – DIGITAL LOGIC COMPONENTS

LABORATORY 2
DIGITAL LOGIC COMPONENTS
OBJECTIVES

No. Objectives Requirements

 Complete truth table,
1 Logic gates:
draw schematic, and symbol of
 NAND2.
logic gates.
 NOR2.
 Simulate including DC
 EX-OR2.
analysis, and transient.
 Create layout, and check
DRC/LVS.
 Complete truth table,
2 Combinational logic circuits:
draw schematic, and symbol of
 2-to-1 Channel Multiplexer.
logic gates.
 8-to-3 Bit Priority Encoder.
 Simulate including DC
analysis, and transient.
 Complete truth table,
3 Sequential logic circuits:
draw schematic, and symbol of
 D-type latch.
logic gates.
 D-type Flip-Flop.
 Simulate including DC
analysis, and transient.
 Find clock speed of these
components.
 Known definitions, and
how to measure setup time, and
hold time.

EXPERIMENT 1

Objective: Known how to design logic gates using CMOS technology.

Requirement: Student must complete the truth table of NAND2, NOR2, and EX-OR2,
then verify them by running simulation.

Instruction: Student may present their work following the template shown below

a. Schematic:
 Truth table of inverter (INV):

Department of Electronics Page | 1

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

INPUT OUTPUT

A Y

Table 1 Truth table of inverter

 Schematic:

Figure 1 Schematic of INV

 Symbol of INV:

Figure 2 Symbol of INV

In fact, at the beginning of this symbol, Cadence Virtuoso just generates a rectangle
with pins you arranged before. You use drawing tools to create a symbol for inverter
symbol. Moreover, you make sure to check and save your symbol.

b. DC Analysis simulation:

Department of Electronics Page | 2

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

Use ADE-L to simulate the DC response of an INV gate. Apply an input signal in
the form of a RAMP voltage ranging from 0-1V (or sweep the input voltage signal from
0-1V) and observe the output response. The circuit parameters are configured as follows:
Parameters Value

1
1
[0, 1]

Table 2 Parameters in DC analysis

During the simulation process, students record the following two results: output voltage
values at various values of with a 0.1V step and plot the curve of . Besides,
students can decrease step to draw curve of more precise.
( ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
( )

Table 3 The output voltage values at various values of with 0.1V step.

Figure 3 ’s curve with respect to

c. Transient simulation:

Use ADE-L to perform a time-domain simulation to verify the operation according

to the truth table of the INV gate, represented in the form of an output waveform. To
conduct this simulation, assemble a testbench circuit consisting of a pulse source
(vpulse), an output capacitor, and provide power to the circuit (vdc). The circuit
parameters are configured as follows:

Department of Electronics Page | 3

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

Parameters Value Note

1

100

Voltage 1 0

Voltage 2 1

Rise time 1

Fall time 1 Paramters for vpulse

Delay 0

Pulse width 1

Period 2

Table 4 Parameters for transient simulation.

Testbench circuit for INV

Figure 4 Testbench circuit INV generated by (left) MOS transistor (right) VerilogA.

During simulation process, students record input and output waveform. Then, students
measure some timing measurements.

Department of Electronics Page | 4

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

Parameters Result

– Rising time (10% − 90%)

– Falling time (90% − 10%)

– Rising propagation delay (90% − 50%)

– Falling propagation delay (10% − 50%)

– Average propagation delay (50% - 50%)

Dynamic power

Static power

Table 5 Measurement results of INV

d. Layout design of INV:

 Stick diagram.
 Complete layout of INV checked DRC, and LVS.

Check: You must show these results in your report.

 The waveform to prove the circuit works correctly. Moreover, students have to
apply these parameters in vpulse, then simulate your design.

In1 In2

Voltage 1 0 0

Voltage 2 1 1

Period 4n 2n

Delay time 0.65n 0.8n

Rise time 1p 1p

Fall time 1p 1p

Pulse width 2n 1n

Table 6 Testbench for NAND2/NOR2/EX-OR2 (using vpulse in analogLib).

 Using simulation result above, students measure some parameters shown in

Table 5 for each logic gate is done.

(Hint: you can use marker (hotkey “M”) along with differential mode (hotkey “D”) or
calculator to measure)

Department of Electronics Page | 5

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

EXPERIMENT 2

Objective: Design some combinational logic circuits re-using logic components designed
in experiment 3 (lab1), and experiment 1 (lab 2).

Requirement: You simulate 2-to-1 channel multiplexer, and an 8-to-3 Bit Priority
encoder.

Instructions:

 There are three ways to design a multiplexer, such as: transmission gate,
compound gate, and tristate inverter. First, students have to complete the truth table of
multiplexer 2-to-1. Second, students simulate and verify the schematics shown in
Figure 6. Finally, students measure some parameters required as shown in Table 6.

(a) (b) (c)

Figure 5 MUX 2-to-1 using (a) transmission gate (b) compound gate (c) tristate inverter

MULTIPLEXER 2-to-1

Transmission
Compound gate Tristate inverter
gate

- Rising time (10%-90%)

- Falling time (90%-10%)

– Rising propagation delay

(90%-50%)

– Falling propagation delay

(10%-50%)

– Average propagation delay

(50% - 50%)

Power consumption

Table 7 Measurement results of MUX 2-to-1

Department of Electronics Page | 6

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

 Unlike a multiplexer that selects one individual data input line and then sends
that data to a single output line or switch. The job of a priority encoder is to produce a
binary output address for the input with the highest priority.

Figure 6 Block diagram and truth table of 8-to-3 bit priority encoder (P-encoder).

Check: You must show in your report these results.

 The waveform to prove the 2-to-1 channel multiplexer circuit works correctly,
and measure parameters shown in Table 7.
 The waveform to prove the 8-to-3 bit priority encoder circuit works correctly.

EXPERIMENT 3

Objective: Review the basic sequential logic components – latch and flip-flop (D-type
latch and D-type flip-flop).

Requirements:

 Distinguish latch and flip-flop by studying D-type latch and D-type flip-flop
using transmission gate. Moreover, you will know definition of setup and hold time, and
analyze them in this design.
 Study three designs of D-type flip-flop and learn how to measure setup and hold
time of these designs.

Instructions:

 There are many methods to design D-type latch and flip-flop. First, students can
review these operations using transmission gate structure shown in Figure 7 and
Figure 8. Sketching hand drawing waveform at each node to observe these operations is
a good idea.

Department of Electronics Page | 7

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

Figure 7 Schematic of D-type latch using transmission gate.

Figure 8 Schematic of D-type Flip-flop using transmission gate.

 Figure 9, Figure 10, and Figure 11 present three design methods of D-type
filp-flop.

Figure 9 Schematic of D-type Flip-Flop negative edge triggered using C2MOS

structure.

Department of Electronics Page | 8

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

Figure 10 Schematic of D-type Flip-Flop positive edge triggered with Preset using
TSPC – True Single Phase Clock – structure.

Figure 11 Schematic of D-type Flip-Flop dual edge triggered.

 In this experiment, students use Cadence Virtuoso to measure the setup and hold
time of these D-type flip-flop (from Figure 9 to 11). Recall that the setup and hold time
are the minimum time before and after the rising clock edge the input signal must
remain constant to store the signal and to generate a stable output, respectively.

Department of Electronics Page | 9

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

Figure 12 Overview measurement setup and hold time method.

Figure 13 Waveform describing measurement setup time method.

 Students can measure setup and hold time using this method: Shift input D
closer to rising CLK signal until Q output is incorrect.

Check: You must show in your report these results.

 Simulate D-type latch and flip-flop to verify your hand drawing waveform of
Figure 7 and Figure 8.

Define paths to calculate setup and hold time.

 Simulate three D-type flip-flop designs shown in Figure 9, Figure 10, and
Figure 11.

Measure some timing parameters, and power consumption of each design. Then,
consider these results.

Department of Electronics Page | 10

Digital IC Design Laboratory

LABORATORY 2 – DIGITAL LOGIC COMPONENTS

D Flip-flop

C2MOS TSPC DET

– Setup time

− Hold time

– Rising propagation delay

(90%-50%)

– Falling propagation delay

(10%-50%)

– Average propagation delay

(50% - 50%)

Power consumption

Table 8 Comparison results between three D-type flip-flop designs

----------------------------------------------------------------------------------------------

 ONE MORE THING…

After completing this lab, please answer the following questions.

 How much time did you spend completing this lab?

 Is there any problem when you do? Please let me know.

Department of Electronics Page | 11

Digital IC Design Laboratory