MIT-WPU

Introduction to Electronics
Engineering
ECE 101 4-2-4
Field Effect Transistors and
CMOS
Field Effect Transistors and CMOS
 Introduction to field effect transistors (FET),
 JFET: construction, working and
characteristics,
 MOSFET: construction, working
 Characteristics of D-MOSFET and E-
MOSFET,
 Introduction to CMOS,
 MOSFET as amplifier,
 MOSFET as switch.
Objectives

 In the end of this chapter, you‟ll be able

– to understand and recognize the following two
types of FET; JFET and MOSFET
– To discuss and differentiate the operation of each
two types of FET
 FET
FET’s (Field – Effect Transistors) are much like BJT’s (Bipolar Junction
Transistors).
Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits
Differences:
• FET’s are voltage controlled devices whereas BJT’s are current
controlled devices.
• FET’s also have a higher input impedance, but BJT’s have higher
gains.
• FET’s are less sensitive to temperature variations and because of there
construction they are more easily integrated on IC’s.
• FET’s are also generally more static sensitive than BJT’s.
 Types of Field Effect Transistors
(The Classification)

JFET n-Channel JFET

FET
p-Channel JFET
(Junctional FET)

MOSFET (Metal Oxide FET)

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET
JFET Construction

There are two types of JFET’s: n-

channel and p-channel.
The n-channel is more widely used.

There are three terminals: Drain (D)

and Source (S) are connected to n-
channel
Gate (G) is connected to the p-type
material
Basic Operation of JFET

JFET operation can be compared to a water analogy:

The source of water pressure – accumulated electrons at the

negative pole of the applied voltage from Drain to Source.
The drain of water – electron deficiency (or holes) at the
positive pole of the applied voltage from Drain to Source.
The control of flow of water – Gate voltage that controls the
width of the n-channel, which in turn controls the flow of
electrons in the n-channel from source to drain.
N-Channel JFET Circuit Layout

How JFET
works?
JFET Symbols
MOST LIKELY QUESTIONS

 Name three terminals of JFET

 Why FET is called voltage controlled device?
 Why FET is called unipolar device?
 Explain the operation of JFET.
 Explain characteristics of JFET.
 Compare Pinch off and cut off voltage.
 Define JFET parameters.
JFET Operating Characteristics

There are three basic operating conditions for a JFET:

A. VGS = 0, VDS increasing to some positive value

B. VGS < 0, VDS at some positive value

C. Voltage-Controlled Resistor
 A. VGS = 0, VDS increasing to some
positive value

Three things happen when VGS = 0 and VDS is

increased from 0 to a more positive voltage:
• The depletion region between p-gate and n-
channel increases as electrons from n-channel
combine with holes from p-gate.
• Increasing the depletion region, decreases the
size of the n-channel which increases the
resistance of the n-channel.
• But even though the n-channel resistance is
increasing, the current (ID) from Source to
Drain through the n-channel is increasing.
This is because VDS is increasing.
 Pinch-off

If VGS = 0 and VDS is further increased to a

more positive voltage, then the depletion zone
gets so large that it pinches off the n-channel.
Hence, no further increase in drain current
and ID becomes essentially constant.

Definition: Pinch off voltage

For VGS = 0 V, the value of VDS at which
ID becomes essentially constant is the
pinch off voltage
 Saturation

At the pinch-off point:

• any further increase in VDS

does not produce any increase in
ID.
VDS at pinch-off is denoted as
Vp.
• ID is at saturation or
maximum. It is referred to as
IDSS.
• The ohmic value of the
channel is at maximum.
JFET modeling when ID=IDSS, VGS=0,
VDS>VP

JFET acts as
constant
current
source.
B. VGS < 0, VDS at some positive value

As VGS becomes more

negative the depletion
region increases.
 ID < IDSS

As VGS becomes more negative:

• the JFET will pinch-off at a lower
voltage (Vp).
• ID decreases (ID < IDSS) even
though VDS is increased.
• Eventually ID will reach 0A. VGS
at this point is called Vp or
VGS(off).
• Also note that at high levels of
VDS the JFET reaches a breakdown
situation. ID will increases
uncontrollably if VDS > VDSmax.
Characteristic curves for N-channel
JFET
C. Voltage-Controlled Resistor

The region to the left of the pinch-

off point is called the ohmic region.
The JFET can be used as a variable
resistor, where VGS controls the
drain-source resistance (rd). As VGS
becomes more negative, the
resistance (rd) increases.

ro
rd 
(1 VGS )2
VP

Explain application of FET as VDR or VVR

Transfer Characteristics

The transfer characteristic of input-to-output is not as straight forward in a

JFET as it was in a BJT.

In a BJT,  indicated the relationship between IB (input) and IC (output).

In a JFET, the relationship of VGS (input) and ID (output) is a little more

complicated:
VGS 2
ID  IDSS(1 )
VP
 Transfer Curve

From this graph it is easy to determine the value of ID for a given value of VGS.
 p-Channel JFETS

p-Channel JFET acts the same as the n-channel JFET, except the polarities and currents are
reversed.
 P-Channel JFET Characteristics

As VGS increases more positively:

• the depletion zone increases
• ID decreases (ID < IDSS)
• eventually ID = 0A
Also note that at high levels of VDS the
JFET reaches a breakdown situation. ID
increases uncontrollably if VDS > VDSmax.
Case Construction and Terminal Identification

This information is also available on the specification sheet.

DRAWBACKS OF JFET

 Gate needs to be Reverse biased for proper

operation of the device.
 i.e. we can only decrease width of the
channel (i.e. decrease the conductivity of
channel)
 This type of operation is referred to as
“Depletion Mode operation”.
MOSFETs

MOSFETs (Metal Oxide Semiconductor FET) have

characteristics similar to JFETs and additional
characteristics that make then very useful.

There are 2 types:

• Depletion-Type MOSFET
• Enhancement-Type MOSFET
 Depletion-Type n channel MOSFET Construction

The Drain (D) and Source (S) connect to the to n-doped regions. These N-doped regions
are connected via an n-channel. This n-channel is connected to the Gate (G) via a thin
insulating layer of SiO2. The n-doped material lies on a p-doped substrate that may have an
additional terminal connection called SS.
Basic Operation
VGS< 0
 Basic Operation
A Depletion MOSFET can operate in two modes: Depletion or Enhancement mode.
Depletion-type MOSFET in Depletion Mode

Depletion mode
The characteristics are similar to the JFET.
When VGS = 0V, ID = IDSS
When VGS < 0V, ID < IDSS
The formula used to plot the Transfer Curve still applies:
VGS 2
ID  IDSS(1 ) [Formula 5.3]
VP
Depletion-type MOSFET in Enhancement Mode

Enhancement mode
VGS > 0V, ID increases above IDSS
The formula used to plot the ID  IDSS(1
VGS 2
)
Transfer Curve still applies: VP
(note that VGS is now a positive polarity)
 p-Channel Depletion-Type MOSFET

The p-channel Depletion-type MOSFET is similar to the n-channel except that the voltage
polarities and current directions are reversed.
Symbols
 Enhancement-Type MOSFET Construction

The Drain (D) and Source (S) connect to the to n-doped regions. These n-doped regions
are connected via an n-channel. The Gate (G) connects to the p-doped substrate via a
thin insulating layer of SiO2. There is no channel. The n-doped material lies on a p-
doped substrate that may have an additional terminal connection called SS.
Operation
 Basic Operation
The Enhancement-type MOSFET only operates in the enhancement mode.

VGS is always positive.

As VGS increases, ID increases.
But if VGS is kept constant and VDS is increased, then ID saturates (IDSS) (Pinch
off process)
The saturation level, VDSsat is reached. VDsat VGS VT
Pinch off
 Transfer Curve

To determine ID given VGS: I D  k (VGS VT ) 2

where VT = threshold voltage or voltage at which the MOSFET
turns on.
k = constant found in the specification sheet
k can also be determined by using values at a specific point and
the formula: ID(on)
k
(VGS(ON)  VT) 2
VDSsat can also be calculated:
VDsat VGS VT
 p-Channel Enhancement-Type MOSFETs

The p-channel Enhancement-type MOSFET is similar to the n-channel except that

the voltage polarities and current directions are reversed.
Symbols
 MOSFET as an amplifier

The E-MOSFET is a normally off device. The n-channel device is biased

on by making the gate positive with respect to the source. A voltage-
divider biased E-MOSFET amplifier is shown.
ID

Enhancement

+VDD

Q
RD IDQ
C3
R1 Vout
C1 Id

RL VGS
0 VGS(th)
Vin C2
R2 RS
Vgs

VGSQ
 MOSFET as an amplifier

The E-MOSFET amplifier in

Example 9-8 is illustrated in
Multisim using a 2N7000 MOSFET.
Introduction

 Integrated circuits: many transistors on one

chip.
 Very Large Scale Integration (VLSI): very
many
 Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors

0: Introduction Slide 45
Silicon Lattice

 Transistors are built on a silicon substrate

 Silicon is a Group IV material
 Forms crystal lattice with bonds to four
neighbors
Si Si Si

Si Si Si

Si Si Si
0: Introduction Slide 46
Dopants

 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si
0: Introduction Slide 47
p-n Junctions

 A junction between p-type and n-type

semiconductor forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

0: Introduction Slide 48
nMOS Transistor

 Four terminals: gate, source, drain, body

 Gate – oxide – body stack looks like a
capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor
Source Gate Drain
(MOS) Polysilicon
capacitor SiO2

– Even though gate is

no longer made of metal n+ n+
0: Introduction p Slidebulk
49 Si
nMOS Operation

 Body is commonly tied to ground (0 V)

 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
0: Introduction S D Slide 50
p bulk Si
nMOS Operation Cont.

 When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
0: Introduction
p bulk Si Slide 51
pMOS Transistor

 Similar, but doping and voltages reversed

– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+
0: Introduction Slide 52
n bulk Si
Power Supply Voltage

 GND = 0 V
 In 1980‟s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

0: Introduction Slide 53
MOSFET as Switch

 E-MOSFETs are generally used for switching

applications because of their threshold
characteristic, VGS(th).
 When the gate-to-source voltage is less than the
threshold value, the MOSFET is off.
 When the gate-to-source voltage is greater than the
threshold value, the MOSFET is on.
 When VGS is varied between VGS(th) and VGS(on),
the MOSFET is being operated as a switch.
The Ideal Switch (NMOSFET)

 When the gate voltage of the n-channel MOSFET is

1, the gate is more positive than the source by an
amount exceeding VGS(th). The MOSFET is on and
appears as a closed switch between the drain and
source.
 When the gate voltage is zero, the gate-to-source
voltage is 0 V. The MOSFET is off and appears as
an open switch between the drain and source.
The Ideal Switch (PMOSFET)

 When the gate voltage of the p-channel MOSFET is

0 V, the gate is less positive than the source by an
amount exceeding VGS(th). The MOSFET is on and
appears as a closed switch between the drain and
source.
 When the gate voltage is 1, the gate-to-source
voltage is 0 V. The MOSFET is off and appears as
an open switch between the drain and source.
Transistors as Switches

 We can view MOS transistors as electrically

controlled switches
 Voltage at gate controls path
g=0
from source
g=1
to
drain d d
d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
0: Introduction Slide 57
The Analog Switch

 MOSFETs are commonly used for switching analog

signals. Basically, a signal applied to the drain can
be switched through to the source by a voltage on
the gate.
 A major restriction is that the signal level at the
source must not cause the gate-to-source voltage to
drop below VGS(th).
 The signal at the drain is connected to the source
when the MOSFET is turned on by a positive VGS
and is disconnected when VGS is 0.
 When the analog switch is on, the minimum gate-to
source voltage occurs at the negative peak of the
signal.
 The difference in VG and -Vp(out) is the gate-to-
source voltage at the instant of the negative peak
and must be equal to or greater than VGS(th) to
keep the MOSFET in conduction.
VGS = VG - Vp(out) >= VGS(th)
Numerical

 A certain analog switch uses an n-channel MOSFET with

VGS(th) 2 V. A voltage of 5 V is applied at the gate to turn the
switch on. Determine the maximum peak-to-peak input signal
that can be applied, assuming no voltage drop across the
switch.
Solution: The difference between the gate voltage and the
negative peak of the signal voltage must equal or exceed the
threshold voltage. For maximum Vp(out),
VG - Vp(out) = VGS(th)
Vp(out) = VG - VGS(th) = 5 V - 2 V = 3 V
Vpp(in) = 2Vp(out) = 2(3 V) = 6 V
 Signal Strengths Signals such as 1 and 0 have strengths,
measures ability to sink or source current VDD and GND.
Under the switch abstraction, G has complete control and S
and D have no effect.
 In reality, the gate can turn the switch on only if a potential
difference of at least Vt exists between the G and S.
 Thus signal strengths are related to Vt and therefore P and N
MOSFETs produce signals with different strengths.
 Strong 1: VDD, Strong 0: GND,
 Weak 1: (~VDD –Vt ) Weak 0 :(~GND + Vt ).
 PMOS gives strong „1‟ and weak „0‟.
 NMOS gives strong „0‟ and weak „1‟.
CMOS Inverter

A Y VDD
0
1
A Y
A Y

GND
0: Introduction Slide 63
CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

A Y ON

GND
0: Introduction Slide 64
CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

A Y OFF

GND
0: Introduction Slide 65
Why CMOS Inverter?

 A major advantage of CMOS is that it consumes very

little dc power.
 Because the MOSFETs are in series and one of
them is always off, there is essentially no current
from the dc supply in the quiescent state.
 When the MOSFETs are switching, there is current
for a very short time because both transistors are on
during this very short transition from one state to the
other.
 CMOS

CMOS – Complementary MOSFET p-channel and n-channel MOSFET on the same

substrate.

Advantage:
• Useful in logic circuit designs
• Higher input impedance
• Faster switching speeds
• Lower operating power levels
Resource Material for the topic
 Reference Books:
Floyd Thomas, Electronic Devices, Prentice
Hall, 9th Edition 2012
 Links to Useful Videos:
1.Lecture series on diode, transistor, JFET
http://nptel.ac.in/courses/117103063/2
 Links to Useful Resource material: