Advanced Information

CAT25C32/64
32K/64K-Bit SPI Serial CMOS E2PROM
FEATURES
■ 1,000,000 Program/Erase Cycles
■ 10 MHz SPI Compatible
■ 100 Year Data Retention
■ 1.8 to 6.0 Volt Operation
■ Self-Timed Write Cycle
■ Hardware and Software Protection
■ 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOPand
■ Zero Standby Current
20-Pin TSSOP
■ Low Power CMOS Technology
■ 64-Byte Page Write Buffer
■ SPI Modes (0,0 &1,1)
■ Block Write Protection
■ Commercial, Industrial and Automotive – Protect 1/4, 1/2 or all of E2PROM Array
Temperature Ranges
DESCRIPTION
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS required to access the device. The HOLD pin may be
E2PROM internally organized as 4Kx8/8Kx8 bits. used to suspend any serial communication without
Catalyst’s advanced CMOS Technology substantially resetting the serial sequence. The CAT25C32/64 is
reduces device power requirements. The CAT25C32/ designed with software and hardware write protection
64 features a 64-byte page write buffer. The device features including Block write protection. The device is
operates via the SPI bus serial interface and is enabled available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
though a Chip Select (CS). In addition to the Chip Select, 20-pin TSSOP packages.
the clock input (SCK), data in (SI) and data out (SO) are

PIN CONFIGURATION BLOCK DIAGRAM

SOIC Package (S) TSSOP Package (U14) TSSOP Package (U20)

CS 1 8 VCC CS 1 14 VCC NC 1 20 NC SENSE AMPS

SO 2 13 HOLD CS 2 19 VCC SHIFT REGISTERS
SO 2 7 HOLD NC 12
3 NC SO 3 18 HOLD
WP 3 6 SCK NC 4 11 NC SO 4 17 HOLD
VSS 4 5 SI NC 5 10 NC NC 5 16 NC WORD ADDRESS COLUMN
WP 6 9 SCK NC 6 15 NC BUFFERS DECODERS
VSS 7 8 SI WP 7 14 SCK
VSS 8 13 SI
DIP Package (P) NC 9 12 NC SO I/O
CS 1 8 VCC NC 10 11 NC SI CONTROL
CONTROL LOGIC

SO 2 7 HOLD CS E2PROM
WP 3 6 SCK SPI XDEC ARRAY
WP CONTROL
VSS 4 5 SI HOLD LOGIC
SCK
PIN FUNCTIONS BLOCK
PROTECT
Pin Name Function LOGIC

SO Serial Data Output DATA IN

STORAGE
SCK Serial Clock
HIGH VOLTAGE/
WP Write Protect TIMING CONTROL
STATUS
VCC +1.8V to +6.0V Power Supply REGISTER
VSS Ground

CS Chip Select

SI Serial Data Input

HOLD Suspends Serial Input

NC No Connect

© 1999 by Catalyst Semiconductor, Inc. Doc No. 25087-00 8/99 SPI-1

Characteristics subject to change without notice
CAT25C32/64 Advanced Information

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
Voltage on any Pin with of the device at these or any other conditions outside of
Respect to VSS1) ................... –2.0V to +VCC +2.0V those listed in the operational sections of this specifica-
VCC with Respect to VSS ................................ –2.0V to +7.0V tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
Package Power Dissipation mance and reliability.
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA

RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
NEND(3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR(3) Data Retention 100 Years MIL-STD-883, Test Method 1008
VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC1 Power Supply Current 10 mA VCC = 5V @ 10MHz
(Operating Write) SO=open; CS=Vss
ICC2 Power Supply Current 2 mA VCC = 5.0V
(Operating Read) FCLK = 10MHz
ISB Power Supply Current 0 µA CS = VCC
(Standby) VIN = VSS or VCC
ILI Input Leakage Current 2 µA
ILO Output Leakage Current 3 µA VOUT = 0V to VCC,
CS = 0V
VIL(3) Input Low Voltage -1 VCC x 0.3 V
VIH (3) Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage 0.4 V 4.5V≤VCC<5.5V
IOL = 3.0mA
VOH1 Output High Voltage VCC - 0.8 V
IOH = -1.6mA

VOL2 Output Low Voltage 0.2 V 1.8V≤VCC<2.7V

VOH2 Output High Voltage VCC-0.2 V IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

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Advanced Information CAT25C32/64

Figure 1. Sychronous Data Timing

tCS
VIH

CS
VIL
tCSH
tCSS
VIH
SCK tWH tWL
VIL
tSU tH
VIH
SI VALID IN
VIL
tRI
tFI

tV tHO tDIS
VOH HI-Z HI-Z
SO
VOL

Note: Dashed Line= mode (1, 1) — — — —

A.C. CHARACTERISTICS

Limits
Vcc= VCC = VCC =
1.8V-6.0V 2.5V-6.0V 4.5V-5.5V Test
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions
tSU Data Setup Time 50 50 20 ns
tH Data Hold Time 50 50 20 ns
tWH SCK High Time 250 125 40 ns
tWL SCK Low Time 250 125 40 ns
fSCK Clock Frequency DC 1 DC 3 DC 10 MHz
tLZ HOLD to Output Low Z 50 50 50 ns
tRI(1) Input Rise Time 2 2 2 µs
tFI(1) Input Fall Time 2 2 2 µs CL = 50pF

tHD HOLD Setup Time 100 100 40 ns

tCD HOLD Hold Time 100 100 40 ns
tWC Write Cycle Time 10 10 5 ms
tV Output Valid from Clock Low 250 250 80 ns
tHO Output Hold Time 0 0 0 ns
tDIS Output Disable Time 250 250 75 ns
tHZ HOLD to Output High Z 150 100 50 ns
tCS CS High Time 500 250 200 ns
tCSS CS Setup Time 500 250 100 ns
tCSH CS Hold Time 500 250 100 ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.

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CAT25C32/64 Advanced Information

FUNCTIONAL DESCRIPTION CS
CS: Chip Select

The CAT25C32/64 supports the SPI bus data transmis- CS is the Chip select pin. CS low enables the CAT25C32/
sion protocol. The synchronous Serial Peripheral Inter- 64 and CS high disables the CAT25C32/64. CS high
face (SPI) helps the CAT25C32/64 to interface directly takes the SO output pin to high impedance and forces
with many of today’s popular microcontrollers. The the devices into a Standby Mode (unless an internal
CAT25C32/64 contains an 8-bit instruction register. write operation is underway). The CAT25C32/64 draws
(The instruction set and the operation codes are de- ZERO current in the Standby mode. A high to low
tailed in the instruction set table) transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
After the device is selected with CS going low, the first sequence is what initiates an internal write cycle.
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK. WP
WP: Write Protect
The first byte contains one of the six op-codes that define WP is the Write Protect pin. The Write Protect pin will
the operation to be performed. allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
PIN DESCRIPTION register are inhibited. WP going low while CS is still low
SI: Serial Input will interrupt a write to the status register. If the internal
SI is the serial data input pin. This pin is used to input all write cycle has already been initiated, WP going low will
opcodes, byte addresses, and data to be written to the have no effect on any write operation to the status
25C32/64. Input data is latched on the rising edge of the register. The WP pin function is blocked when the WPEN
serial clock. bit is set to 0.

SO: Serial Output HOLD

HOLD: Hold
SO is the serial data output pin. This pin is used to The HOLD pin is used to pause transmission to the
transfer data out of the 25C32/64. During a read cycle, CAT25C32/64 while in the middle of a serial sequence
data is shifted out on the falling edge of the serial clock. without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
SCK: Serial Clock is low. The SO pin is in a high impedance state during the
SCK is the serial clock pin. This pin is used to synchro- time the part is paused, and transitions on the SI pins will
nize the communication between the microcontroller be ignored. To resume communication, HOLD is brought
and the 25C32/64. Opcodes, byte addresses, or data high, while SCK is low. (HOLD should be held high any
present on the SI pin are latched on the rising edge of the time this function is not being used.) HOLD may be tied
SCK. Data on the SO pin is updated on the falling edge high directly to Vcc or tied to Vcc through a resistor.
of the SCK. Figure 9 illustrates hold timing sequence.

INSTRUCTION SET

Instruction Opcode Operation

WREN 0000 0110 Enable Write Operations
WRDI 0000 0100 Disable Write Operations
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 0011 Read Data from Memory
WRITE 0000 0010 Write Data to Memory

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Advanced Information CAT25C32/64

STATUS REGISTER array. These bits are non-volatile.

The Status Register indicates the status of the device. The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
The RDY (Ready) bit indicates whether the CAT25C32/ control the programmable hardware write protect fea-
64 is busy with a write operation. When set to 1 a write ture. Hardware write protection is enabled when WP is
cycle is in progress and when set to 0 the device low and WPEN bit is set to high. The user cannot write
indicates it is ready. This bit is read only. to the status register (including the block protect bits and
the WPEN bit) and the block protected sections in the
The WEL (Write Enable) bit indicates the status of the
memory array when the chip is hardware write pro-
write enable latch . When set to 1, the device is in a Write
tected. Only the sections of the memory array that are
Enable state and when set to 0 the device is in a Write
not block protected can be written. Hardware write
Disable state. The WEL bit can only be set by the WREN
protection is disabled when either WP pin is high or the
instruction and can be reset by the WRDI instruction.
WPEN bit is zero.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the

STATUS REGISTER

7 6 5 4 3 2 1 0
WPEN X X X BP1 BP0 WEL RDY

BLOCK PROTECTION BITS

Status Register Bits Array Address Protection

BP1 BP0 Protected
0 0 None No Protection
0 1 25C32: 0C00-0FFF Quarter Array Protection
25C64:1800-1FFF
1 0 25C32: 800-0FFF Half Array Protection
25C64:1000-1FFF
1 1 25C32: 0000-0FFF Full Array Protection
25C64:0000-1FFF

WRITE PROTECT ENABLE OPERATION

Protected Unprotected Status

WPEN WP WEL Blocks Blocks Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable

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CAT25C32/64 Advanced Information

DEVICE OPERATION After the correct read instruction and address are sent,
Write Enable and Disable the data stored in the memory at the selected address is
The CAT25C32/64 contains a write enable latch. This shifted out on the SO pin. The data stored in the memory
latch must be set before any write operation. The device at the next address can be read sequentially by continu-
powers up in a write disable state when Vcc is applied. ing to provide clock pulses. The internal address pointer
WREN instruction will enable writes (set the latch) to the is automatically incremented to the next higher address
device. WRDI instruction will disable writes (reset the after each byte of data is shifted out. When the highest
latch) to the device. Disabling writes will protect the address (1FFFh for 25C64 and FFFh for 25C32) is
device against inadvertent writes. reached, the address counter rolls over to 0000h allow-
ing the read cycle to be continued indefinitely. The read
READ Sequence operation is terminated by pulling the CS high. To read
The part is selected by pulling CS low. The 8-bit read the status register, RDSR instruction should be sent.
instruction is transmitted to the CAT25C32/64, followed The contents of the status register are shifted out on the
by the 16-bit address(the three Most Significant Bits are SO line. The status register may be read at any time
don’t care for 25C64 and four most significant bits are even during a write cycle. Read sequece is illustrated in
don't care for 25C32). Figure 4. Reading status register is illustrated in Figure 5.

Figure 2. WREN Instruction Timing

CS

SK

SI 0 0 0 0 0 1 1 0

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) — — — —

Figure 3. WRDI Instruction Timing

CS

SK

SI 0 0 0 0 0 1 0 0

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) — — — —

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Advanced Information CAT25C32/64

WRITE Sequence Byte Write

The CAT25C32/64 powers up in a Write Disable state. Once the device is in a Write Enable state, the user may
Prior to any write instructions, the WREN instruction proceed with a write sequence by setting the CS low,
must be sent to CAT25C32/64. The device goes into issuing a write instruction via the SI line, followed by the
Write enable state by pulling the CS low and then 16-bit address (the three Most Significant Bits are don’t
clocking the WREN instruction into CAT25C32/64. The care for 25C64 and four most significant bits are don't
CS must be brought high after the WREN instruction to care for 25C32), and then the data to be written. Pro-
enable writes to the device. If the write operation is gramming will start after the CS is brought high. Figure
initiated immediately after the WREN instruction without 6 illustrates byte write sequence.
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.

Figure 4. Read Instruction Timing

CS

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
SK

OPCODE

SI 0 0 0 0 0 0 1 1 BYTE ADDRESS*

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

*Please check the instruction set table for address

Note: Dashed Line= mode (1, 1) — — — —

Figure 5. RDSR Instruction Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK

OPCODE

SI 0 0 0 0 0 1 0 1

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

Note: Dashed Line= mode (1, 1) — — — —

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CAT25C32/64 Advanced Information

During an internal write cycle, all commands will be restriction is that the 64 bytes must reside on the same
ignored except the RDSR (Read Status Register) in- page. If the address counter reaches the end of the
struction. page and clock continues, the counter will “roll over” to
the first address of the page and overwrite any data that
The Status Register can be read to determine if the write may have been written. The CAT25C32/64 is automati-
cycle is still in progress. If Bit 0 of the Status Register is cally returned to the write disable state at the completion
set at 1, write cycle is in progress. If Bit 0 is set at 0, the of the write cycle. Figure 8 illustrates the page write
device is ready for the next instruction. sequence.
Page Write To write to the status register, the WRSR instruction
The CAT25C32/64 features page write capability. After should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
the first initial byte the host may continue to write up to register can be written using the WRSR instruction.
64 bytes of data to the CAT25C32/64. After each byte Figure 7 illustrates the sequence of writing to status
of data is received, six lower order address bits are register.
internally incremented by one; the high order bits of
address will remain constant. The only

Figure 6. Write Instruction Timing

CS

0 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 29 30 31
SK

OPCODE DATA IN

SI 0 0 0 0 0 0 1 0 ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) – – – –

Figure 7. WRSR Instruction Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

OPCODE DATA IN
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0
MSB

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) — — — —

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Advanced Information CAT25C32/64

DESIGN CONSIDERATIONS
The CAT25C32/64 powers up in a write disable state CAT25C32/64 goes into a write disable mode. CS must
and in a low power standby mode. A WREN instruction be set high after the proper number of clock cycles to
must be issued to perform any writes to the device after start an internal write cycle. Access to the array during
power up. Also,on power up CS should be brought low an internal write cycle is ignored and program-ming
to enter a ready state and receive an instruction. After is continued. On power up, SO is in a high impedance.
a successful byte/page write or status register write the

Figure 8. Page Write Instruction Timing

CS

0 1 2 3 4 5 6 7 8 21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1

SK

DATA IN
OPCODE
Data Data Data Data Byte N
SI 0 0 0 0 0 0 1 0 ADDRESS Byte 1 Byte 2 Byte 3 7..1 0

HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) – – – –

Figure 9. HOLD Timing

CS

tCD tCD

SCK

tHD
tHD
HOLD

tHZ
HIGH IMPEDANCE
SO
tLZ
Note: Dashed Line= mode (1, 1) — — — —

ORDERING INFORMATION
Prefix Device # Suffix

CAT 25C64 S I -1.8 TE13

Optional Product Temperature Range Tape & Reel

Company ID Number Blank = Commercial (0˚C to +70˚C) TE13: 2000/Reel
25C32: 32K I = Industrial (-40˚C to +85˚C)
25C64: 64K A = Automotive (-40˚ to +105˚C)*

Package Operating Voltage

P = 8-Pin PDIP Blank = 2.5 to 6.0V
S = 8-Pin SOIC 1.8 = 1.8 to 6.0V
U14= 14-Pin TSSOP
U20 = 20-Pin TSSOP

* -40˚C to +125˚C is available upon request

Notes:
(1) The device used in the above example is a 25C64SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)

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