IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 21, NO 12.

DECEMBER 1992 I709

A 100-MHz 100-dB Operational Amplifier

with Multipath Nested Miller
Compensation Structure
Ruud G. H. Eschauzier, Leo P. T. Kerklaan, and Johan H . Huijsing, Senior Member, ZEEE

Abstract-A 100-MHz bipolar operational amplifier has a gain r

of 100 dB. The op amp owes its high unity-gain bandwidth and
high gain to an all-n-p-n signal path and multipath nested Miller I
compensation (MNMC). The phase margin with a 100-pF load
is 40" at 100 MHz and the amplifier settles in 60 ns to 0.1% on
a 1-V step. For comparison, a similar op amp without the mul-
tipath technique has been realized. The unity-gain bandwidth
of this nested Miller compensation (NMC) op amp is 60 MHz
and the settling time is 70 ns. Theory and measurements con- -L
firm that the multipath technique almost doubles the band- Fig. 1. Principle of nested Miller compensation.
width of nested Miller compensated amplifiers.
Unfortunately, NMC causes a bandwidth reduction
I. INTRODUCTION compared to simple pole splitting. The bandwidth halves,
for example, when stepping from a two-stage simple
S PEED or bandwidth demands are generally in conflict
with demands on low-frequency accuracy or gain in
an operational amplifier (op amp). Op amps consisting of
Miller compensated amplifier to a three-stage amplifier
with nested Miller compensation.
The multipath nested Miller compensation (MNMC)
three gain stages to obtain an acceptable dc gain cannot structure proposed in this paper overcomes the bandwidth
be frequency compensated by conventional means. A reduction typical of conventional NMC by introducing an
widespread compensation method like simple pole split- independent path for high frequencies. The MNMC struc-
ting is only capable of handling the two dominant poles ture consists of NMC with a multipath input stage con-
that occur in two-stage amplifiers. nected in parallel with the regular input stage of the op
For this reason, high-frequency bypass techniques are amp. The multipath stage directly drives the output tran-
extensively used in high-frequency high-gain amplifiers sistor, bypassing the intermediate stage for high frequen-
[l]. In these amplifiers one gain stage is bypassed by a cies.
capacitor, short circuiting the stage for high frequencies. In the ideal case no pole-zero doublets occur, because
This compensation method greatly worsens the settling the multipath input stage can be independently configured
time of the operational amplifier because of the strong and from the remainder of the amplifier. In practice, the
inevitable pole-zero doublet the feedforward capacitor in- matching depends on the ratio of transconductances and
troduces [2]. the ratio of capacitors, both being among the best con-
A more effective way to compensate an amplifier con- trolled parameters in a standard IC process.
taining three gain stages or more is by nested Miller com- To take full benefit of the MNMC, the operational am-
pensation (NMC) [3]. This compensation technique nests plifier presented is based on an all-n-p-n topology, allow-
Miller feedback loops, as shown in Fig. 1. The structure ing an extremely high unity-gain bandwidth. Combined
starts off with an output device with a Miller capacitor with an effective class-AB control, the result represents
connected across it. For every gain stage added to the cir- the state of the art in high-bandwidth precision opera-
cuit, an additional Miller capacitor is introduced, closing tional amplifiers.
a wider feedback loop. For comparison, two operational amplifiers have been
Manuscript received April 27, 1992; revised July 10, 1992. This work realized. The first is compensated using NMC and dis-
was supported by the Technology Foundation (STW). plays a unity-gain bandwidth of 60 MHz with a 100-pF
R.G. H. Eschauzier and J . H. Huijsing are with the Department of Elec-
trical Engineering, Delft University of Technology, 2628 C D Delft, The
load. The second op amp has an additional multipath in-
Netherlands. put stage, which raises the bandwidth to 100 MHz under
L. P. T. Kerklaan was with the Department of Electrical Engineering, the same conditions.
Delft University of Technology, 2628 C D Delft, The Netherlands. He is
now with Philips Industrial Electronics, 5600 MO Eindhoven, The Neth-
The organization of the paper is as follows. The next
erlands. section addresses the principle of operation of the nested
IEEE Log Number 9203617. and the multipath nested Miller compensation structures.

0018-9200/92$03.00 0 1992 IEEE

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 1710 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 12, DECEMBER 1992

In Section I11 the two realized op amps are discussed, in-

cluding the all-n-p-n topology and class-AB control. Sec-
tion IV gives the experimental results. The paper finishes
with the conclusions and references.

11. PRINCIPLE OF OPERATION

A. Nested Miller Compensation CI

Fig. 2 shows the simplified schematic of a three-stage
P3 P2 PI
amplifier with NMC. Fig. 3 is the corresponding Bode
Fig. 2. Three-stage NMC.
plot. It shows the frequency characteristic of the output
stage, resulting from Cmland Cm2.
The output stage has two dominant poles p I and p2,
represented in Fig. 2 by the corresponding resistors and
capacitors. Inserting C,, splits the poles, such that p1
shifts to a higher frequency pi and p2to a lower frequency
p;. This is the effect of normal pole splitting, resulting in
a well-behaved combination of the intermediate and out-
put stage.
Miller capacitor Cm2,which closes the second loop, acts
on the newly placed pole pi and the additional pole p3,

+&
the latter being introduced by the input stage. Splitting
these two poles results in a straight 20-dB/decade rolloff Fig. 3 . Bode plot of the NMC structure.
from the dominating pole frequency pi up to the unity-
gain frequency wo. The Miller capacitors also help reduce
distortion by applying all internal gain across the output
stage.
The process of pole splitting is further clarified by Fig.
4(a) and (b). These figures show the root loci for C,, and
Cm2,respectively. Pole p i , positioned by the inner Miller p3 p2"

capacitor C m llimits
. the bandwidth of the op amp. To first
order pi depends on the ratio of the transconductance of
the output stage and the load capacitor C,:
Fig. 4 . Root locus of the NMC structure with effects of (a) C,,,, and
(b) C,.Z.

The design criteria for the NMC follow from requiring

a Butterworth frequency response from the amplifier with is closed. At approximately half its frequency polepi col-
unity-gain feedback: lides with p3. Fig. 4(b) illustrates this effect. Pole fre-
quency Ip;' I obeys

(3) B. Multipath Nested Miller Compensation

Fig. 5 demonstrates how adding an independent paral-
where gm2 is the transconductance of the intermediate lel input stage transforms the NMC structure into the
stage and gm3 is the transconductance of the first stage. MNMC structure. Transistors Q , through Q3 together with
Expression (2) gives a hint about the dimensioning of a the two capacitors Cmland Cm2build up the conventional
NMC amplifier. The unity-gain frequency of the inner NMC structure. The multipath input stage is transistor pair
loop, set by the transconductance of the intermediate stage Q4.This differential pair directly drives the output tran-
gm2and the inner Miller capacitor Cml,has to equal half sistor, overruling Q2 for high frequencies.
the limiting pole frequency pi . In Fig. 6 the Bode plot of the MNMC amplifier is
As (3) reveals, the unity-gain bandwidth of the NMC shown. Drawn as a dashed line is the high-gain low-fre-
op amp wo is one-fourth of the limiting pole frequency quency part established by the three-stage NMC ampli-
pi. This is half the value that could be obtained in a two- fier. The solid line represents the high-frequency part cre-
stage amplifier with simple Miller compensation. ated by the two transistors Q4and Q , and Miller capacitor
The bandwidth reduction is due to the downward shift C m l .Since this HF part is solely determined by a two-
of pole pi when the outer Miller loop with capacitor C,,,, stage amplifier with simple Miller compensation, no

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 ESCHAUZIER er a1 OP AMP WITH MULTIPATH NESTED MILLER COMPENSATION STRUCTURE 1711

The position of the doublet is

Or, with (6)

P3 P2 P1
since for a phase margin of 60" the unity-gain frequency
woof the op amp should be half p i (=pi' ).
Fig. 5 . Multipath NMC.
The root locus in Fig. 7 shows the movement of the
poles in the MNMC structure. In contrast to NMC, clos-
ing the outer Miller loop only moves the poles a fraction,
because of the low value g m 2 / C m IPole
. p j is eliminated
by the multipath zero.

111. CIRCUITDESCRIPTION
A. All-n-p-n Topology
Fig. 8 is a simplified schematic of the op amp with
NMC. To assure a high bandwidth, only n-p-n transistors
Fig. 6. Bode plot of the MNMC structure are present in the signal path. As a consequence, in the
push-pull output stage an emitter follower has to be used
for the push and an inverting amplifier for the pull tran-
bandwidth reduction takes place. Matching of the high- sistor. The emitter following Qdo0has a capacitor Cpl con-
and low-frequency parts is easy, as the following analysis nected from its base to ground and the inverting amplifier
confirms. Qsooa Miller capacitor from base to collector. Capacitors
It is important to note that the multipath input stage Cmland Cpl have equal values.
adds a zero to the transfer function. The positions of the Surprisingly, when driven by a current signal both tran-
poles do not change compared to NMC. This makes clear sistor configurations behave symmetrically [4]. Not only
that the dimensioning of the MNMC circuit should be dif- do they have the same transimpedance z,, but also their
ferent from the NMC circuit, otherwise the second pole output impedances zoutare equal.
p;' will stay at its place and no bandwidth improvement is
to be expected. The position of pole p;' with respect to its
original position pi before closing the second Miller loop
is given by

P ,,I -- P- i+ - Pi I - - . 4gm2
2 2 Pi Cm, Because of the differential second stage in Fig. 8, the
circuit has a capacitor Cp2added to it to balance out Miller
From ( 5 ) it follows that the greater ratio gm2/Cm1(the
capacitor C,, .
unity-gain frequency of the inner Miller loop) compared
The level-shift circuit, depicted as a voltage source in
to the limiting pole frequency p i , the lower the bandwidth
Fig. 8, has the characteristics of an all-pass current net-
of the circuit. Setting gm2to zero leads to p;' = p i . Ob-
work [4]. In Fig. 9 the circuit is shown. For input currents
viously, in this case there is no bandwidth reduction, since
there are two separate routes from input to output. For
only two stages are active. A better choice is
low frequencies the signal goes through the resistor and
the p-n-p transistor. For high frequencies the path is
through the capacitor and the n-p-n current follower. The
crossover frequency fnp is set by the RC product. As long
With this ratio, the bandwidth reduction is only about 10% as& is lower than thef, of the p-n-p transistor, no pole-
and still three stages contribute to the low-frequency gain. zero doublets occur, because no current is lost in the all-
Putting the multipath zero on top of pole p j requires pass network. The bandwidth of the level-shift circuit
equals the n-p-n'sf,. The location of the level shift in the
(7) circuit is dictated by noise considerations. Situating the
level shift directly following the input stage would have
The condition in (7) is satisfied by (6). As (7) reveals, the increased the noise, because this would mean abandoning
matching of the pole and the zero only depends on the the passive collector loads.
matching of transconductances and capacitors. The MNMC op amp is largely similar to the NMC op

~-~ -~ - ~ - - ~

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 1712 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 12, DECEMBER 1992

I I

multipath zero
I o p2'
3-
pl' p l " p3' p3 p2"

I I I
Fig. 7 . Root locus of the MNMC structure. input stage ' intermediate' level- ' output stage
stage shift

Fig. 10. Simplified schematic of the MNMC op amp

I I I
input stage ' intermediate' level- output stage
stage shift
Fig. 11. Class-AB control
Fig. 8. Simplified schematic of the NMC op amp.

-lout

Fig. 12. Class-AB characteristic.

class-AB control doubles the driving of the other transis-

tor).
Fig. 9. All-pass level-shift circuit. The class-AB circuit incorporates a combined error am-
plifier and decision gate. The decision gate, comprising
e611 and & I , selects the smaller of the two transistor
amp in Fig. 8. Added is the multipath input stage, as Fig. currents in the output stage. Controlling this current keeps
10 points out. the output transistors from shutting off. The transistors
e611 and function as two emitter followers, but only
B. Class-AB Control the device corresponding to the lowest output current be-
The feedback class-AB circuit controls the quiescent comes properly biased. This active emitter follower trans-
current of the output stage and prevents cutoff of the out- fers its input voltage to the common-emitter node of the
put devices by assuring a minimum quiescent current [5]. error amplifier.
The control circuitry is independent from the signal The error amplifier consists of the decision gate to-
path, as demonstrated in Fig. 11. The signal is applied to gether with e 601 and Qm2. The input voltages of the de-
the output transistors as two differential currents, while cision gate are derived from the push and pull transistor
the class-AB circuit controls the biasing by two common currents by diodes Q750and Q7m. The reference of the
currents. Class-AB operation does not interfere with the error amplifier is current If&across diode Q710. Fig. 12
output signal, because the common currents cancel in the shows the class-AB characteristic. The quiescent current
output stage (i.e., when one of the transistors is controlled is set by Zfef and the emitter ratios of the transistors. The
at its quiescent current due to a high output current, the minimum value is limited to half the quiescent current.

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 1713

Fig. 13. Total schematic of the NMC op amp

VCr

ZJQO
V n
Fig. 14. Total schematic of the MNMC amplifier.

C. Total Schematic consequence to the PTAT output current and start-up is

Fig. 13 shows the total schematic of the NMC opera- guaranteed. The PTAT current is 100 pA at room tem-
tional amplifier. This circuit diagram includes the biasing perature. The quiescent current of the output transistors
and level-shift elements. The actual circuit uses Darling- is set to 4.5 mA.
ton transistors in the output stage to improve the gain. The The MNMC op amp (Fig. 14) is, apart from the addi-
bias current is generated in the PTAT current source con- tional input stage with Qlosand e,,,,
largely comparable
sisting of Q80()-&0 [ 6 ] . Resistor R,,, initiates a small to the operational amplifier without the multipath tech-
current in the right-hand branch. Because of the cross- nique. To limit the bandwidth reduction, indicated by ( 5 ) ,
couplea structure, the magnitude of the current is of no the transconductance of the intermediate stage is reduced

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 s
1714 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 21. NO. 12, DECEMBER 1992

Lbond

Lbond

I C'ood
Fig. 15. Separate voltage and current terminals at the output

(a) (b)
Fig. 16. Photomicrographs of the (a) NMC op amp and (b) MNMC op amp.

by lowering the tail current of Q200and and inserting of the MNMC op amp is 100 MHz, with a phase margin
degeneration resistors R,, and R210. The doublet fre- of slightly less than 40". Both op amps are loaded by a
quency, according to (8), is 15 MHz. 100-pF capacitor in parallel with a 1-kQ resistor, as is the
The lower tail current of the intermediate stage ensures case in the following measurements.
that, despite the extra input stage of the MNMC op amp, Fig. 18 gives the slew response of the op amps to an
the total supply currents of the two amplifiers are equal. input step of 1 V. Since the input stages are not degen-
erated by emitter resistors, the slew rate is determined by
IV. REALIZATIONS
AND EXPERIMENTAL
RESULTS the unity-gain bandwidth of the amplifiers. The slew rate
of the NMC op amp (Fig. 18(a)) is 20 V/ps, and that of
The chips were fabricated in a 3-GHz 5 n-p-n bipolar the MNMC op amp (Fig. 18(b)) is 35 V/ps.
IC process. To be able to drive a 100-pF load with a Fig. 19 gives an impression of the small-signal settling
unity-gain bandwidth of 100 MHz, load and feedback are of the amplifiers. The input step is 100 mV. The 0.1%
separated by two output pins and corresponding bond settling time corresponding to the NMC (Fig. 19(a)) is 40
wires (Fig. 15). The pins act as current and voltage ter- ns. The step response very much resembles the designed
minals and isolate the driving of the load from the feed- for Butterworth curve. As Fig. 19(b) indicates a slow set-
back path. Without this measure the load capacitance and tling component is detectable in the step response of the
inductance of the bonding wires would introduce a pair of MNMC amplifier. The doublet spacing corresponding to
complex poles in the feedback loop, resulting in instabil- the slow settling component is approximately 5 % . The
ity of the circuit. 0.1 % settling time is 50 ns.
Clearly the two output bonding wires can be seen in The contribution of the slow settling component to the
Fig. 16. Fig. 16(a) is a photomicrograph of the NMC and total settling time becomes relatively less important for
Fig. 16(b) of the MNMC op amp. The die area of both large input steps. Because most of the large-signal step
amplifiers is equal. The extra area needed on the MNMC response is governed by slewing of the op amp, the
chip for the multipath input stage is used in the NMC MNMC settles faster to 0.1 % after a 1-V input step than
amplifier to accommodate the Miller capacitors. These its NMC counterpart. This is confirmed by the plots in
capacitors are larger due to the lower bandwidth of the op Fig. 20. Settling times are 70 and 60 ns, respectively.
amp. The die area of the chips is 1.2 mm x 1.5 mm. The last plot concerning the two op amps is shown in
In Fig. 17 the Bode plots of the op amps are shown. Fig. 21(a) and (b), which represents the input-referred
The NMC op amp has a unity-gain bandwidth of 60 MHz voltage noise of the NMC and MNMC op amps, respec-
with a phase margin of 40°C. The unity-gain bandwidth tively. The voltage noise of the op amps is 2 nV/&.

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 ESCHAUZIER et al.: OP AMP WITH MULTIPATH NESTED MILLER COMPENSATION STRUCTURE 1715

0 MKR 59 274 131.098 I I Z A: REF 0: R

T/H 403.095m dU 70.00 18

DIV DIV START 100 000.000 Hz OIV DIV START 100 0 0 0 . 0 0 0 H Z

10.00 36.00 STOP 200 000 0 0 0 . 0 0 0 HZ 10.00 36.00 STOP 200 000 0 0 0 . 0 0 0 H Z
(a) (b)
Fig. 17. Bode plots of the (a) NMC op amp and (b) MNMC op amp.

-20 GOO ne

Fig. 18. Slew response of the (a) NMC op amp and (b) MNMC op amp (500 mV/div)

77 so0 ns

(a) (b)
Fig. 19. Small-signal settling of the (a) NMC op amp and (b) MNMC op amp ( 5 mV/div)

For frequencies above 15 MHz (the crossover frequency circuits contributes to the input noise through the multi-
of the multipath input stage) the noise of the MNMC op path input stage. The total input noise is limited to
amps goes up slightly. Because the intermediate stage is 4 nV/& over the bandwidth of the MNMC op amp.
not active in this frequency region, noise of the level-shift Table I summarizes the measurement results.

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 1716 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 12, DECEMBER 1992

10.0 nsfdiv

(a) (b)
Fig. 20. Large-signal settling of the (a) NMC op amp and (b) MNMC op amp (50 mV/div)

V. CONCLUSIONS

Nested Miller compensation and multipath nested

Miller compensation open the door for a next generation
of fast and accurate operational amplifiers. The MNMC
amplifier presented drives a 100-pF load with a unity-gain
bandwidth of 100 MHz. The multipath technique intro-
c

$ I
.-
04
duces a well-controlled pole-zero doublet, the matching
of which depends on capacitor and current ratios only. In
lk 10k lOOk 1M 10M 100M
frequency [Hz] + a test chip the doublet spacing was 5 % . The unity-gain
(a) bandwidth of the NMC op amp is 60 MHz. Since feed-
forward components are absent in this amplifier, no pole-
zero doublets occur. The gain of both op amps is 100 dB.

ACKNOWLEDGMENT

The authors would like to thank the following people

% I : : : ; :
0
lk 10k lOOk 1M 10M lOOM
of Philips Nijmegen for their valuable contributions in the
fabrication of the test chips: E. van Tuyl for making avail-
able the facilities, M. Rolsma for his help during the lay-
frequency [Hz] 4 out and simulation, and T. Clerkx for his support in fin-
(b) ishing the chips.
Fig. 21. Input-referred voltage noise of (a) the NMC op amp, and (b) the
MNMC op amp.
REFERENCES
TABLE I
MEASUREMENT
RESULTS [ I ] NE 5534 Data Sheet, Signetics, 1978; TDA 1034 Data Sheet, Philips,
Apr. 1976.
Parameter NMC MNMC [2] B . Y. Kamath, R. G. Meyer, and P. R. Gray, “Relationship between
frequency response and settling time of operational amplifiers,” IEEE
Unity-Gain Frequency 60 MHz 100 MHz J. Solid-Srare Circuits, vol. SC-9, pp. 341-352, Dec. 1974.
DC Gain 100 dB 100 dB [3] J. H. Huijsing, “Multi-stage amplifier with capacitive nesting for fre-
Settling Time (0.1 %) (V, = 0.1 V) 40 ns 50 ns quency compensation,” U.S. Patent Appl. Ser. 602234, filed Apr. 19,
Settling Time (0.1 %) ( V , = I V) 70 ns 60 ns 1984.
Input Noise Voltage (1 kHz) 2 nv/& 2 nv/& [4] J. H. Huijsing and F. Tol, “Monolithic operational amplifier design
(50 MHz, 100 MHz) 2 nV/& 4 nv/& with improved HF behavior,” IEEE J. Solid-Srare Circuits, vol. SC-1 I ,
Output Impedance (50 MHz) 10 n 10 n pp. 323-328, Apr. 1976.
Maximum Output Current +50 mA k 5 0 mA [5] E. Seevinck, W. De Jager, and P. Buitendijk, “A low-distortion out-
Supply Current 9.5 mA 9.5 mA put stage with improved stability for monolithic power amplifiers,”
IEEE J. Solid-State Circuits, vol. 23, pp. 794-801, June 1988.
(TA = 25”C, Vcc = 8 V, C,= 100 pF, and R, = 1 k n except where indi- [6] G. C. M. Meijer, “Integrated circuits and components for bandgap
cated.) references and temperature transducers,” Internal Report, Delft Univ.
Technology, Delft, The Netherlands, 1982.

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 ESCHAUZIER et al.: OP AMP WITH MULTIPATH NESTED MILLER COMPENSATION STRUCTURE 1717

Ruud G. H. Eschauzier was bom in Vlaardin- Johan H. Huijsing (SM’81) was bom in Ban-
gen. The Netherlands, on August 10, 1967. He dung, Indonesia, on May 21, 1938. He received
received the M.S. degree in electrical engineering the M.Sc. degree in electrical engineering from
in 1990, from the Delft University of Technology. the Delft University of Technology, Delft, The
He is now a Ph.D. student at the Electronic In- Netherlands, in 1969, and the Ph.D. degree from
strumentation Laboratory of the Delft University. this university in 1981 for work on operational
His research subjects include analog integrated amplifiers (thesis: “Integrated Circuits for Accu-
circuits with extremely high bandwidth-to-power rate Linear Analogue Electric Signal Process-
ratios. ing,” supervised by Prof. Dr. Ir. J. Davidse).
Since 1969 he has been a member of the Re-
Leo P. T. Kerklaan was born in Amsterdam, The search and Teaching Staff of the Electronic Instru-
Netherlands, on January 22, 1955. He received mentation Laboratory, Department of Electrical Engineering, Delft Uni-
the M.S. degree in electrical engineering from the versity of Technology, where he is now Professor of Electronic
University of Delft, The Netherlands, in 1988 on Instrumentation. He teaches courses on electrical measurement techniques,
the subject of the design of a nested feedback electronic instrumentation, operational amplifiers, and analog-to-digital
structure op amp. converters. His field of research is analog circuit design (operational am-
He is now with Philips Industrial Electronics, plifiers, analog multipliers, etc.) and integrated smart sensors (signal con-
Eindhoven, The Netherlands, where he is cur- ditioning on the sensor chip, frequency and digital converters which in-
rently engaged in the design of high-frequency corporate sensors, bus interfaces, etc). He is the author or coauthor of some
video electronics. 70 scientific papers and 12 patents.

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