LECTURE-29

UNIT-V(Memory System)
The Memory System
• the execution speed of programs is highly dependent on the speed
with which instructions and data can be transferred between the
processor and the memory.
• Ideally, the memory would be fast, large, and inexpensive.
Unfortunately, it is impossible to meet all three of these requirements
simultaneously.
• The memory of a computer comprises a hierarchy, including a cache,
the main memory, and secondary storage.
• Here we describe the most common components and organizations
used to implement these units, so as to improve the effective speed
and size of the memory
Basic Concepts
Memory
Measurement
Units
Address Space
• The number of locations represents the size of the address space of the
computer.
• Example: Machines whose instructions generate 32-bit addresses can
utilize a memory that contains up to 232 = 4G (giga) locations
• The memory is usually designed to store and retrieve data in word-length
quantities
• Example:
• Consider a byte-addressable computer whose instructions generate 32-bit addresses.
• the high order 30 bits determine which word will be accessed.
• If a byte quantity is specified, the low-order 2 bits of the address specify which byte
location is involved.
Memory and Processor Connections

When the processor-

memory interface
receives the memory’s
response, it asserts the
MFC signal

Fig. Connections of the Memory to the Processor

Few Definitions
• Memory Access Time: the time that elapses between the initiation of
an operation to transfer a word of data and the completion of that
operation.
• Memory Cycle Time:
• is the minimum time delay required between the initiation of two successive
memory operations,
• for example, the time between two successive Read operations.
• The cycle time is usually slightly longer than the access time
• RAM: A memory unit is called a random-access memory (RAM) if the
access time to any location is the same, independent of the location’s
address.
Cache and Virtual Memory
• Cache Memory:
• One way to reduce the memory access time is to use a cache memory. This is a small,
fast memory inserted between the larger, slower main memory and the processor.
• It holds the currently active portions of a program and their data.
• Virtual memory:
• is another important concept related to memory organization.
• With this technique, only the active portions of a program are stored in the main
memory, and the remainder is stored on the much larger secondary storage device.
• Sections of the program are transferred back and forth between the main memory
and the secondary storage device, as and when required.
• As a result, the application program sees a memory that is much larger than the
computer’s physical main memory.
Lecture 30
(UNIT-V)
Block Transfers
• data move frequently between the main memory and the cache and
between the main memory and the disk.
• Data are always transferred in contiguous blocks involving tens,
hundreds, or thousands of words.
• Data transfers between the main memory and high-speed devices
such as a graphic display or an Ethernet interface also involve large
blocks of data.
• Hence, a critical parameter for the performance of the main memory
is its ability to read or write blocks of data at high speed.
Semiconductor RAM Memories
• The technology for implementing computer memories uses semiconductor
integrated circuits.
• Semiconductor random-access memories (RAMs) are available in a wide
range of speeds.
• Their cycle times range from 100 ns to less than 10 ns.
• Your computer probably uses two types of RAM at the same time :
• Static RAM (SRAM) and
• Dynamic RAM (DRAM)
• Static RAM is fast and expensive, and dynamic RAM is less expensive and
slower.
• Therefore, static RAM is used to create the CPU's speed-sensitive cache,
while dynamic RAM forms the larger system RAM space.
 Internal Organization of Memory Chips

• The data input and the data output

of each Sense/Write circuit are
connected to a single bidirectional
data line that can be connected to
the data lines of a computer.
• Two control lines, 𝑅/𝑊 # and CS, are
provided.
• the CS (Chip Select) input selects a
given chip in a multi-chip memory
system.
• Each cell will be in state 0 or state 1
• Requires 14 external connections for
address, data, and control lines.
• It also needs two lines for power
supply and ground connections.
Fig. 16x8 Organization of bit cells in a Static memory chip.
 Static RAM Cell
• Memories that consist of circuits
capable of retaining their state as
long as power is applied are known
as static memories.
• Two inverters are cross-connected to
form a latch.
• The latch is connected to two bit
lines by transistors T1 and T2.
• These transistors act as switches that
can be opened or closed under
control of the word line.
• When the word line is at ground
level, the transistors are turned off
and the latch retains its state.
• In order to read from / write into the
SRAM cell, the word line is activated
to close switches T1 and T2.
Dynamic RAM Cell
• Information is stored in a dynamic memory cell in the form of
a charge on a capacitor.
• An example of a dynamic memory cell that consists of a
capacitor, C, and a transistor, T, is shown in Figure 8.6.
• To store information in this cell, transistor T is turned on and
an appropriate voltage is applied to the bit line.
• This causes a known amount of charge to be stored in the
capacitor.
• After the transistor is turned off, the capacitor begins to
discharge; its contents must be periodically refreshed by
restoring the capacitor charge to its full value.
• This occurs when the contents of the cell are read or when
new information is written into it.
 Static RAM Vs Dynamic RAM

Feature Static RAM Dynamic RAM

Speed Faster Slower
Bit Packing Density Less(as many transistors are High(as only a capacitor and a
required per cell) transistor is required for each
cell)
Cost per bit High Low
Retaining time Retains the cell state for a Retains the cell state for a short
longer time time (as the capacitor loose
charge over time)
Power Consumption Low(requires a small steady High(as it requires bursts of
current ) power every few milliseconds to
refresh. )
Use Used in cache memories Used in Main memory
Internal Organization of Memory Chips

Q. 1 How many external Connections are

required here ? (Ans. 15)

Q.2 How many external connections are

required for 1K (1024) memory Cells
realised as 128 x 8 memory ? (Ans. 19)
Internal Organization of Dynamic RAM Chips
• Without multiplexing this circuit
requires(25+8+2+2) =37 pins
• When higher order row bits(14) and lower order
column bits(11) are multiplexed onto 14 address
pins
• Thus only(14+8+2+2+2)=28 pins are required.
• During a Read or a Write operation, the row
address is applied first.
• It is loaded into the row address latch in
response to a signal Row Address Strobe (𝑅𝐴𝑆 ).
• This causes a Read operation to be initiated, in
which all cells in the selected row are read and
refreshed.
• Shortly after the row address is loaded, the
column address is applied to the address pins…
• 𝑅𝐴𝑆 𝑎𝑛𝑑 𝐶𝐴𝑆 signals are generated by a
memory controller circuit external to the chip,
when the processor issues a Read or a Write
command.
Asynchronous Vs Synchronous RAM
• In the past, DRAM has been asynchronous, meaning that memory
access is not coordinated with the system clock.
• This works fine for lower speeds but the need for high speed
applications has led to the development of synchronous DRAM
(SDRAM).
• In SDRAM, all signals are tied to the clock, so timing is much tighter
and better controlled.
Lecture-31
(UNIT-V)
DDR1,DDR2, DDR3, and DDR4
• DDR stands for Double Data Rate
• They are the next generation of SDRAM, which
achieves greater bandwidth than the preceding
single data rate SDRAM by transferring data on
the rising and falling edges of the clock signal
(double pumped).
• These are all SDRAMS, governed by the clock
which enables the memory controller to know
the exact clock cycle when the requested data
will be ready
• so the CPU no longer has to wait between
memory accesses.
• Speeds in (1 MT/s is 106 or one million
transfers per second)
SIMM and DIMM
• SIMM : Single in Line Memory Module (chips on single side of the MM)
• DIMM: Dual in Line Memory Module (chips on both sides of the MM)
• DDR RAMS comes as DIMM
Multi-chip Memory Organization to form a Memory
System(Static RAM Example)

Figure Organization of a 2M x32 memory module

using 512K x 8 static memory chips.
Example:
Give the organization of 4GB memory using 1GB memory chips.
Home Work
• Design a memory system of capacity 2048x16 using 128x8 RAM chips.
Show address lines, data lines, and control signals
Computer Memories
 Read-only Memories(ROMs)

• There are many applications requiring small permanent memory

• ROM BIOS in computers
• Embedded Computers uses ROM to store instructions for controlling
embedded devices like(washing machines, water heaters, etc.)

• Since its normal operation involves only reading the stored data, a
memory of this type is called a read-only memory (ROM).
ROM Cell
• A logic value 0 is stored in the cell if the
transistor is connected to ground at point P;
otherwise, a 1 is stored.
• The state of the connection to ground in each
cell is determined when the chip is
manufactured
• The bit line is connected through a resistor to
the power supply.
• To read the state of the cell, the word line is
activated to close the transistor switch.
• If there is no connection to ground, the bit line
remains at the high voltage level, indicating a 1.
• A sense circuit at the end of the bit line
generates the proper output value. ,
Types of
ROM
PROM(Programmable ROM)
• Some ROM designs allow the data to be loaded by the user, thus providing a
programmable ROM (PROM).
• Programmability is achieved by inserting a fuse at point P in Figure.
• Before it is programmed, the memory contains all 0s.
• The user can insert 1s at the required locations by burning out the fuses at these
locations using high-current pulses.
• Of course, this process is irreversible.
• PROMs provide flexibility and convenience not available with ROMs
• It provides a more convenient and considerably less expensive approach, because
memory chips can be programmed directly by the user.
EPROM (Erasable PROM)
• It allows the stored data to be erased and
new data to be written into it.
• It provides considerable flexibility during
the development phase of digital systems.
• Erasure is done by exposing the chip to
ultraviolet light, which erases the entire
contents of the chip.
• To make this possible, EPROM chips are
mounted in packages that have
transparent windows.
EPROM Working
• An EPROM cell has a structure similar to the ROM cell
• However, the connection to ground at point P is made through a
special transistor.
• The transistor is normally turned off, creating an open switch. It can
be turned on by injecting charge into it that becomes trapped inside.
• Erasure requires dissipating the charge trapped in the transistors that
form the memory cells.
• This can be done by exposing the chip to ultraviolet light, which
erases the entire contents of the chip.
EEPROM (Electrically Erasable PROM)
• An EPROM must be physically removed from the circuit for reprogramming.
• Also, the stored information cannot be erased selectively. The entire
contents of the chip are erased when exposed to ultraviolet light.
• EEPROM can be programmed, erased, and reprogrammed electrically.
• It does not have to be removed for erasure.
• Moreover, it is possible to erase the cell contents selectively.
• One disadvantage of EEPROMs is that different voltages are needed for
erasing, writing, and reading the stored data, which increases circuit
complexity.
• Due to its many advantages, they have replaced EPROMs in practice.
EPROM Vs EEPROM
Flash Memory
• Similar to EEPROM technology
• The key difference is that, in a flash device, it is only possible to write an entire
block of cells.
• Prior to writing, the previous contents of the block are erased.
• Flash devices have greater density, which leads to higher capacity and a lower
cost per bit.
• They require a single power supply voltage, and consume less power in their
operation.
• The low power consumption of flash memories makes them attractive for use in
• portable, battery-powered equipment.
• Typical applications include hand-held computers, cell phones, digital cameras,
and MP3 music players
Flash Memories Vs SDD(Static Storage Device)
• Similarities:
• both are faster than HDDs and do not have
moving parts like HDDs.
• Both are also forms of non-volatile memory, so
they retain any information saved to them even
after you shut down your computer
• and flash and SSD storage are easily
rewriteable.
• Differences:
• the flash memory in flash drives is often much
slower than the flash used in SSDs.
• while most SSDs do use flash memory, not all
SSDs do. (SSD indicates no moving parts)
HDD Vs SDD
(HDD has
moving parts,
but SSD
doesn’t have
them)
Memory Hierarchy
Cache Memories
• The cache is a small and very fast memory, interposed
between the processor and the main memory.
• Its purpose is to make the main memory appear to the
processor to be much faster than it actually is.
• The effectiveness of this approach is based on a property of
computer programs called locality of reference.
• many instructions in localized areas of the program are
executed repeatedly during some time period
• This behaviour manifests itself in two ways: temporal and
spatial.
Temporal and Spatial Locality
• Temporal locality:
• suggests that whenever an information item, instruction or data, is first
needed, this item should be brought into the cache, because it is likely to be
needed again soon.
• Spatial locality:
• suggests that instead of fetching just one item from the main memory to the
cache, it is useful to fetch several items that are located at adjacent addresses
as well.
• The term cache block(cache line) refers to a set of contiguous address
locations of some size.
Working of
Cache Memory
• When the processor issues a
Read request, the contents of
a block of memory words
containing the location
specified are transferred into
the cache.
• Subsequently, when the
program references any of
the locations in this block, the
desired contents are read
directly from the cache.
Replacement Algorithm
• The correspondence between the main memory blocks and those in
the cache is specified by a mapping function.
• When the cache is full and a memory word (instruction or data) that
is not in the cache is referenced, the cache control hardware must
decide which block should be removed to create space for the new
block that contains the referenced word.
• The collection of rules for making this decision constitutes the cache’s
replacement algorithm.
Cache Hit
• The cache control circuitry determines whether the word requested by the processor
currently exists in the cache.
• If it does, the Read or Write operation is performed on the appropriate cache location.
• In this case, cache hit is said to have occurred.
• The main memory is not involved when there is a cache hit in a Read operation.
• For a Write operation, the system can proceed in one of two ways:
• write-through protocol: both the cache location and the main memory location are
updated.
• write-back, or copy-back protocol:
• update only the cache location and to mark the block containing it with an associated flag bit,
often called the dirty or modified bit.
• The main memory location of the word is updated later, when the block containing this
marked word is removed from the cache to make room for a new block(cache replacement).
• Both the protocols result in unnecessary write operations in the main memory
• The write-back protocol is used most often, to take advantage of the high speed with
which data blocks can be transferred to memory chips.
Cache Miss
• Read Miss - A Read operation for a word that is not in the cache:
• It causes the block of words containing the requested word to be copied from
the main memory into the cache.
• After this, the particular word requested is forwarded to the processor.
• Alternatively, this word may be sent to the processor as soon as it is read from
the main memory(called load-through, or early restart)
• Write miss - A Write operation for a word that is not in the cache
• occurs in a computer that uses the write-through protocol, the information is
written directly into the main memory
• For the write-back protocol, the block containing the addressed word is first
brought into the cache, and then the desired word in the cache is overwritten
with the new information.
Separate Instruction and Data Caches
• When memory operand fetch for the current instruction and the
subsequent instruction fetch, is being done at the same time,
instruction fetch is delayed until the data access operation is
completed.
• the instruction pipeline is stalled during this operation
• To avoid stalling the pipeline, many processors use separate caches
for instructions and data, making it possible for the two operations to
proceed in parallel
Lecture-32
(UNIT-V)
Cache Mapping Techniques
• There are several methods for determining where memory blocks are
placed in the cache.
• Example: Assume that the memory system has
• A cache consisting of 128 blocks of 16 words each, total (2048 (2K)) words.
• The main memory consisting of 4K blocks of 16 words each, total 64K words
• consecutive addresses refer to consecutive words.
• Techniques:
• Direct Mapping
• Associative Mapping
• Set - Associative Mapping
 Direct Mapping
• In this technique, block j of the main
memory maps onto block j modulo
128 (j%128) of the cache
• Mappings: MB -> CB
• 0->0, 128->0, 256->0, … 3968->0
• 1->1, 129->1, 257->1, … 3969->1
• When accessing a memory word, the
corresponding TAG fields are
𝑇𝑎𝑔 𝑏𝑖𝑡𝑠 =
𝑛𝑜. 𝑜𝑓 𝑏𝑙𝑜𝑐𝑘𝑠 𝑖𝑛 𝑚𝑎𝑖𝑛 𝑚𝑒𝑚𝑜𝑟𝑦 compared
𝑛𝑜. 𝑜𝑓 𝑏𝑙𝑜𝑐𝑘𝑠 𝑖𝑛 𝑐𝑎𝑐ℎ𝑒 𝑚𝑒𝑚𝑜𝑟𝑦 • Match -> hit and Mismatch ->
miss
• Contention is resolved using
overwriting the new block on the old
one (e. g. M1 and M257, no choice:
direct replacement)
• May lead to poor performance if both
blocks are required frequently
 Associative Mapping
• It is the most flexible mapping method, in which a
main memory block can be placed into any cache
block position
• In the example, 12 tag bits are required to identify
a memory block when it is resident in the cache
• The tag bits of an address received from the
processor are compared to the tag bits of each
block of the cache to see if the desired block is
present.
• When a new block is brought into the cache, it
replaces (ejects) an existing block only if the cache
is full.
• In this case, we need a replacement algorithm to
select the block to be replaced.
• The complexity of an associative cache is higher
than that of a direct-mapped cache, because of the
need to search all 128 tag patterns.
• To avoid a long delay, the tags must be searched in
parallel. A search of this kind is called an
associative search
Set - Associative Mapping
• It is a combination of the direct- and associative-
mapping techniques.
• Figure shows Set-associative-mapped cache with
two blocks per set.
• The blocks of the cache are grouped into sets, and
the mapping allows a block of the main memory
to reside in any block of a specific set.
• Hence, the contention problem of the direct
method is eased by having a few choices for block
placement
• At the same time, the hardware cost is reduced by
decreasing the size of the associative search(lesser
tag bits and lesser comparisons of tag fields).
• two-way associative search is required in the
example.
• The number of blocks per set is a parameter that
can be selected to suit the requirements of a
particular computer.
Stale Data in cache and Valid Bit

• A control bit, usually called the valid bit, must be provided for each
cache block to indicate whether the data in that block are valid(1) or
invalid(0).
• When power is first turned on, the cache contains no valid data and bits
of all the cache blocks are set to 0.
• If the memory blocks being updated (using DMA) are currently in the
cache, the valid bits of the corresponding cache blocks are set to 0.
• As program execution proceeds, the valid bit of a given cache block is
set to 1 when a memory block is loaded into that location.
• The processor fetches data from a cache block only if its valid bit is
equal to 1.
• The use of the valid bit in this manner ensures that the processor will
not fetch stale data from the cache.
Cache Coherence
• Consider a system that uses the write-back protocol for cache.
• Under this protocol, new data written into the cache are not written to the memory at the same
time.
• Hence, data in the memory do not always reflect the changes that may have been made in the
cached copy.
• It is important to ensure that such stale data in the memory are not transferred to the disk.
• One solution is to flush the cache, by forcing all dirty blocks to be written back to the memory
before performing the transfer to the disk.
• The operating system can do this by issuing a command to the cache before initiating the DMA
operation that transfers the data to the disk.
• Flushing the cache does not affect performance greatly, because such disk transfers do not occur
often
• The need to ensure that two different entities (the processor and the DMA subsystems in this
case) use identical copies of the data is referred to as a cache-coherence problem.