04 CPUOverview
04 CPUOverview
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Overview
CPU overview
Cortex-M0+ Processor Core
Cortex-M0+ Processor Core Registers
Memory System and Addressing
Thumb Instruction Set
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CPU OVERVIEW
Central Processing Unit (CPU)
CPU is the fundamental execution/processing unit
of the computer
CPU consists of ALU, Control Unit, and Registers
CPU is characterized by:
Clock frequency
Speed
Data bus width
Instruction set
Addressing capability
Addressing capacity
Internal Structure of CPU
Intel 4004
in 1971, commercially available single-chip microprocessor
Example:
Motorola 6802
Registers in the Fetch Unit
Program Counter: holds the memory location
of the next instruction.
Instruction Register: holds the current
instruction being executed
Instruction Decoder
It decodes the instructions and generates the
control signals
Arithmetic Logic Unit (ALU)
ALU performs all arithmetic and logic
operations in a microprocessor
ALU has two inputs (A, B) for the operands
and one input for a control signal that
selects the operation
Operation and Shift control bits determine,
which type of operation to perform (F)
Output is the result of operation (R) and
status information (D)
Status information is used to indicate cases
Zero: if all result lines have value 0
Overflow: integer overflow of add and
subtract functions
For unsigned integers, it does not provide any
useful information
Registers
A register is a storage location in the CPU
It is used to hold data or a memory address during
the execution of an instruction
Because the register file is small and close to the
ALU, accessing data in registers is much faster than
accessing data in memory outside the CPU
The register file makes program execution more
efficient
The number of registers varies from computer to
computer
Condition Code Register or Flag Register
Depending on the outcomes of Arithmetic or Logical
operations, we can branch and jump
The eight-bit Condition Code Register (CCR) provides a
status report on the ALU's activity
Carry/Borrow
Half carry from bit 3 to bit 4
oVerflow
CCR also provides a status report after loading ACC
Zero
Negative
V Z N H C
Condition Code Register (CCR)
They flag certain conditions resulting from the ALU
outcomes
Example:
A= 01001000 B= 01111001
A+B:
A 01001000
B +01111001
11000001 V=1 Z=0 N=1 H=1 C=0
BOOK2 BOOK2
BOOK1 BOOK1
You can also take a book off the top of the stack:
BOOK3
BOOK3
BOOK2 BOOK2
BOOK1 BOOK1
D4 D4 D5 D6 D6
SP
11 D3 D3 D3 D3 D3 D3
10 D2 D2 D2 D2 D2 D2
01 D1 D1 D1 D1 D6 D6
00 D4 D4 D5 D5 D5
SP=11 SP=00 SP=11 SP=00 SP=01 SP=00
Stack Pointer
The stack is a way of using
the memory. SP
All that's needed is some Address $A000
unused memory and an $A000 D0 $9FFF
index register, called
the Stack Pointer (SP), $9FFF D1 $9FFE
that always points to the $9FFE D2 $9FFD
next available (empty)
location above the current $9FFD D3 $9FFC
top of the stack $9FFC D4 $9FFB
The stack grows toward $9FFB
lower addresses
$9FFA
Control Unit
The control unit is a synchronous sequential
logic circuit that sends control signals to the data
processing unit, memory and other parts of the
system
The signals from the control unit tells the data
processing unit to manipulate data according to
the algorithm built into the sequential logic circuit
The control unit is instruction controlled;
therefore it can do more than one algorithm based
on its design (programmable)
Typical control units recognize several hundred
different instruction codes
System Clock
In order to regulate when the control unit issues its
control signals, computers use a system clock
Examples:
MC680x, MC68K, Intel40xx, Intel80xx,
Intel x86 (32bit and 64bit laptop, desktop, server systems),
IBM System-Z Mainframes and many other supercomputers
Examples:
ARM (iPad, iPhone, iPod, Blackberry, Android phones)
IBM Power PC (Wii, Xbox, Sony's PS)
Oracle (SUN) Sparc
Embedded applications
Single board computers
Instruction Set Differences
START LDAA, <$0080> : load ACCA the contents of memory address <$0080>
ADDA, <$0081> : Add ACCA the contents of memory address <$0081>
STAA, <$0082> : Store contents of ACCA to the memory address <$0082>
point to point
network
Reliability and safety
Cortex-M0+ Core and Processor
NXP Kinetis KL25Z family microcontroller
*NXP KL25Z128VLK4
Development Board
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Simplified structure of the CPU core
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ARM Processor Core Registers
ARM Processor Core Registers (32 bits each)
R0-R12 - General purpose registers for data
processing
SP - Stack pointer (R13)
Can refer to one of two SPs
Main Stack Pointer (MSP)
Process Stack Pointer (PSP)
Uses MSP initially, and whenever in Handler mode
When in Thread mode, can select either MSP or PSP
using SPSEL flag in CONTROL register.
LR - Link Register (R14)
Holds return address when called with Branch & Link
instruction (B&L)
PC - program counter (R15)
Operating Modes
Reset
Thread
Mode.
MSP or PSP.
Exception Starting
Processing Exception
Completed Processing
Handler
Mode
MSP