1

GURU TEGH BAHADUR

INSTITUTE OF TECHNOLOGY

FREE IN-HOUSE TRAINING ON

TANNER EDA TOOL

SUBMITTED BY:
PIYUSH MALHOTRA
20213202815
ECE-II,THIRD YEAR

MENTOR:
MS. VIDISHA KHETARPAL
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ACKNOWLEDGEMENT

I have taken efforts in this project. However, it would not

have been possible without the kind support and help of
many individuals. I would like to extend my sincere thanks
to all of them.

I am highly indebted to Ms. Vidisha Khetarpal for her

guidance and constant supervision as well as for providing
necessary information regarding the project & also for their
support in completing the project.
I would like to express my special gratitude and thanks to
the college and the management team for providing free
in-house winter training.
3

CERTIFICATE

This is to certify that Piyush Malhotra,20213202815, S/O

Suresh Malhotra, a student of B. Tech (Electronics and
communication Engineering), Guru Tegh Bahadur Institute
Of Technology,New Delhi has successfully completed Free
In-House Training in Tanner EDA tools in the winter
vacations of 2017-18,from 26th December 2017 to 5th
January 2018.

We wish him success in his future endeavors.

MUKESH SAHU VIDISHA KHETARPAL

Head of Department Teacher-In-Charge
Electronics and Communication Engineering
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CONTENTS

S.NO CONTENTS PAGE NO

1. Abstract 5
2. Introduction 7
3. Methodology and Software used 12
4. Schematic Edit 25
5. T-Spice and Waveform Edit 30
6. Project(Half Adder) 40
7. Conclusion 45
8. Reference 46
5

ABSTRACT

Very-large-scale integration (VLSI) is the process of creating an

integrated circuit (IC) by combining hundreds of thousands of
transistors or devices into a single chip. VLSI began in the 1970s
when complex semiconductor and communication technologies
were being developed. The microprocessor is a VLSI device. Before
the introduction of VLSI technology most ICs had a limited set of
functions they could perform. An electronic circuit might consist of a
CPU, ROM, RAM. VLSI lets IC designers add all of these into one chip.

NMOS uses n-type field effect transistors (MOSFETs) to implement

logic gates and other digital circuits. These nMOS transistors
operate by creating an inversion layer in a p-type transistor body.
This inversion layer, called the n-channel, can conduct electrons
between n-type "source" and "drain" terminals. The n-channel is
created by applying voltage to the third terminal, called the gate.

PMOS logic uses p-channel MOSFETs to implement logic gates and

other digital circuits. PMOS transistors operate by creating an
inversion layer in an n-type transistor body. This inversion layer,
called the p-channel, can conduct holes between p-type "source"
and "drain" terminals. The p-channel is created by applying voltage
to the third terminal, called the gate.

PMOS and NMOS transistors have four modes of operation: cut-off

(or sub threshold), triode, saturation (sometimes called active), and
velocity saturation.

In CMOS technology, both above kinds of transistors are used in a

complementary way to form a current gate that forms an effective
means of electrical control. CMOS transistors use almost no power
when not needed. As the current direction changes more rapidly,
however, the transistors become hot. This characteristic tends to
limit the speed at which microprocessors can operate.. CMOS
technology is used in microprocessors, micro controllers, static RAM,
and other digital logic circuits. CMOS technology is also used for
several analog circuits such as image sensors (CMOS sensor), data
converters, and highly integrated transceivers for many types of
communication.
6

CHAPTER

1.
7

INTRODUCTION

The MOS System under External Bias

We now turn our attention to the electrical behavior of the MOS structure under
externally applied bias voltages. Assume that the substrate voltage is set at VB = 0,
and let the gate voltage be the controlling parameter. Depending on the polarity and
the magnitude of VG, three different operating regions can be observed for the MOS
system: accumulation, depletion, and inversion. If a negative voltage VG is applied to
the gate electrode, the holes in the p-type substrate are attracted to the semiconductor-
oxide interface. The majority carrier concentration near the surface becomes larger
than the equilibrium hole concentration in the substrate; hence, this condition is
called carrier accumulation on the surface (Fig.1 ). Note that in this case, the oxide
electric field is directed towards the gate electrode. The negative surface potential
also causes the energy bands to bend upward near the surface. While the hole density
near the surface increases as a result of the applied negative gate bias, the electron
(minority carrier) concentration decreases as the negatively charged electrons are
pushed deeper into the substrate.(1)

Figure (1):- The cross-sectional view and the energy band diagram of the MOS structure in surface
inversion, under larger gate bias voltage.
courtesy:- S.M. kang. Y. Lebiebici, “CMOS digital integrated circuits analysis & design”

Structure and Operation of MOS Transistor (MOSFET)

The basic structure of an n-channel MOSFET is shown in Fig. 2 This four-terminal
device consists of a p-type substrate, in which two n+ diffusion regions, the drain and
the source, are formed. The surface of the substrate region between the drain and the
source is covered with a thin oxide layer, and the metal (or polysilicon) gate is
deposited on top of this gate dielectric. The midsection of the device can easily be
recognized as the basic MOS structure which was examined in the previous sections.
The two n+ regions will be the current-conducting terminals of this device. Note that
the device structure is completely symmetrical with respect to the drain and source
regions; the different roles of these two regions will be defined only in conjunction
with the applied terminal voltages and the direction of the current flow.
8

Figure (2):- The physical structure of an n-channel enhancement-type MOSFET

courtesy:- S.M. kang. Y. Lebiebici, “CMOS digital integrated circuits analysis & design”

A conducting channel will eventually be formed through applied gate voltage in the
section of the device between the drain and the source diffusion regions. The distance
between the drain and source diffusion regions is the channel length L, and the lateral
extent of the channel (perpendicular to the length dimension) is the channel width W.
Both the charnel length and the channel width are important parameters which can be
used to control some of the electrical properties of the MOSFET. The thickness of the
oxide layer covering the channel region, t x, is also an important parameter. A MOS
transistor which has no conducting channel region at zero gate bias is called 'an
enhancement-type (or enhancement-mode) MOSFET. If a conducting channel already
exists at zero gate bias, on the other hand, the device is called a depletion-type
(MOSFET). In a MOSFET with p-type substrate and with n+ source and drain
regions, the channel region to be formed on the surface is n-type. Thus, such a device
with p-type substrate is called an n-channel MOSFET. In a MOSFET with n-type
substrate and with p+ source and drain regions, on the other hand, the channel is p-
type and the device is called a p-channel MOSFET.(2)

Figure( 3):- N channel mosfet and P channel mosfet

courtesy S.M. kang. Y. Lebiebici, “CMOS digital integrated circuits analysis & design”
oNMOS
N-type metal-oxide-semiconductor logic uses n-type field-effect
transistors (MOSFETs) to implement logic gates and other digital circuits.
These NMOS transistors operate by creating an inversion layer in a p-
type transistor body. This inversion layer, called the n-channel, can
conduct electrons between n-type "source" and "drain" terminals. The n-
channel is created by applying voltage to the third terminal, called the gate
9

Like other MOSFETs, NMOS transistors have four modes of operation: cut-off
(or subthreshold), triode, saturation (sometimes called active), and velocity
saturation. MOS stands for metal-oxide-semiconductor, reflecting the way
MOS-transistors were originally constructed, predominantly before the 1970s,
with gates of metal, typically aluminium. Since around 1970, however, most
MOS circuits have used self-aligned gates made of polycrystalline silicon.
These silicon gates are still used in most types of MOSFET based integrated
circuits, although metal gates (Al or Cu) started to reappear in the early 2000s
for certain types of high speed circuits, such as high performance
microprocessors.

The MOSFETs are n-type enhancement mode transistors, arranged in a so-

called "pull-down network" (PDN) between the logic gate output and negative
supply voltage (typically the ground). A pull up (i.e. a "load" that can be
thought of as a resistor, see below) is placed between the positive supply
voltage and each logic gate output. Any logic gate, including the logical
inverter, can then be implemented by designing a network of parallel and/or
series circuits, such that if the desired output for a certain combination of
boolean input values is zero (or false), the PDN will be active, meaning that at
least one transistor is allowing a current path between the negative supply
and the output. This causes a voltage drop over the load, and thus a low
voltage at the output, representing the zero.(3)

Figure:- (4)

courtesy- S.M. kang. Y. Lebiebici, “CMOS digital integrated circuits analysis & design”

PMOS
P-type metal-oxide-semiconductor logic uses p-channel metal-oxide-
semiconductor field effect transistors (MOSFETs) to implement logic gates
and other digital circuits. PMOS transistors operate by creating an inversion
layer in an n-type transistor body. This inversion layer, called the p-channel
can conduct holes between p-type "source" and "drain" terminals.
10

The p-channel is created by applying voltage to the third terminal, called the
gate. Like other MOSFETs, PMOS transistors have four modes of operation:
cut-off (or subthreshold), triode, saturation (sometimes called active), and
velocity saturation.
While PMOS logic is easy to design and manufacture (a MOSFET can be
made to operate as a resistor, so the whole circuit can be made with PMOS
FETs), it has several shortcomings as well. The worst problem is that there is
a direct current (DC) through a PMOS logic gate when the PUN is active, that
is, whenever the output is high, which leads to static power dissipation even
when the circuit sits idle.
Also, PMOS circuits are slow to transition from high to low. When transitioning
from low to high, the transistors provide low resistance, and the capacitive
charge at the output accumulates very quickly (similar to charging a capacitor
through a very low resistance). But the resistance between the output and the
negative supply rail is much greater, so the high-to-low transition takes longer
(similar to discharge of a capacitor through a high resistance). Using a
resistor of lower value will speed up the process but also increases static
power dissipation.(4)

Figure:- (5)
courtesy- S.M. kang. Y. Lebiebici, “CMOS digital integrated circuits analysis & design”

CMOS
Complementary metal–oxide–semiconductor, abbreviated as CMOS is a
technology for constructing integrated circuits. CMOS technology is used in
microprocessors, micro controllers, static RAM, and other digital logic circuits.
CMOS is also sometimes referred to as complementary-symmetry metal–oxide–
semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the
fact that the typical design style with CMOS uses complementary and symmetrical
pairs of p-type and n-type metal oxide semiconductor field effect transistors
(MOSFETs) for logic functions. Two important characteristics of CMOS devices are
high noise immunity and low static power consumption. Since one transistor of the
pair is always off, the series combination draws significant power only momentarily
during switching between on and off states.(5)
11

CHAPTER

2.
12

Methodology and Software used.

The VLSI Design Process (6)

• The Design Process : An iterative process that refines an "idea" to a

manufacturable device through at least five levels of design abstraction.
Abstraction : A very effective means of dealing with design
complexity. Creating a model at a higher level of abstraction
involves replacing detail at the lower level with simplifications.
Simulation : The functional behavior of the design (or a parameter
such as power) is determined by applying a set of excitation
vectors to a circuit model.

Hierarchy and Abstraction

• Moore's Law: Integration density doubles every 18 months.

For example, Microprocessors: The million transistor/chip barrier crossed
in `88 with the 486.

• Hierarchy is used in the design of the Pentium. The processor is a

collection of modules each composed of cells. Re-use of cells reduces
design effort and increases the chance of a first-time right
implementation. The use of hierarchy is a key ingredient to the success of
the digital circuit. Reason why large analog designs never caught on.

• Abstraction is also possible in digital designs. And difficult to apply

effectively to analog designs. This divide and conquer ( hierarchical )
approach allows the designer to deal with a much smaller number of well
characterized modules (or abstractions ).

• Abstraction levels:
• Physical level : Rectangles, design rules.
• Circuit level : Transistors, R and C, analog voltage/current values.
• Switch level: Transistors, R and C, multi-valued logic.
• Logic level : Boolean logic gates, binary valued logic.
• Register Transfer Level : Adders, datapaths, binary valued words.
• Functional level : Processors, programs and data structures.

• Entire TANNER design frameworks are based on this design philosophy.

These have made it possible to achieve current design complexity.

• Design tools include:

• Simulation at various complexity levels.
• Design verification.
• Layout generation.
• Design synthesis.
13

• Standard cells are a popular design style that makes layout generation
easy. Layouts of basic gates such as AND, OR, NAND, NOR, and NOT as
well as arithmetic and memory modules are provided as input. These
cells are designed with similar characteristics, such as constant height,
and can be manipulated easily to generate a layout.

Analysis Methodology(7):

DC operating point analysis finds a circuit’s steady- state condition, obtained (in
principle) after the input voltages have been applied for an infinite amount of
time. The .include command causes T- Spice to read in the contents of the
model file for the evaluation of NMOS and PMOS transistors.

The technology file assigns values to MOSFET model parameters for both n - and
p -type devices. When read by the input file, these parameters are used to
evaluate MOSFET model equations, and the results are used to construct
internal tables of current and charge values. Values read or interpolated from
these tables are used in the computations called for by the simulation. Following
each transistor name are the names of its terminals. The required order of
terminal names is: drain -gate -source -bulk. Then the model name (NMOS or
PMOS in this example), and physical characteristics such as length and width,
are specified. The .op command performs a DC operating point calculation and
writes the results to the file specified in the Simulate > Start Simulation dialog.
The output file lists the DC operating point information for the circuit described
by the input file.

DC Transfer Analysis

DC transfer analysis is used to study the voltage or current at one set of points
in a circuit as a function of the voltage or current at another set of points. This is
done by sweeping the source variables over specified ranges, and recording the
output. A list of sources to be swept, and the voltage ranges across which the
sweeps are to take place follow the .dc command, indicating transfer analysis.
The transfer analysis will be performed as follows: vdd will be set at 5 volts and
vin will be swept over its specified range; vdd will then be incremented and vin
will be reswept over its range; and so on, until vdd reaches the upper limit of its
range. The .dc command ignores the values assigned to the voltage sources vdd
and vin in the voltage source statements, but they must still be declared in
14
those statements. The results for nodes in and out are reported by the .print dc
command to the specified destination.
15

Transient Analysis

Transient analysis provides information on how circuit elements vary with time.
The basic T- Spice command for transient analysis has three modes. In the
default mode, the DC operating point is computed, and T- Spice uses this as the
starting point for the transient simulation. The .tran command specifies the
characteristics of the transient analysis to be performed.

AC Analysis

AC analysis characterizes the circuit’s behavior dependence on small- signal

input frequency. It involves three steps: (1) calculating the DC operating point;
(2) linearizing the circuit; and (3) solving the linearized circuit for each
frequency. When ac voltage source is to be applied, then vdiff sets the DC
voltage difference between nodes the two nodes to -0. 0007 volts; its AC
magnitude is 1 volt and its AC phase is 180 degrees. The .ac command performs
an AC analysis. Following the .ac keyword is information concerning the
frequencies to be swept during the analysis. In case, the frequency is to be
swept logarithmically, by decades (DEC); 5 data points are to be included per
decade is considered to be the standard The two .print commands write the
voltage magnitude (in decibels) and phase (in degrees), respectively, for the
node out to the specified file. The .acmodel command writes the small- signal
model parameters and operating point voltages and currents for all circuit
devices

Noise Analysis

Real circuits, of course, are never immune from small, random fluctuations in
voltage and current levels. In T- Spice, the influence of noise in a circuit can be
simulated and reported in conjunction with AC analysis. The purpose of noise
analysis is to compute the effect of the noise associated with various circuit
devices on an output voltage or voltages as a function of frequency. Noise
analysis is performed in conjunction with AC analysis; if the .ac command is
missing, then the .noise command is ignored. With the .ac command present,
the .noise command causes noise analysis to be performed at the same
16
frequencies. The .noise command takes two arguments: the output at which the
effects of noise are to be computed, and the input at which the .noise can be
considered to be concentrated for the purposes of estimating the equivalent
noise spectral density. The print command is used to print results.
17

Introduction to Tanner Tool(8)

Tanner tool is a Spice Computer Analysis Programmed for Analogue Integrated

Circuits. Tanner tool consists of the following Engine Machines:

1.S-EDIT (Schematic Edit)

2.T-EDIT (Simulation Edit)

3.W-EDIT (Waveforms Edit)

Using these engine tools, spice program provides facility to the use to design &
simulate new ideas in Analogue Integrated Circuits before going to the time
consuming & costly process of chip fabrication.

SCHEMATIC EDIT TOOL (S-EDIT)

S-Edit is hierarchy of files, modules & pages. It introduces symbol & schematic
modes. S-Edit provides the facility of:

1.Beginning a design.

2.Viewing, drawing & editing of objects.

3.Design connectivity.

4. Properties, net lists & simulation.

5.Instance & browse schematic & symbol mode.

Beginning a design: It explains the design process in detail in terms of file

module operation and module.

Browser: Effective schematic design requires a working knowledge of the S-Edit

design hierarchy of files & modules. S-Edit design files consist of modules. A
module is a functional unit of design such as a transistor, a gate and an
amplifier.

Modules contain two components:

1)Primitives: Geometrical objects created with drawing tools.

18

2) Instances: References to other modules in file. The instanced module is the

original.

S-Edit has two viewing modes:

1.Schematic Mode: to create or view a schematic, we operate in

schematic mode.

2.Symbol Mode: it represents symbol of a larger functional unit such as

operational amplifier.

CIRCUIT SIMULATOR -T-SPICE

An introduction to the integrated components of the T- Spice Pro circuit analysis

suite:

Schematic data files (.sdb): describes the circuits to be analyzed in graphical

form, for display and editing by S- Edit" Schematic Editor.

Simulation input files (.sp): describes the circuits to be analyzed in textual

form, for editing and simulation by T- Spice" Circuit Simulator.

Simulation output files (.out): containing the numerical results of the circuit
analyses, for manipulation and display by W- Edit" Waveform Viewer.

T- Spice Pro’s waveform probing feature integrates S- Edit, T- Spice, and W- Edit
to allow individual points in a circuit to be specified and analyzed. A few analysis
19
is described below:

The heart of T-Spice operation is the input file (also known as the circuit
description, the net list & the input deck). This is a plain text file that contains
the device statement &
20
simulation commands, drawn from the SPICE circuit description language with
which T-Spice constructs a model of the circuit to be simulated. Input files can
be created and modified with any text editor.

T-Spice is a tool used for simulation of the circuit. It provides the facility of

1. Design Simulation

2. Simulation Commands

3. Device Statements

4. User-Designed External Models

5. Small Signal & Noise Models

T-Spice uses Kirchhoff’s Current Law (KCL) to solve circuit problems. To T-Spice, a
circuit is a set of devices attached to nodes. The voltage at all nodes represents
the circuit state. T-Spice solves for a set of node voltage that satisfied KCL
(implying that sum of currents flowing into each node is zero). In order to
evaluate whether a set of node voltages is a solution, T-Spice computers and
sums all the current flowing out of each device into nodes connected to it (its
terminals). The relationship between the voltages at device terminals and the
currents through the terminal is determined by the device model for a resistor of
resistance R is

I=∆V/R

Where, ∆V represents the voltage difference across the device. A few analyses
are discussed below:
21
22

WAVEFORM EDIT

The ability to visualize the complex numerical data resulting from VLSI circuit
simulation is critical to testing, understanding & improving these circuits. W-Edit
is a waveform viewer that provides ease of use, power & speed in a flexible
environment designed for graphical data representation. The advantages of W-
Edit include:

1. Tight Integration with T-spice, Tanner EDA_s circuit level simulator. W-Edit can
chart data generated by T-spice directly, without modification of the output
text data files. The data can also be charted dynamically as it is produced during
the simulation.

2. Charts can automatically configure for the type of data being presented.

3. A data is treated by W-Edit as a unit called a trace. Multiple traces from

different output files can be viewed simultaneously in single or several windows;
traces can be copied and moved between charts & windows. Trace arithmetic
can be performed on existed tracing to create new ones.

4. Chart views can be panned back & forth and zoomed in & out, including
specifying the exact X-Y co-ordinate range.

5. Properties of axes, traces, rides, charts, text & colors can be customized.

Numerical data is input to W-Edit in the form of plain or binary text files. Header
& Comment information supplied by T-Spice is used for automatic chart
configuration. Runtime update of results is made possible by linking W-Edit to a
23
running simulation in T-Spice. W-Edit saves data with chart, trace, axis &
environment settings in files with the WDB (W-Edit Database).
24

CHAPTER

3.
25

S-edit :

PROCEDURE:-
1. Open S-edit; then create a new design file
File→ New→ Newdesign and save the file with design name.
2. Then add the library files
Add→ Documents→ Tanner EDA→ Tanner tools v13.0→ Libraries→
All→All.tanner
3. To open the schematic view, select schematic in view 0 and then click ok. Cell→
New view→ Ok
4. Draw the design and then check for errors and then save the design.
5. Then generate the net list program of schematic. Tools→ T-spice.

NMOS using single source

PMOS using single source

26

NMOS using double source

PMOS using double source

27

CMOS inverter (DC analysis)

CMOS inverter (transient analysis)

NOR using cmos (dc analysis)

28

NOR using cmos (transient analysis)

NAND using cmos (dc analysis)

NAND using cmos (transient analysis)

29

CHAPTER

4.
30

T-spice :

N-mos with single source

NMOS with double source

PMOS with single source

31

PMOS with double source

CMOS with DC analysis

CMOS with Transient analysis

32

NOR with DC analysis

NOR with Transient analysis

33

NAND with DC analysis

NAND with Transient anaylsis

34

WAVEFORM EDITS:

NMOS using single source

PMOS using single source

NMOS using double source

35

PMOS using double source

CMOS

inverter (DC analysis)

CMOS inverter (transient analysis)

36
37

NOR using cmos (dc analysis)

NOR using cmos (transient analysis)

NAND using cmos (dc analysis)

38

NAND using cmos (transient analysis)

39

CHAPTER

5.
40

PROJECT

Half Adder using CMOS

THEORY:-
An adder is a digital circuit that performs addition of numbers. In
many computers and other kinds of processors adders are used in
the arithmetic logic units or ALU. They are also utilized in other
parts of the processor, where they are used to calculate addresses,
table indices, increment and decrement operators, and similar
operations.
Although adders can be constructed for many number
representations, such as binary coded decimal or excess-3, the
most common adders operate on binary numbers. In cases where
two's complement or ones' complement is being used to represent
negative numbers, it is trivial to modify an adder into an adder .
Other signed number representations require more logic around the
basic adder.
41

Schematic

inverter schematic

carry schematic
42

SUM schematic

HALF ADDER
43

OUTPUT WAVEFORM
W-EDIT
44

CHAPTER

6.
45

CONCLUSION

Although EDA tools offer lot of opportunities to design variety of

electronic chips, there are disadvantages too. EDA tools are expensive,
many of the tools are not easy to install on a computer system. Many of the
tools are not user friendly enough to learn, and there are not many experts
available to teach the EDA tools. While the tools available in colleges are
good, however, lack of experts to teach the tool, the students are not
continuing in EDA domain, rather they are moving into other domains,
such as software. If we educate the students about the EDA tools in their
early education levels, and if the EDA tools are made cost effective, we
can see more students in EDA domain, creating more expertise and better
growth in the EDA domain.

Some of the advantages of EDA tools are minimizing time in designing

complex ICs, eliminating manufacturing errors, reducing manufacturing
costs, optimizing the IC design and simplicity of usage etc.

Before EDA tools developed, circuit designers used to depend on manually

drawing the circuit on a paper or some geometric software to design a
circuit.
As described above, EDA tools generally follow a flow. The design flow
can be divided into two designs, digital design and analog design. In
digital design a circuit is described using a hardware description language,
followed by simulation of circuit design, synthesis, place & route and post
layout simulation. In analog design, a circuit is captured, followed by
simulation, physical design, layout extraction and post layout simulation.
The combined layouts of digital and analog designs are used in a
manufacturing facility to produce an electronic chip.
46

REFERENCE

SUNG MO KANG & YUSUF LEBIEBICI’S CMOS digital

integrated circuit (analysis and design) (TATA McGRAW HILL’S )
• (1)S.M. kang. Y. Lebiebici, “CMOS digital integrated circuits
analysis & design” page no- 52
• (2) S.M. kang. Y. Lebiebici, “CMOS digital integrated circuits
analysis & design” page no- 55,56
• (3) Internet:-
https://www.webopedia.com/TERM/N/NMOS.html
• (4)Internet:-
tuttle.merc.iastate.edu/ee230/topics/mosfets/pmos.pdf
• (5) Internet :- https://techterms.com/definition/cmos
•Figure:- (1) courtesy S.M. kang. Y. Lebiebici, “CMOS digital
integrated circuits analysis & design” page no:- 54
•Figure:- (2) courtesy S.M. kang. Y. Lebiebici, “CMOS digital
integrated circuits analysis & design” page no:- 55
•Figure:- (3) courtesy- S.M. kang. Y. Lebiebici, “CMOS digital
integrated circuits analysis & design” page no:- 56
•Figure:-(4) courtesy:- S.M. kang. Y. Lebiebici, “CMOS digital
integrated circuits analysis & design” page no:- 77
•Figure:-(5) courtesy:- S.M. kang. Y. Lebiebici, “CMOS digital
integrated circuits analysis & design” page no:- 77

(6) http://ece-research.unm.edu/jimp/vlsi/slides/c1_intro.html

(7) http://www.wrcad.com/manual/wrsmanual/node5.html

(8) https://www.scribd.com/doc/75568595/Introduction-to-Tanner-Tool