01-03-2023

Von Neumann (Princeton) and Harvard Architecture

(a) Von Neumann architecture (b) Harvard architecture

❖ 8051 Microcontroller: Hardware, Software & Applications, V Udayashankara, M S Mallikarjunaswamy, TMH, 2009 DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA
❖ 8051 Microcontroller Internals, Instructions, Programming and Interfacing, Subrata Ghoshal, Pearson, 2010

Introduction
(a) General-purpose Microprocessor System (b) Microcontroller

❖ Must add RAM, ROM I/O ports, timers to make system functional.
❖ Versatility on the amount of RAM,ROM and I/O ports

❖ Fixed amount of On chip ROM,RAM and I/O ports make them ideal
for many applications where cost and space are critical.
❖ The space, the power consumption and price per unit is much more
critical then computing power
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Comparison Between 8085 and MCS-51

Similarities between 8085 and 8051

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

❖ 8051 Microcontroller Internals, Instructions, Programming and Interfacing, Subrata Ghoshal, Pearson, 2010

Comparison Between 8085 and MCS-51

Differences between 8085 and 8051 DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA
❖ 8051 Microcontroller Internals, Instructions, Programming and Interfacing, Subrata Ghoshal, Pearson, 2010

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Criteria for Choosing a Microcontroller

Meeting the computing needs of the task and cost
❖ Speed
❖ Packaging
❖ Power consumption
❖ Amount of RAM and ROM
❖ Number of I/O pins and timers
❖ Easy Upgradation
❖ Cost per unit
❖ Size, Number of bits (8, 16, 32)
❖ Reliable manufacturers like Motorola, Intel, Zilog, Atmel, Microchip, Maxim, Philips, AMD,
Dallas Semiconductors, Signetics, NEC, Fujitsu, Infineon, Freescale, STMicroelectronics,
NXP, Texas etc
❖ Availability of software development tools like compilers, assemblers and debuggers
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Overview Of 8051 Family – 8051 Microcontroller

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

❖ 8051 Microcontroller: Hardware, Software & Applications, V Udayashankara, M S Mallikarjunaswamy, TMH, 2009

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Overview Of 8051 Family – 8051 Microcontroller

Versions of 8051/52 Microcontroller From Dallas Semiconductor (Maxim) Versions of 8051 From Atmel (All ROM Flash)

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

The 8051 Microcontroller and Embedded Systems: Using Assembly and C, 2nd. ed. Mazidi, Mazidi and McKinlay

MCS-51 Microcontroller Naming Convention

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

❖ 8051 Microcontroller Internals, Instructions, Programming and Interfacing, Subrata Ghoshal, Pearson, 2010

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Microprogrammed Control Organization

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Microprogrammed Control Unit

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Hardwired Control Unit

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Pipelining Concept

❖ Pipelining is an effective way of organizing concurrent activity in a computer system.

❖ The pipelined processor completes the processing of one instruction in each clock cycle.
❖ The potential increase in performance resulting from pipelining is proportional to the number of
pipeline stages. The rate of instruction processing is four times than that of sequential operation
for 4 stage pipeline.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Two Stage Pipeline

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Four Stage Pipeline

❖ F (Fetch): Read the instruction from the memory.
❖ D (Decode): Decode the instruction and fetch the
source operand(s).
❖ E (Execute): Perform the operation specified by the
instruction.
❖ W (Write): Store the result in the destination location.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Block diagram of 8051 Microcontroller

128/

System bus ❖ Note that the interfacing of program

memory with the system bus is
marginally different from other
interfacing.
❖ We must remember that data bus
is unidirectional from program
memory while address and control
bus directions are similar as other
devices.
The 8051 Microcontroller and Embedded Systems: Using Assembly and C, 2nd. ed. Mazidi, Mazidi and McKinlay DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA
8051 Microcontroller: Hardware, Software & Applications, V Udayashankara, M S Mallikarjunaswamy, TMH, 2009

Architectural block diagram of microcontroller 8051

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

The 8051 Microcontroller Architecture, Programming and applications, Ayala, K. J., Penram International Publishing (India) Pvt. Ltd., 2007

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Salient features: 8051 Microcontroller

❖ 8 bit CPU with registers A (the accumulator) and register B, 8 bit ALU and working registers

❖ 16 bit Program counter (PC) and Data pointer (DPTR)

❖ Eight bit program status word (PSW) and eight bit stack pointer (SP)

❖ Internal ROM or EPROM (8751) of 0 (8031) to 4 Kbytes (8051) of on-chip program memory

❖ Internal on-chip RAM of 128 bytes data

❖ Four register banks, each containing eight registers

❖ Sixteen bytes, which may be addressed at the bit level

❖ Eight bytes of general-purpose memory

❖ 16 bit address bus multiplexed with port 0 and port 2 and 8 bit data bus multiplexed with port 0

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Salient features: 8051 Microcontroller

❖ 64 Kbytes of external program/code memory address space (Only Read) PSEN controlled

❖ 64 Kbytes of external data memory address space (Read and Write) RD, WR Controlled

❖ 32 bidirectional Input/Output pins (as four 8 bit ports (P0-P3)) or 32 individually addressable I/O lines

❖ Two 16 bit timers/counters: T0 and T1

❖ Full duplex serial asynchronous data receiver/transmitter (UART): SBUF

❖ 6 sources/Five-vector interrupt structure with two priority levels (Two external and three internal and

Reset)

❖ One on Chip Oscillator and clock circuits

❖ Control Registers: TCON, TMOD, SCON, PCON, IP and IE

❖ Code memory selectable by EA DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Programming Model of microcontroller 8051

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

The 8051 Microcontroller Architecture, Programming and applications, Ayala, K. J., Penram International Publishing (India) Pvt. Ltd., 2007

Pin Diagram of 8051

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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8051 Reset Circuit

❖ 8051 can be reset in two ways 1) Power-on reset – which resets the 8051 when power is turned ON and 2) manual
reset – in which a reset happens only when a push button is pressed manually.
❖ For reset to happen, the reset input pin (pin 9) must be active high for at least 2 machine cycles.
❖ During a reset operation :- Program counter is cleared and it starts from 00H, register bank #0 is selected as default,
Stack pointer is initialized to 07H, all ports are written with FFH. A reset doesn’t affect contents of internal RAM.
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Reset values for XX51

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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CPU Timing/System Clock

❖ All MCS-51 microcontrollers have an on-chip oscillator
which can be used if desired as the clock source for the CPU.
❖ To use the on-chip oscillator, connect a crystal or ceramic
resonator between the XTAL1 and XTAL2 pins of the
12 MHz
microcontroller, and capacitors to ground.

Figure: Using the On-Chip Oscillator

A. HMOS or CHMOS B. For HMOS only C. For CHMOS only

Figure: Using an External Clock DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

❖ A general practice is to use an external crystal of 12 MHz frequency. For the systems using serial
communications facilities, a crystal of frequency 11.0592 MHz is used for the standard baud rates (9600,
4800, etc.) generation.
❖ Internally, multiple numbers of this system clock oscillation are used for various purposes. Each complete
oscillation of the external crystal or clock source is a pulse, two such pulses produce a state. Six states
generate one machine cycle. Instructions need one, two or four such machine cycles for fetching the opcode
and its execution
❖ ALE signal can be monitored through an oscilloscope and every machine cycle would generate two ALE
pulses. As MCS-51 depends on micro-programming, therefore so many pulses are necessary.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Program Memory Organisation Data Memory Organisation

Arrangement of program memory in XX51 Arrangement of internal and external data memory of XX51/52
with (a) EA = 1 and (b) EA = 0

❖ The internal data memory of 8051 is divided into three

separate functional parts as
❖ Register banks (address 00H to 1FH),
❖ Bit-addressable area (address 20H to 2FH) and
❖ Scratch-pad area (address 30H onwards).

❖ 8051 Microcontroller Internals, Instructions, Programming and Interfacing, Subrata Ghoshal, Pearson, 2010 DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Registers
❖ Register are used to store information temporarily, while the information could be
❖ A byte of data to be processed, or
❖ An address pointing to the data to be fetched
❖ The vast majority of 8051 register are 8-bit registers
❖ There is only one data type, 8 bits
❖ The most widely used registers
❖ A (Accumulator)
❖ For all arithmetic and logic instructions
❖ B, R0, R1, R2, R3, R4, R5, R6, R7
❖ DPTR (data pointer), and PC (program counter)

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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ALU- Arithmetic Logic Unit and Accumulator (‘A’ Reg)

❖ The ALU performs the computing functions.

❖ The accumulator is an 8 bit SFR register, both bit and byte addressable. In arithmetic and
logical operations, one of the operands is in ‘A’ register. After the arithmetic/logical operations
are performed, the result is stored in ‘A’ register and this affects Carry (CY), Auxiliary Carry
(AC), Overflow (O), and Parity (P) flags.
❖ In multiplication operation, one of the 8 bit operands is stored in ‘A’ register. After the
operation, it stores the lower byte of the result in ‘A’ register.
❖ In division operation, it holds an 8 bit dividend and after the operation, the quotient is stored in
the accumulator. It is also used in indexed addressing mode to access information from
program memory.
❖ Register A cannot be addressed indirectly.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

B-Register

❖ The 8 bit ‘B’ SFR is used during multiply and divide operations.
❖ In multiplication operation (MUL AB), one of the 8 bit operands is stored in ‘B’ register.
After the operation, it stores the higher byte of the result in ‘B’ register.
❖ In division operation (DIV AB), it holds 8 bit divisor and after the operation the remainder
is stored in ‘B’ register.
❖ For other instructions, it can be used as an 8 bit general purpose register.
❖ Register ‘B’ is bit addressable register and ‘B’ cannot be addressed indirectly.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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8051 Flag/PSW Register

❖ The Carry bit, also serves as
PSW.4 PSW.3
the “Accumulator” for a number
of Boolean operations.(other Direct Address D0H

than a Carry bit,)

❖ SETB C and CLR C
❖ SETB PSW.3 will make PSW.3
=1 and selects register bank 1

Signed arithmetic

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

❖ 8051 Microcontroller Internals, Instructions, Programming and Interfacing, Subrata Ghoshal, Pearson, 2010

Example

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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PC-Program Counter

❖ PC points to the address of next instruction to be executed from ROM

❖ It is 16 bit register means the 8051 can access program address from 0000H to FFFFH
i.e a total of 64KB of code.
❖ ORG instruction is used to initialize the PC.
❖ ORG 0000H means PC initialize by 0000H. After reset, the PC will be set to 0000H and
the CPU will start executing the first instruction stored at program memory location
0000H.
❖ PC is incremented after each instruction fetch from program ROM. It doesn’t have
internal address.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Stack and Stack Pointer (SP)

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Pushing onto Stack

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

The 8051 Microcontroller and Embedded Systems: Using Assembly and C, Mazidi, Mazidi and McKinlay

Popping From Stack

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

The 8051 Microcontroller and Embedded Systems: Using Assembly and C, Mazidi, Mazidi and McKinlay

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Data Pointer (DPTR) Register

❖ DPTR is a 16 bit register, divided into two 8-bit registers DPH and DPL. DPH for Higher
order 8 bits, DPL for lower order 8 bits.
❖ DPTR, DPH, DPL are SFRs in 8051.
❖ 8051 uses DPTR to furnish memory addresses for internal and external code access and
external data access.
❖ The Data Pointer (DPTR) is the 8051’s only user-accessible 16-bit (2-byte) register.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Architecture of MCS-51 Ports

FET pull-up at output
Output latch

(a) Output latch of one bit of port 1 (b) Output pin (showing 1 or 0 output) of port 1

Read output latch

Read buffer for port pin

(c) Reading from a port pin of port 1 (d) Reading output latch of port 1
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

❖ 8051 Microcontroller Internals, Instructions, Programming and Interfacing, Subrata Ghoshal, Pearson, 2010

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Port 0 Pin Structure

(1)

(0)

Figure: 8051 Port Bit Latches and I/O Buffers

❖ Port-0 can be configured as a normal bidirectional I/O port

❖ Used for address/data interfacing for accessing external memory
❖ When control is '1', the port is used for address/data interfacing.
❖ When the control is '0', the port can be used as a normal bidirectional I/O port
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Port 0 with Pull Up Resistors

Open Drain Connections

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Port 1 Pin Structure

TB2

TB1

To switch off this FET, a ‘1’ must be written at the D-flip–flop, before
the port pin-reading operation. This is very important.

Figure: 8051 Port Bit Latches and I/O Buffers

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Port 2 Pin Structure

TB2

TB1

Figure: 8051 Port Bit Latches and I/O Buffers

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Port 3 Pin Structure

TB2

TB1

Figure: 8051 Port Bit Latches and I/O Buffers

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

I/O Ports and Bit Addressability : Example

❖ Write the following programs.
(a) Create a square wave of 50% duty cycle on bit 0 of port 1.
(b) Create a square wave of 66% duty cycle on bit 3 of port 1.

(a) The 50% duty cycle means that the “on” and “off” states (or the high and low portions of
the pulse) have the same length. Therefore, we toggle P1.0 with a time delay in between
each state.
HERE: SETB P1.0 ;set to high bit 0 of port 1
LCALL DELAY ;call the delay subroutine
CLR P1.0 ;P1.0=0
LCALL DELAY
SJMP HERE ;keep doing it

Another way to write the above program is:

HERE: CPL P1.0 ;complement bit 0 of port 1
LCALL DELAY ;call the delay subroutine
SJMP HERE ;keep doing it

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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I/O Ports and Bit Addressability : Example…

❖ Write the following programs.
(a) Create a square wave of 50% duty cycle on bit 0 of port 1.
(b) Create a square wave of 66% duty cycle on bit 3 of port 1.

(b) The 66% duty cycle means the “on” state is twice the “off” state.

BACK: SETB P1.3 ;set port 1 bit 3 high

LCALL DELAY ;call the delay subroutine
LCALL DELAY ;call the delay subroutine again
CLR P1.3 ;clear bit 2 of port 1(P1.3=low)
LCALL DELAY ;call the delay subroutine
SJMP BACK ;keep doing it

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

I/O Ports and Bit Addressability : Single Bit Instructions

❖ Instructions that are used for single-bit operations are as follows:

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Checking an Input Bit

❖ Write a program to perform the following:
(a) keep monitoring the P1.2 bit until it becomes high
(b) when P1.2 becomes high, write value 45H to port 0
(c) send a high-to-low (H-to-L) pulse to P2.3

SETB P1.2 ;make P1.2 an input

MOV A,#45H ;A = 45H
AGAIN: JNB P1.2,AGAIN ;get out when P1.2 = 1
MOV P0,A ;issue A to P0
SETB P2.3 ;make P2.3 high
CLR P2.3 ;make P2.3 low for H-to-L

In this program, instruction “JNB P1.2,AGAIN” (JNB means jump if no bit) stays in the loop as
long as P1.2 is low. When P1.2 becomes high, it gets out of the loop, writes the value 45H to
port 0, and creates an H-to-L pulse by the sequence of instructions SETB and CLR.
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Checking an Input Bit: Example

❖ Assume that bit P2.3 is an input and represents the condition of an oven. If it goes high, it
means that the oven is hot. Monitor the bit continuously. Whenever it goes high, send a
high-to-low pulse to port P1.5 to turn on a buzzer.

HERE: JNB P2.3,HERE ;keep monitoring for high

SETB P1.5 ;set bit P1.5=1
CLR P1.5 ;make high-to-low
SJMP HERE ;keep repeating
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Read-Modify-Write Feature

The ports in 8051 can be accessed by the read-modify-write technique

This feature saves many lines of code by combining in a single instruction all three actions
1. CPU reads the latch of the port and performs the operation
2. Modify the latch
3. Writing to the port pin

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Instructions Reading a Latch (Read-Modify-Write)

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Writing “1” to Output Pin P1.X

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Writing “0” to Output Pin P1.X

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Reading “High” at Input Pin

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Reading “Low” at Input Pin

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Reading the Latch

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Assembling and Running An 8051 Program

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Assembler Directives
❖ Assembler directives (Pseudo Operations or instructions) tell the assembler to do something
other than creating the machine code for an instruction. In assembly language
programming, the assembler directives instruct the assembler to
❖ Process subsequent assembly language instructions
❖ Define program constants
❖ Reserve space for variables

❖ The following are the widely used 8051 assembler directives:

❖ ORG (origin): The ORG directive is used to indicate the starting address. It can be used
only when the program counter needs to be changed. The number that comes after ORG
can be either in hex or in decimal. Eg: ORG 0000H ;Set PC to 0000.
❖ If number not followed by H, its is decimal and the assembler will convert to Hex
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

8051 Data Types And Assembler Directives

❖ END: The END directive signals the end of the assembly module. It indicates the end of the
program to the assembler. Any text in the assembly file that appears after the END directive
is ignored. If the END statement is missing, the assembler will generate an error message.
❖ DB (DEFINE BYTE): The DB directive is used to define an 8 bit data. DB directive initializes
memory with 8 bit values. The numbers can be in decimal, binary, hex or in ASCII formats.
For decimal, the 'D' after the decimal number is optional, but for binary and hexadecimal, 'B'
and ‘H’ are required. For ASCII, the number is written in quotation marks (‘LIKE’ This).
❖ DATA1: DB 40H ;hex
❖ DATA2: DB 01011100B ;b i n a r y
❖ DATA3: DB 48 ; decimal
❖ DATA4: DB ' HELLO W’ ; ASCII

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Assembler Directives
❖ EQU and SET: EQU and SET directives assign numerical value or register name to the
specified symbol name. EQU is used to define a constant without occupying a memory
location or storage for data items but associates a constant value with label. When the
label appears in the program, its constant value will be substituted for the label. The
symbol defined with EQU should not be redefined.
❖ SET directive allows redefinition of symbols at a later stage.
❖ By the use of EQU directive, value of constant used at multiple places in the program is
easily changed. One can change it once and the assembler will change all of its
occurrences

❖
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Addressing Modes-8051

❖ The various methods of accessing data are called addressing modes.

❖ The 8051 addressing modes can be classified into the following categories
❖ Immediate addressing
❖ Register addressing
❖ Direct addressing
❖ Indirect addressing * Show countequ.uvproj file*
❖ Absolute addressing
❖ Long addressing
❖ Indexed addressing
❖ Bit inherent addressing
❖ Relative addressing
❖ Bit direct addressing
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Immediate Addressing Mode

❖ In Immediate addressing an 8/16-bit data is provided as part of the instruction

❖ The source operand is a constant
❖ The immediate data must be preceded by the pound sign “#”
❖ Can load information into any registers, including 16-bit DPTR register
❖ DPTR can also be accessed as two 8-bit registers, the high byte DPH and the low byte DPL

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Immediate Addressing Mode

❖ We can use EQU directive to access immediate data

❖ We can also use immediate addressing mode to send data to 8051 ports

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Register Addressing Mode

❖ Register addressing mode involves the use of registers (R0 to R7) as the instruction operand
to hold the data to be manipulated in the instruction. The assembly language documentation
refers to a register generically as Rn.

❖ The source and destination registers must match in size

❖ The movement of data between Rn registers is not allowed

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Direct Addressing Mode

❖ Direct addressing mode is provided to allow us access to internal data memory and Special
Function Register (SFR) only.
❖ In this addressing mode, data is obtained directly from the memory.
❖ In direct addressing, an 8 bit internal data RAM memory address is specified as part of the
instruction, It can specify the address only in the range of 00H to 7FH (entire 128 bytes) of RAM
but most often used to access the RAM locations 30-7FH or address of SFR (80H to FFH).
❖ The register bank locations are accessed by register name.

❖ Contrast this with immediate addressing mode, there is no # sign in the operand

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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SFR Registers and Their Addresses

❖ The SFR (special function registers can be accessed by their names or by their addresses

❖ The SFR registers have addresses between 80H and FFH

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

8051/8052 SFR Addresses

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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8051/8052 SFR Addresses

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

SFR Registers and Their Addresses

❖ Write code to send 55H to ports P1 and P2, using (a) their names, (b) their addresses.

(a) MOV A,#55H ;A=55H

MOV P1,A ;P1=55H
MOV P2,A ;P2=55H

(b) From Table of SFR, P1 address = 90H; P2 address = A0H

MOV A,#55H ;A=55H
MOV 90H,A ;P1=55H
MOV 0A0H,A ;P2=55H

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Stack and Direct Addressing Mode

❖ Only direct addressing mode is allowed for pushing or popping the stack
❖ PUSH A is invalid
❖ Pushing the accumulator on to stack must be coded as PUSH 0E0H

❖ Show the code to push R5, R6, and A onto the stack and then pop them back
them into R2, R3, and B, where register B = register A, R2 = R6, and R3 = R5.

PUSH 05 ;push R5 onto stack

PUSH 06 ;push R6 onto stack
PUSH 0E0H ;push register A onto stack
POP 0F0H ;pop top of stack into register B
;now register B = register A
POP 02 ;pop top of stack into R2
;now R2 = R6
POP 03 ;pop top of stack into R3
;now R3 = R5
DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Register Indirect Addressing Mode

❖ The indirect addressing mode uses a register to hold the actual address of the data to be
moved. Registers R0, R1, and DPTR are the only registers that can be used as data pointers.
R2-R7 can not be used to hold the address of an operand located in RAM.
❖ When R0 and R1 hold the addresses of RAM locations (00h to 7FH), they must be preceded
by the “@” sign. Both internal and external RAM can be indirectly addressed.
❖ Indirect addressing cannot be used to refer to SFR registers.
❖ R0, R1 and SP can hold 8 bit address while only DPTR can hold 16 bit address.
❖ When accessing externally connected RAM or on-chip ROM, we need 16-bit pointers, here
we use DPTR register.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Example: Direct addressing mode

❖ Write a program to copy the value 55H into RAM memory locations 40H to 45H using
(a) direct addressing mode, (b) register indirect addressing mode without a loop, and
(c) with a loop.

(a) direct addressing mode

MOV A,#55H ;load A with value 55H
MOV 40H,A ;copy A to RAM location 40H
MOV 41H,A ;copy A to RAM location 41H
MOV 42H,A ;copy A to RAM location 42H
MOV 43H,A ;copy A to RAM location 43H
MOV 44H,A ;copy A to RAM location 44H

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Example: Register Indirect Addressing Mode

❖ Write a program to copy the value 55H into RAM memory locations 40H to 45H using
(a) direct addressing mode, (b) register indirect addressing mode without a loop, and
(c) with a loop.

(b) MOV A,#55H ;load A with value 55H

MOV R0,#40H ;load the pointer. R0=40H
MOV @R0,A ;copy A to RAM location R0 points to
INC R0 ;increment pointer. Now R0=41H
MOV @R0,A ;copy A to RAM location R0 points to
INC R0 ;increment pointer. Now R0=42H
MOV @R0,A ;copy A to RAM location R0 points to
INC R0 ;increment pointer. Now R0=43H
MOV @R0,A ;copy A to RAM location R0 points to
INC R0 ;increment pointer. Now R0=44H
MOV @R0,A

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Example: Register Indirect Addressing Mode With a Loop

❖ Write a program to copy the value 55H into RAM memory locations 40H to 45H using
(a) direct addressing mode, (b) register indirect addressing mode without a loop, and
(c) with a loop.

(c) with a loop

MOV A,#55 ;A=55H
MOV R0,#40H ;load pointer. R0=40H, RAM address
MOV R2,#05 ;load counter, R2=5
AGAIN: MOV @R0,A ;copy 55H to RAM location R0 points to
INC R0 ;increment R0 pointer
DJNZ R2,AGAIN ;loop until counter = zero

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Register Indirect Addressing Mode

❖ It makes accessing data dynamic rather than static as in direct addressing mode
❖ Looping is not possible in direct addressing mode

❖ Write a program to clear 16 RAM locations starting at RAM address 60H.

CLR A ;A=0
MOV R1,#60H ;load pointer. R1=60H
MOV R7,#16 ;load counter, R7=16 (10 in hex)
AGAIN: MOV @R1,A ;clear RAM location R1 points to
INC R1 ;increment R1 pointer
DJNZ R7,AGAIN ;loop until counter = zero

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Register Indirect Addressing Mode

❖ Write a program to copy a block of 10 bytes of data from RAM locations starting at 35H
to RAM locations starting at 60H.

MOV R0,#35H ;source pointer

MOV R1,#60H ;destination pointer
MOV R3,#10 ;counter
BACK: MOV A,@R0 ;get a byte from source
MOV @R1,A ;copy it to destination
INC R0 ;increment source pointer
INC R1 ;increment destination pointer
DJNZ R3,BACK ;keep doing it for all ten bytes

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Indexed Addressing Mode and On-chip ROM Access

❖ In indexed addressing, a separate register—either the program counter (PC), or the data
pointer (DTPR)—is used to hold the base address, and the A is used to hold the offset
address. Adding the value of the base address (pointer) to the value of the offset address in
A forms the effective address.
❖ Indexed addressing is used with JMP or MOVC instructions.
❖ This addressing mode is used in accessing data elements of look up tables located in the
program ROM only .
❖ The instruction used for this purpose is

❖ Use instruction MOVC where “C” means code/constant.

❖ The contents of A are added to the 16-bit register DPTR to form the 16-bit address of the
needed data.
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External Addressing Modes using MOVX and MOVC

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Indexed Addressing Mode and MOVX

❖ In many application, the size of program code does not leave any room to share the 64 kB
code space with data.
❖ The 8051 has another 64kB of memory space set aside exclusively for data storage. This
data memory space is referred to as external memory and it is accesses only by the
MOVX instruction.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

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Indexed Addressing Mode and MOVX

❖ Exchange the content of FFH and FF00h

❖ Here one is internal memory location and other is external memory location so first the content of
external memory location FF00H is loaded in accumulator then the content of internal memory
location FFH is saved first and then content of accumulator is transferred to FFH. now saved
content of FFH is loaded in accumulator and then it is transferred to FF00H.

MOV DPTR, #0FF00h ; take the address in DPTR

MOVX A, @DPTR ; get the content of 0050H in A

MOV R0, 0FFH ; save the content of 50H in R0

MOV 0FFH, A ; move a to 50H

MOV A,R0 ; get content of 50h in A

MOVX @DPTR,A ; move it to 0050H

RAM Locations 30 – 7FH as Scratch Pad

❖ We generally use R0-R7 of bank 0

❖ Leaves addresses 08-1FH for the stack usage
❖ If we need more registers, we simply use RAM locations 30-7FH as scratch pad.

❖ Write a program to toggle P1 a total of 200 times. Use RAM location 32H to hold
your counter value instead of registers R0 - R7.

MOV P1,#55H ;P1=55H

MOV 32H,#200 ;load counter value into RAM loc 32H
LOoP1: CPL P1 ;toggle P1
ACALL DELAY
DJNZ 32H,LOoP1 ;repeat 200 times
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Bit Addressable RAM

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Bit Addressable RAM

❖ Find out to which byte each of the following bits belongs.
❖ Give the address of the RAM byte in hex.
(a) SETB 42H ;set bit 42H to 1 (d) SETB 28H ;set bit 28H to 1
(b) CLR 67H ;clear bit 67 (e) CLR 12 ;clear bit 12 (decimal)
(c) CLR 0FH ;clear bit 0FH (f) SETB 05

(a) RAM bit address of 42H belongs to D2 of RAM location 28H.

(b) RAM bit address of 67H belongs to D7 of RAM location 2CH.
(c) RAM bit address of 0FH belongs to D7 of RAM location 21H.
(d) RAM bit address of 28H belongs to D0 of RAM location 25H.
(e) RAM bit address of 12 belongs to D4 of RAM location 21H.
(f) RAM bit address of 05 belongs to D5 of RAM location 20H.

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Bit Addressable RAM

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Figure: SFR RAM Address

Figure: 16 Bytes of Internal RAM.
(Byte and Bit)
Note: They are both bit- and byte-accessible.

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SFR: I/O Port Bit Addresses

❖ While all of the SFR registers are byte-addressable, some of them are also bit-addressable
(e.g. P0-P3) are bit addressable.
❖ We can access either the entire 8 bits or any single bit of I/O ports P0,P1,P2, and P3
without altering the rest.
❖ When accessing a port in a single-bit manner, we use the syntax SETB X.Y where X is the
port number P0,P1,P2 or P3. Y is the desired bit number from 0 to 7 for data bits D0 to D7.
❖ Example: SETB P1.5 sets bit 5 of port 1 high.
❖ When code such as SETB P1.5 is assembled, it becomes SETB 95H.

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Example

❖ For each of the following instructions, state to which port the bit belongs.
❖ (a) SETB 86H (b) CLR 87H (c) SETB 92H (d) SETB 0A7H

(a) SETB 86H is for SETB P0.6.

(b) CLR 87H is for CLR P0.7.
(c) SETB 92H is for SETB P1.2.
(d) SETB 0A7H is for SETB P2.7.

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Bits of the PSW Register

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Registers Bit Addressability

❖ Write a program to save the Accumulator in R7 of bank 2.
CLR PSW.3
SETB PSW.4
MOV R7,A

❖ JNC and JC are used to check the carry flag bit (CY), there are no instructions for the
overflow flag bit (OV). How would you write code to check OV?

❖ The OV flag is PSW.2 of the PSW register. PSW is a bit-addressable register; therefore,
we can use the following instruction to check the OV flag.
JB PSW.2,TARGET ;jump if OV=1

❖ Write a program to save the status of bit P1.7 on RAM address bit 05.
MOV C,P1.7 ;get bit from port
MOV 05,C ;save bit
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Main Difference between 8051 and 8052

DR. ASHOK KHERODIA, ECE DEPARTMENT, IIIT KOTA

Main Difference between 8051 and 8052

Figure: The 8051 Program Memory

Figure: The 8052 Program Memory

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Main Difference between 8051 and 8052

Figure: The 8051 Data Memory

Figure: The 8052 Data Memory

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Special Function Register 8051Vs. 8052

SFR Map. (... ) Indicates Resident in 8052s, not in 8051s

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