LX) 258) ° What is microprocessor? Itis a program controlled semi conductor device (IC). which fetches, deéodes and execute instructions. 2. What are the basic units of microprocessor? The basic nits or blocks of microprocessor ave ALU, an tela} af registers and control unit. & Whatis a bus? « Bus is a group of conducting \ines that carries data, address and control signals, A Why data bus is bi-directional? The microprocessor is to fetch (read) the data from memory or input device for processing and after processing it has to store (write) the data to memory or output devices. Hence the data bus is bi-directional. A Whydataburisbidireetional? Why Adchese bus is Unimelirectional F ‘The address is an identification aumber used by the microprocessor to idemtify or access a memory location or inpuvoutput device. Itis an ontput signal from the processor. Hence the address bus is unidirectional é * 6. Define machine cycle? Machine cycle is defined as the time required to complete one operation of accessing memory inpuvoutput, or acknowledging an external request. This cycle ‘may consists of three to six T-states. a7. Define T-state? T-state is defined as one subdivision of operation performed in one clock ‘eziodThese subdivisions are intemal states synchronized with the system clock, and ‘each T-state is precisely equal to one clock period. Lc Mavis am insrvsion cycle? ‘The sequence of operations that @ processor has to carry out while ‘executing the instruction is called instruction cycle. Each instruction cycle of Processor contains a number of machine cycles. 1. What is fetch and execute cycle? ‘The instruction cycle is divided in to feich and execute cycles. The fetch cycle is executed to fetch the opcode from memory. The exeente cycle is executed to ‘decode the instruction and to perform the work instructed by the instruction. 10. List the flags of 8085? ‘There are five flags in 8085.They are sign flag, zero flag, auxiliary camry flag, parity flag and carry flag. 11, What does memory-mapping mean? ‘The memory mapping is the process of interfacing memories to microprocessor and allocating addresses to each memory locations. 12, What is opcode fetch cycle? ‘The opcode fetch cycle is a machine cycle executed to fetch the opcode of an instruction stored in memory. Each instruction stants with opcode fetch machine cycle. 15. What are the instructions used to control the interrupts? EL « DI* RM * sim 14, What is polling? In polling, the microprocessor's software simply checks each of the YO devices every so often. During this check, the microprocessor tests to see if any device needs servicing. 15. What are the different types of interrupts? + Hardware © Software Hardware interrupts- The interrupts where the CPU pins are used to receive {interrupt requests , are called hardware interrupts.“ Software interrupts ~ This interrupt is caused by the execution of ‘the instriction. These are special instructions supported by the microprocessor. 16. What are the types of hardware interrupts? > TRAP _ + RST75 > RST6S + RSTS5 + INTR L 17. Difference between memory mapped Vo and VO mapped Wo? ‘Memory mapped VO WO mapped VO 5s 1. In this device address is 16-bit. Thus | I. In this device address is 8-bit. Thus Ao ‘Ao to AIS lines are used to generate the device address to A7 or AB to AIS lines a used to ‘generate device address.| 2. MEMR and MEMW conuol signals | 2. TOR and JOW control signals we wacd | are used to control read and write UO to control read and write 1/0 operations operations. 3: Instructions available are 3. Instructions available are IN and OUT. LDASTAMOV RM, ADD Metc 4. Data wansfer is between any register | 4. Data wansfer is between accummulaiar and VO device, and VO device. 3. Decoding 16-bit address may require | 5. Decoding 8-bit address will require more hardware. Jess hardware. 18. Describe the function of. tbe following pins in 8085? a)READY b) ALE c)IO/M d)HOLD e)SID and SOD READY ~ It is used by the microprocessor to sense whether a peripheral i ready oF ‘not for data transfer. If not, the processor waits. Its thus used to synchronize slower Bee nn Se ROS el ory ao) acide ae oc cal ALE In 8085, ADo to AD? lines are multiplexed and lower half of address (Ao to A7) is available only during T1 of the machine. ‘cycle. The latching of lower half address from the multiplexed address lines by using ALE signal. TOIRT - indicates whether /O operation or memory operation is being carried out. HOLD — This signal indicates that another master is requesting for the use of address bos, data bus and control bus. ‘S10 (Serial Inpat Data) - This input signal is used to accept serial data bit by bit from the external device. ‘SOD(Serial Ourput Data) ~ This is an output signal which enables the transmission of serial data bit by bit to the external device.Instruction No.ofmle | No. of Name of cycles cycles | T-states TMVIA eb [2 i ‘Opeode Fetch, Memory Read DstAadaess | 4 13 Opcode feich MR.MRMW FLxIrp dale [3 10 OFMRMR 3 Z Lab ee [5 16 OFMRMR.MW.MW SMViMdaw®) | 3 10 OFMRMW 7 CCMPree®) [7 4 OF i; 7. ADD reg(8) 1 4 OF B.CMA 1 4 OF 9. CMC 1 4 OF 10. ADD M z 7 ‘OF.MR 11.CMP M 2 7 ‘OF,MR TZ LDA address [4 13 OLMRMRMR 13. DAD sp s 10 OF, Bus Idie,Bus Idle ‘14.INRM - 10 OF.MR,MW ¥ 15. XTHL 5 16 OF,MR.MR,MW.MW 16. IMP address3 | 3 10 OF.MR.MR 17. J condition 2 7 OF,MR 78. PUSHip 3 10 OFMW.MW 19.POP ip 3 10 OF MRMR "20. CALL address | 5 18 ‘OF.MR.MR.MW,.MW 7 RET a 10 OFMRMR 7" 2.RST 3 12 OFMwMW 23. MOV 1.M. 2 ‘OF,MR 24. MOV Mr 2 Bs OF.MW W.INaddress [3 10 OFMRUORead 26. OUT address | 3 10 OF,.MR,V/O Write19. Comparison between full address decoding and partial address decoding? Full Address Decoding Partial Address decoding | T All higher address lines are decoded to select the memory or HO device. to select the memory or 1/0 device. T. Few higher address lines are decoded | 7 More hardware is required to design decoding logic. 7, Hardware required to design decoding logic is less and sometimes it can be eliminated. 3. Higher cost for decoding circuit. 3, Less cost for decoding circuit. 4, No Multiple addresses. @, Iehas a advantage of multiple addresses. ‘5. Used in large systems 5. Used in small systems 20. What is ALE? “The ALE (Address latch enable) is a signal used to demultiplex the ‘address and data lines using an external Jatch. It is used to enable the extemal laich. 21. Where is the READY signal used? READY is an input signal to the processor, used by the memory or inpuvoutput devices to get extra time for data transfer or to introduce wait states in the bus cycles. 22. Give some examples of port devices used in 8085 microprocessor based system? The various port devices used in 8085 are 8212,8155,8156,8255,8355.8755. 23. What is the need for timing diagram? ‘The timing cing vides informa mening smi of ris signals, when a machine cycle is executed. The knowledge of timing-diagram is essential for system designer to select matched peripheral devices like memories, latches, ports etc from a microprocessor system.24, What operation is performed during first T-state of every machine cycle in 8085? B ‘In 8085, during the first T-state of every machine cycle the low byte address is latched into an external latch using ALE signal. 25. What is interrupt acknowledge cycle? ‘The interrupt adknowledge cycle is a machine cycle executed by 8085 processor to get the address of the interrupt service routine in order to service the interrupt device. 26. What is vectored and non-vectored interrupt? When an interrupt is accepted, ifthe processor control branches toa specific address defined by the manufacturer then the interrupt is called vectored imternapt, In Non-vectored interrupt there is no specific address for storing the interrupt service routine. Hence the imterrupted device should give the address of the interrupt service routine 27. List the sofiware and hardware imerrupts of 80852 Software imesrupts : RST O,RST | RST 2.RST 3,RST 4,RST 5.RST 6,RST7 Hardware interrupts : TRAP,RST 7.5,RST 6.5,RST 5.5, INTR. 28. What is TRAP? ‘The TRAP is a non-maskable interrupt of 8085. It is not disabled by - rocessor reset or after recognition of interrupt. 29. How clock signals are generated in 8085 and what is the frequency of the internal clock? ¥ ‘The 8085 has the clock generation circuit on the chip bil an external ‘quartz crystal or LC cireuit or RC circuit should be connected at the pins X1 andX2. ‘The maximum internal clock frequency of 8085 is 3.03MHz, % 30. Define stack?ff Ranney oly dees Jy Ravenrer” Seyorte Stack is a sequence of RAM memory locations defined by the programmer. 31. What is program counter? How itis useful in program execution? ‘The program counter keeps tack of program enecation. To execute 2 program the stating address ofthe program is loaded in program counter. The PC sends out an address to fetch a byte of instruction from memory and increments its content automatically é 32. Define opcode and operand? | Opeode(operation code) is the part of an instruction that identifies a specific operation. Operand is a pan of instruction that represents a value on which the instruction acts. 33. How the 8085 processor differentiates a memory access and 1/O access? . ‘The memory access and /O access is differentiated using 1O/M signal. “The 8085 processor asserts IO/M low for memory operation and high for YO operations. 34. When the 8085 processor checks for an interrupt? In the second T-state of the last machine cycle of every instruction, the ‘8085 processor checks whether an interrupt request is made or not. 35. Why interfacing is needed for 70 devices? Generally UO devices are slow devices. Therefore the speed of LO devices does not match with the speed of microprocessor. And so anvinterface is . provided between system bus and I/O devices. 2 36. What is interrupt 70? Ifthe VO device initiate the data transfer through interrupt thn the YO is called imerupt driven VO.ia 37. What is a port? ‘The port is a buffered VO, which is used to hold the data transmitted from the microprocessor to VO. devices and vice versa, 38. What is the need for interrupt controller? The interrupt controller is employed to expand the interrupt inputs. it an handle the interrupt request from various devices and allow one by one tothe Processor. 39. What is synchronous data transfer scheme? 40. What is asynchronous data transfer scheme? In asynchronous dave transfer scheme, first the processor sends a Tapes tothe device for read/write operation. Ten he processor keeps on polling the Sams ofthe device. Ones the device is ready, tbe processor executes a data transfer instruction to complete the process. 41. What are the internal devices of 82559 ‘The imtema) devices of 8255 are port, por-B, por-C. The pons can be Programmed fo either input or ouput function in different operating modes, 42. What is USART? . ‘The device which can be programmed to perform Synchifhous or Asynchronous serial communication is called USART (Universal Synchronous Asynchronous Receiver Transmitter), Eg: INTEL 8251 43. What is scanning in keyboard and what is scan time?“The process of sending a zero to each row of a keyboard matrix and seading the columns for key actuation is called scanning. The scan time is the time taken by the processor to scan all the rows one by one starting from first row ang ‘coming back to the first row again. 44. What is programmable peripheral device? If the function performed by the peripheral device can be altered or changed by a program instruction then the peripheral device is called programmable device. Ithave control register. The device can be programmed by sending control ‘word in the prescribed format to the control register. 45, What is baud rate? ‘The baud rate is the rate at which the serial date-are transmitted. Baud rate is defined as (The time for a bit cell: In some systems one bit cell has one data bit, then the band rate and bits/sec are same. 46. What are the tasks involved in keyboard interface? ‘The tasks involved in keyboard interfacing are sensing a key actuation, ‘Debouncing the key and generating key codes( Decoding the key). These tasks are performed software ifthe keyboard is interfaced through ports and they are performed by hardware if the keyboard is interfaces through 8279. 47. How a keyboard matrix is formed in keyboard interface using 82797 “The retum lines, RLO toRLT of 8279 are used to form the columns of keyboard ‘matrix. In decoded scan lines SLO t0SL3 of 8279 are used to form the rows of + kevbosrd matrix. In encoded scan mode, the output lines of external dicoder are used as rows of keyboard matrix * 48, What is GPIB? GPIB is the General Purpose interface Bus. tis used to interface the test instruments to the system controller.2 49. Advamages of differential data wansfer? 4. Communication at high data rate in real ‘World environment. 2. Differential data ansmission offers superior performance 3. Differemtial signals can hetp induced noise signals. ‘50. Features of INTEL 82599 1. Itmanage 8 interrupt request. 2. “The imerrupt vector addresses are programmable. 3. The priorities of imterrupis are programmable. 4. The interrupt can be masked or unmasked individually. 51. What is meant by micro controller? & 8 5 g i F | 5 52. List the features of 8051 micro controllers? ‘Single supply +5v operation using HMOS technology. 4096 bytes program memory on-chip. 128 data memory on chip. © 4register banks 2 multiple modes, 16 bit imer/counter Extensive Boolean processing capabilities, * G4KB external RAM size. 32 bi-directional /O lines. | | Shift clock. 8-bits are wansmitted or received:8-data bi | fixed at 1/12 the oscillaor frequency.| ‘54. Explain the operating mode 2 of 8051 serial port? An this mode 11 bits are transmitted (through TXD) or received ahrowgh (RXD): a start bit(0), 8 data bits( LSB first), a programmable 9" data bit and 2 sop bit(1). (On transmit, the 9” data bit can be assigned the value 0 or 1. On receive, the 9" data bit go into the RBS in special function register SCON, while the stop bit is ignored. ‘The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. 55. Explain the mode 3 of 8051 serial port? In this mode, 11 bits are wansmitted (through TXD) or (received (through RXD): a stant bit(0), 8 data bits(LSB first), a programmable 9* data bit and a stop bit(1).It is same as mode 2 except the baud rate. The baud rate in mode 3 is variable. ‘56. Explain the intesrupts of 8051 micro controller? ‘+ External imterrupt 0 (IED) — Highest priority ‘© Timer interrupt 0 (TPO) ‘© Extemal interrupt 1 (151) © Timer interrupt 1 (TF1) * Serial port Interrupt Receive interrupt (RI) | - lowest priority ‘Transmit interrupt (TD) 517. How many bytes of internal RAM and ROM supported by 8051 micro controller? 128 bytes of internal RAM and 4 bytes of ROM. 58. Define machine cycle of 80512 i 8051 machine cycle consists of 6 states, Si through S7. One state is made up of 2 clock pulses. Thus 12 clock period constitute one machine cycle, Two clock periods in a state is termed as phase 1 and phase 2. 59. What are the special function of port 0 of 8051?Port 0 is used as a multiplexed low order address/data bus during the external memory access. When ALE is enabled, the address on port 0 pins are latched and bus is ready to act as a data bus when ALE is Jow. 60. What are the alternative function of port 3 of 8051? Serial data input (P3.0), serial data output (P3.1), external interrupt 0 (P3.2), external interrupt 1 (P33), external input for timer O(P3.4), extemal input for timer 1 (P3.5), external memory write pulse (P3.6), extemal memory read (P3.7) are the alternative functions of port 3. 61. What are the use of scratch pad area of internal RAM of 8051? In internal RAM 80 bytes constitutes the scratch pad area. The scratch pad bytes can be programmed as a general purpose registers. (62. What are the flags supported by 8051 controller? + Cary flag “+ Auxiliary carry flag / © Over flow flag © General purpose user flag © Register bank select bit one. © Register bank select bit zero ve Parity flag 63. What is meant by Power-on- Reset in 8051 controller? When RESET pin is activated, the 8051 juinps to address location 0000H. This is called as Power-on-Reset. Reset pin is considered as sixth iacegt | source of 8051. | i | 64. What are the significance of SFRs?‘SFRs denotes Special function Registers of 8051 controller. All the controller registers such as port latches, timer register, peripheral control register, accumulator, PC and DPTR all are available in SFR region. 65. What are the different group of instructions supported by 8051? Data Transfer Group Asithmetic Group Logical Group Branching Group ‘Bit manipulation Group 66. Write a program to mask the 0” and 7 bit using 8051? MOV A.tdata ANLAS8I MOV DPTR,#4500 MOVX @DPTR.A Loop: SIMPLOOP 67. List the addressing modes of 8051? Direct addressing Register addressing Register indirect addressing Implicit addressing Immediate addressing Index addressing a Bit addressing . 68. Write about CALL statement in 8051? ‘There are two CALL instructions. They are ‘5 © LCALL(Long call) ‘+ ACALL{Absolute call)(69. Write about the jump statement? There are three forms of jump. They are > LIMP (Long jump) ~ 16 bit address + AJMP(Absolute jump) ~ 11 bit address ‘= SIMP (Shor jump) — relative address 70. Write 2 program to find the 2's complement using 8051? MOV A.RO CPLA INCA 71. Write a program to swap two numbers using 8051? MOV A# data SWAPA 72. Write a program to subtract two numbers & exchange the digits using 80512 MOV A#9F MOV RO.#40 SUBB A.RO SWAP A ‘73. What are the different types of Address decoding Techniques? Absolute decoding/Full decoding, Linear decoding/Pantial decoding 74. Comparison between full address decoding and Partial address decoding?“ Pall address decoding Partial address decoding 1. All higher address Hines are decoded to | 1. Few higher address lines are decoded select the memory or VO device. to select the memory or /O device. 2 More hardware is required to design | 2. Hardware required to design'dccoding decoding logic. logic is less and sometimes it can beC eliminated. 3. Higher cost for decoding circuit. 3. Less cost for decoding circuit. 4. No maltiple addresses. Ithas a disadvantage of multiple addresses. (Shadow addresses) 3. Used in large systems. 5. Used in small systems. 75: What is the significance of wait state generator? “This is used to transfer data between slower VO device and the microprocessor. In some appins, the speed of W/O systems is not compatible with the microprocessor’s timings. So the microprocessor has to confirm whether the peripheral is ready or not. If READY pin is high, the peripheral is ready otherwise 8085 enters in to wait state. 16. What is a Non-maskable interrupt? It is unaffected by any mask or interrupt enable. Eg: TRAP 77. What is a Data pointer register? ‘The data pointer register (DPTR) consists of a high byte(DPH) and a low byte (DPL) functions to hold 16 bit address. it may be manipulated as a 16-bit data register or as independent 8-bit registers. It serves as a base register in indirect jumps, Jook up table instructions and external data transfer. 78. What are the operating modes of 8279? 1. Input modes : ‘© Scanned keyboard © Scanned sensor matrix © Strobed input > 2. Display modes ‘© Leftventry (Type writer mode) © Right entry (Calculator mode)79. What are the different functional units in 8279? (CPU interface section Keyboard section Display section ‘Scan section 80. What are the priority modes in 82597 Folly nested mode 9. Special fully nested mode Rotating Priority mode |. Special Masked mode . Polled mode 81. What is IMR(Interrupt mask register)? IMR stores the masking bits of the interrupt lines 1o be masked. This register can be programmed by an operation command word (OCW). 82. What is priority resolver? It determines the priorities of the bits set in the Interrupt request register (IRR}-Phe bit corresponding to the highest priority interrupt inpat is set in the ISR during INTA input. 83. What is the use of IRR? ‘The imerrupt sequest register is used to store all the imerrupt levels which are requesting the service. The eight interupt inputs sets corresponding bits of the Interrupt Request Register upon the service request. ‘ ‘84. What is Interrupt service register(ISR)? The interrupt service register stores all the levels that are currently being serviced, . Siren85. What is the difference between SHLD and LHLD? ‘SHLD- Store HL register pair in memory. ‘This instruction is used to store the contents of H and L register directly in to memory. LHLD- Load HL register pair from memory. ‘This instruction copies the contents of memory location given with in the instruction in to the L register and the contents of next memory location in to the H register. 86. What isthe difference between STAX and LDAX? ae, oP STAX rp—Store the contents of Accumulator register (A) in memory location whose address is specified by BC or DE register pair. ent LDAX rp — Load Accumplator register (A) with the contents of memory location ‘A whose address is specified by BC or DE register pair. Soe £87. Write an assembly language program to transfer data from memory block B1 to ‘memory block B2? ‘MVICOAH: Initialize counter << LXIH, 2200H5 Initialize source memory pointer ~~ LXID, 2300H; Initialize destination memosy pointer Loop: - MOV A.M; Get byte from source inemory blosk — STAX D; Store byte in the destination memory block INX H; Increment source memory pointer - ~~~ NX D; Increment destination memory poimer DCR C/Decrement counter ~ Ms INZ Loop ; If counter # 0 repeat HLT ’ ‘88. What are the types of branching instructions? 1. Jump instructions 2. Call and Return instructions3. Restart instructions 1 89. Write an assembly language program to add 2 BCD numbers? LXIH,2200H; Initialize poimer MOV AM ; Get the first nuniber INX H; Increment the pointer ADD M ; Add two numbers © DAA ; Convert HEX to valid BCD STA 2300: store the result HLT 90. Explain the instruction LXA sp,data (16)? LXLp, data(16) - Load 16 ~bit immediate data to specified register pair or stack pointer. The 1p is 16 — bit register pairs such as BC, DE, HL or stack pointer. 91. Write the difference between LDA and STA instruction? LDA — Lond data in to Accumulator register(A) directly from the address specified with in the instruction. STA- Store the contents of Accumulator register(A) to the address specified with in the instruction. 92. What are the types of rotate instructions? RLC- Rotate Accumnlator Left RRC- Rotate Accumulator Right RAL — Rotate Accumulator Left through Cay RAR - Rotate Accumulator Right through Carry ‘93. What are the operating modes of 8255? . 1. Bit set(Reset mode 2. VO modes a)mode 0 : Simple inpuvoutput . b)mode | : Inpuvourpor with handshakec)mode 2 : Bi-directional YO data transfer (94, What are the prierity modes in 82597 1. Polly nested mode 2. Special fully nested mode 3. Rotating priority mode 4. Special mask mode 5. Poll mode 95. What is the use of SWAP function in 80512 SWAP A : Swap nibbles with in the Accumulator bytes. It imerchanges the low and high order nibbles of the Accumulator (bits 0-3 and bits 4-7) ‘96. What is SCON? SCON is the serial port control register , which contains not only the mode selection bits (SMO — SM2 REN), but also the 9" data bit for wansmit and receive (TBS and RB8) and the seria} port interrupt bits (TI and RD. [SMO - Serial port mode control bit 0 SMI — Serial port mode control bit ! ‘SM2 ~ Serial port mode control bit 2 REN - Receiver enable control bit ‘TBS - Transmit bit 8 RBB — Receive bit 8 ‘TI= Transmit Imerrupt flag 3 RI- Receive interrupt flag = 97. How we calculate the Baud rate for serial port in mode 0? Baud Rate = Oscillator frequency/12 98. What is the significance of TXD and RXD pins in 8051?‘TXD — Transmit data pin for serial port in UART mode. Clock output in shift register mode, RXD-— Receive data pin for serial port in UART mode. Data HO pin in shift register mode. 99. Write two examples of Register indirect Addressing modes in 8051? MOV A,@RO ; Load the contents pointed by RO in A. ADD A,@RI_ ; Add the contents of A and the contents pointed by RI 100. What is Accumulator Register? I is an 8 — bit register. Itholds a source operand and receives the result of the arithmetic instructions (Addition, Subtraction, Multiplication and Division) ‘16; Marks Questions 1. With Neat diagram, explain the Architecture of 8085? | > Block diagram | > Explaination 2. Explain the instruction sets of 8085? Data transfer instructions Arithmetic instructions Logical instructions Branching instractions Machine contro! instructions : 3. Explain the interrupt structure of 8085? o TRAP o RSTTS o RST6S o RSTSS ¥> INTR 4, Draw the timing diagram of STA address? 4 machine cycles. > Opcode Fetch > Memory Read > Memory Read > Memory Write ‘5. Explain about Memory interfacing? = Explanation 6. Write the Assembly language program to sort a set of numbers in Ascending order? Program Output * 7, Write an Assembly language program to find the largest nunaber in an array? ‘> Program > Ourput 8 With neat block diagram, explain the Architecture of 8279? > Block diagram > Explanation 9. Write an Assembly language program to add two BCD numbers? career Output 10. With neat block diagram, explain the Architecture of PPI? > Block diagram > Explanation11. With neat block diagram, explain the Architecture of 82537 * Block diagram © Explanation 12. With neat block diagram, explain the Architecture of USART? > Block diagram > Explanation 13. Explain the operating modes of 8279? Input modes * Scanned keyboard * Scanned sensor matrix ‘© Swobed input Display modes Left entry (Type writer mode) * Right entry (Calculator mode) 14. Explain the operating modes of 8255? Bit scvReset mode VO modes a)mode 0 : Simple inpavoutput b)mode 1 : Inpuvoutput with handshake ‘©)mode 2 : Bi-directional VO data transfer 15. Explain the operating modes of PPI? - 16. Explain the operating modes of USART? a 17, Explain the operating modes of 82597 * Fully nested mode * Special fully nested mode ‘ ‘* Rotating priority mode© Special mask mode ‘+ Poll mode 5. Explain the Architecture of 8259? > Block diagram > Explanation 19. Explain the instruction sets of 8051? & Types Explanation 20. Explain the interrupt structure of 8051? + Types + Explanation 21. How 8279 is interfaced with 8085? > Dingram > Explanation 2. How stepper motor is interfaced with 8085? ‘ > Diagram > Explanation 23. Explain about Servo motor interfacing? 24. Explain the Addressing modes of 8051? © Direct addressing © Register addressing © Register indirect addressing ‘+ Implicit addressing © Immediate addressing ¢ Index addressing