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CS2340.005 Class Notes 103023

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12 views

CS2340.005 Class Notes 103023

Uploaded by

TryMyTutor com (Trymytutor)
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CS/SE 2340

The Processor

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The Processor
CS/SE 2340

Introduction

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The Processor
CS/SE 2340

Introduction
• CPU performance factors
 Instruction count
 Determined by ISA and compiler
 CPI and Cycle time
 Determined by CPU hardware
• We will examine two MIPS implementations
 A simplified version
 A more realistic pipelined version
• Simple subset, shows most aspects
 Memory reference: lw, sw
 Arithmetic/logical: add, sub, and, or, slt
 Control transfer: beq, j
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The Processor
CS/SE 2340

Instruction Execution

• PC → instruction memory, fetch instruction


• Register numbers → register file, read registers
• Depending on instruction class
 Use ALU to calculate
 Arithmetic result
 Memory address for load/store
 Branch target address
 Access data memory for load/store
 PC ← target address or PC + 4

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The Processor
CS/SE 2340

CPU Overview

An abstract view of the implementation of the MIPS subset showing the


major functional units and the major connections between them.
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The Processor
CS/SE 2340

Multiplexers

• Can’t just join wires together


 Use multiplexers in 3 places

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The Processor
CS/SE 2340

Control

The basic implementation


of the MIPS subset,
including the necessary
multiplexors and control
lines

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The Processor
CS/SE 2340

Logic Design Conventions

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The Processor
CS/SE 2340

Logic Design Basics


• Information encoded in binary
 Low voltage = 0, High voltage = 1
 One wire per bit
 Multi-bit data encoded on multi-wire buses
• Combinational element
 Operate on data
 Output is a function of input
 e.g., ALU, AND gate, etc.
• State (sequential) elements
 Has internal storage and contains state
 Has at least two inputs (data and clock) and one output
 e.g., instruction and data memories, registers, etc.
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The Processor
CS/SE 2340

Combinational Elements
• AND-gate • Adder
 Y=A&B  Y=A+B

• Multiplexer • Arithmetic/Logic Unit


 Y = S ? I1 : I0  Y = F(A, B)

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The Processor
CS/SE 2340

Sequential Elements
• Register: stores data in a circuit
 Uses a clock signal to determine when to update the stored value
 Edge-triggered: update when Clk changes from 0 to 1

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The Processor
CS/SE 2340

Sequential Elements
• Register with write control
 Only updates on clock edge when write control input is 1
 Used when stored value is required later

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The Processor
CS/SE 2340

Clocking Methodology
• Combinational logic transforms data during clock cycles
 Between clock edges
 Input from state elements, output to state element
 Longest delay determines clock period

Input/output state elements Read and write a state


surrounding a block of element (e.g., a register) in
combinational logic the same clock cycle
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The Processor

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