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Im Tech Ver I Log Introduction

This document provides an introduction to Verilog, including: 1. Keywords like module and endmodule are used to define modules in Verilog. Modules contain port declarations, variables, and a functional specification. 2. Verilog supports both behavioral and structural modeling. Behavioral describes what a module does, structural describes how it is built from simpler modules. 3. Verilog code is case sensitive and whitespace is ignored. Comments begin with // for single-line and /* */ for multi-line. This provides a concise high-level overview of some basic concepts in Verilog like modules, modeling styles, syntax, and comments.

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10 views

Im Tech Ver I Log Introduction

This document provides an introduction to Verilog, including: 1. Keywords like module and endmodule are used to define modules in Verilog. Modules contain port declarations, variables, and a functional specification. 2. Verilog supports both behavioral and structural modeling. Behavioral describes what a module does, structural describes how it is built from simpler modules. 3. Verilog code is case sensitive and whitespace is ignored. Comments begin with // for single-line and /* */ for multi-line. This provides a concise high-level overview of some basic concepts in Verilog like modules, modeling styles, syntax, and comments.

Uploaded by

ramkushal090
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to Verilog

A Peek Into Open Source Verilog Simulator -


Open Source For You (opensourceforu.com)
Top 4 HDL Simulators for Beginners |
HackerNoon
List of HDL simulators - Wikipedia
List of Verilog Simulators - Open-source
Simulators (liquisearch.com)

EDA Playground : Edit code - EDA Playground


References
[1] Verilog HDL- A Guide to Digital
Design and Synthesis
by Samir Palnitkar
[2] http://www.verilog.com/
[3] http://en.wikipedia.org/wiki/VHD
L
[4] http://iverilog.icarus.com/
Hardware Modules
module :
The Main
Keyword
Component
module
of Verilog

module module-name
List of ports; Variables, wires, and
Declarations module parameters
... are declared.
Functional specification of module
...
endmodule
Keyword
endmodule
Verilog Module

Two types of Modules:


− Behavioral: describe what a module does
− Structural: describe how it is built from simpler
modules
Behavioral Verilog
module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

• module/endmodule: required to begin/end module


• example: name of the module
• Operators:
~: NOT
&: AND
|: OR
Verilog syntax
• Case sensitive
– Example: reset and Reset are not the same signal.
• No names that start with numbers
– Example: 2mux is an invalid name
• Whitespace ignored
• Comments:
– // single line comment
– /* multiline
comment */
Bitwise Operators
module gates(input [3:0] a, b,
output [3:0] y1, y2, y3, y4,
y5);
/* Five different two-input logic
gates acting on 4 bit busses */
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
Reduction Operators
module and8(input [7:0] a,
output y);
assign y = &a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] &
// a[3] & a[2] & a[1] & a[0];
endmodule
Conditional assignment
module mux2(input [3:0] d0, d1,
input s,
output [3:0] y);
assign y = s ? d1 : d0;
endmodule

? : is also called a ternary operator because it


operates on 3 inputs: s, d1, and d0.
Internal variables
module fulladder(input a, b, cin,
output s, cout);
wire p, g; // internal nodes

assign p = a ^ b;
assign g = a & b;

assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule
Numbers
• Format: N'Bvalue
N = number of bits, B = base

Number # Bits Base Decimal Stored


Equivalent
3'b101 3 binary 5 101
'b11 unsized binary 3 00…0011
8'b11 8 binary 3 00000011
8'b1010_1011 8 binary 171 10101011
3'd6 3 decimal 6 110
6'o42 6 octal 34 100010
8'hAB 8 hexadecimal 171 10101011
42 Unsized decimal 42 00…0101010
Bit Manipulation
• '
assign y = {a[2:1], {3{b[0]}}, a[0], 6 b100_010};

• // if y is a 12-bit signal, the above statement


produces:
• y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0

• // underscores (_) are used for formatting only to make


it easier to read. Verilog ignores them.
Z: Floating output
module tristate(input [3:0] a,
input en,
output [3:0] y);
assign y = en ? a : 4'bz;
endmodule
Why HDL ?
• To conquer the complexity
• Text based rather than schematic based
• Tools to help in moving from one abstraction
level to other
HDL to GATES
• Simulation
– Inputs applied to circuit
– Outputs checked for correctness
– Millions of dollars saved by debugging in simulation instead of
hardware
• Synthesis
– Transforms HDL code into a netlist describing the hardware (i.e.,
a list of gates and the wires connecting them)

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