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Timing constraints can be very complex. Here we introduce basic timing path
constraints first, and we will introduce complex timing constraints later.

The main contents in this section are as follows:

·Introduction to timing path and critical path

·Brief description of setup time and hold time

Nickname: IC_learner
·Clock constraints (register-register path constraints) Age: 6 years and 9 months
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·Input delay constraints
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·Output delay constraints

·Constraints of combinational logic < November 2023 >

dayone two three Four five six
·Combined with design specifications for actual combat
29 30 31 1 2 3 4

The RTL code describes the sequential logic and combinational logic of the circuit. 5 6 7 8 9 10 11
12 13 14 15 16 17 18
That is, the RTL code reflects the register structure and number of the circuit, the topology twenty twenty t twenty t twenty
19 20 25
of the circuit , the combinational logic functions between registers, and the combinational one wo hree four
26 27 28 29 30 1 2
logic functions between registers and I/O ports. However, the code does not include the
3 4 5 6 7 8 9
circuit time (path delay) and circuit area (number of gates). Synthesis tools currently cannot
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support asynchronous circuits very well, or even do not support asynchronous circuits.
Therefore, the constraints on timing paths are mainly for synchronous circuits. The looking around
constraints on asynchronous circuits will be explained later.
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The characteristic of the path is that there is delay . That is to say, paths 1, 2, 3, and 4
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When constraining, first understand the three concepts of flip-flops: setup time, hold
ath constraints (14)
time, and metastability. Here is just a brief introduction . For an in-depth introduction to 3. Tcl and Design Compiler (3) - DC synthesis
setup time and hold time, please check my blog post: process (12)
4. Clocks and constraints in digital design(12)
http://www.cnblogs.com/IClearner/p/6443539.html . For an in-depth introduction to
5. (Digital IC) Introduction to Low-Power Desig
metastability, please Check out my blog post: n (1) - Low-Power Design Purpose and Types
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Setup time : Within a certain period of time before the arrival of the valid edge of the latest comment

clock, the data must be stable, otherwise the flip-flop cannot latch the data. This period of 1. Re: A blog link from a senior colleague
time becomes the setup time, represented by Tsetup or Tsu.
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Holding time : Within a certain period of time after the arrival of the valid edge of the Hello blogger, is this senior’s blog no longer
clock, the data must also be stable, otherwise the flip-flop cannot latch the data. This period updated? It shows that it cannot be opened.
Can you help me update the link?
of time becomes the holding time, represented by Thold or Th.
--Everything from yesterday has become who
As shown below: I am today
2. Re: Tcl and Design Compiler (2) - Overview
of DC synthesis and Tcl syntax structure

Hello, how to set up the syntax of checking tcl

using dcprocheck?

--Weaving
3. Re: Tcl and Design Compiler (9) - Formal
verification after synthesis

Can you publish the contents of this file

./scripts/fm.tcl? Otherwise, we only know a set
of commands, but we don’t know which
commands they are.

--AIcoder96
4. Re:Tcl and Design Compiler (6) - Basic
timing path constraints
At the rising edge of the second clock, the high level of the input terminal D needs to be
latched. D1 meets the setup time and hold time; while D2 does not meet the setup time, so The design (constraint) specification is as
follows:
the input cannot be latched successfully. The high level of D3 is not satisfied, and the high
(Definition of clock)
level of the input cannot be successfully latched. (Definition of register setup time)
(Definition of delay of input and output ports)
Metastable state : Each flip-flop has its specified setup and hold time parameters, ...
which are stored in the process library provided by the semiconductor manufacturer. If the How do you know these known conditions?

flip-flop is triggered by the rising edge of the clock, the input signal is not allowed to --AIcoder96
change within this time parameter. Otherwise, if the signal is sampled during its setup or 5. Re: Cross-clock domain signal transmission
(2) - Data signals
hold time, the result obtained is unpredictable and may be 0 or 1, which is a metastable
Hello poster, thank you for sharing. Your post
state. is very well written. Some of the circuit
structures are the first time I have seen them.
With these three concepts in mind, we can constrain the path. The constraint is to meet Thank you very much. I would like to ask
the setup time (and hold time) of the register. We first constrain the path within the module, where this picture in the article (that is, the first

which is the middle part of the circuit block diagram below: picture under the title "When the data rate (or
the frequency of the sending clock) is slightly
higher than the receiving clock end") comes
from...
--Beginner classmate

For the middle part of the path, the previous path diagram can be used to describe:

That is to say, these types of paths are mainly constrained. This section mainly talks about
the constraints of these paths.

②Constraints of path 2 ( path from register to register ) :

Let’s start with path 2 from register to register; as mentioned earlier, why we need to
constrain the timing path is to meet the setup time and hold time of the register . For path 2,
when data is transmitted from the D port of FF1 to the D port of FF2, it mainly needs to
experience delays such as flip-flop time/conversion delay, combinational logic delay
between registers, and wiring delay . Because data is transmitted back beat by beat with the
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beat of the clock, the path constraints between registers here are the modeling of the clock,
or the constraints on the clock. The following explains:

In order to meet the requirements of the FF2 setup time, that is, the time it takes for the
data to reach the D terminal of FF2 after passing through the above delays (flip-flop flip
time/conversion delay, combinational logic delay between registers and registers,
connection delay) In addition, the setup time of FF2 needs to be less than the clock cycle;
that is to say, your delays cannot be too large . Once the delay is too large, the data may
not meet the setup time relationship, and may not even be updated. For example :

After the current beat (the moment 0ns) arrives, the data (for example, a high level) is
transmitted from the D end of FF1. After the combination logic, it is transmitted to the D of
FF2 at the next beat (the moment 20ns). terminal, update the data of FF2 (at 0ns, FF2 saves
a low level), as shown by the red arrow; but because the delay is too large, the next beat
arrives (20ns arrives), and this high level is still there In the combinational logic, as shown
by the green arrow, the D-side data of FF2 cannot be updated, or the setup time is not met ,
which may cause a latch error. When the clock is modeled, the beat length is also
determined, that is, what is the maximum delay (the flip-flop time/conversion delay of the
flip-flop, the combinational logic delay between registers, and the connection delay) That is
to say, by modeling the clock, that is, by constraining the path between registers, DC will
know the maximum delay of the operation of this path, and will select appropriate units
to meet these delays. Constraints, if DC is selected over and over again, and it is found that
the circuit delay obtained by the most powerful unit is still very large, unable to meet the
establishment time requirements of FF2, DC will report an error. At this time, you need to
modify the design (such as modifying constraints or modifying the code).

In order to meet the holding time of FF2, that is, the time it takes for the data to reach
the D end of FF2 after passing through the above delays (flip-flop flip time/conversion
delay, combinational logic delay between registers, and connection delay), Cannot be less
than a certain value. In other words, these delays cannot be too small . To take an extreme
example, at 0ns, the valid edge of the flip-flop arrives, and both FF1 and FF2 update data.
FF1 is ready to latch the high level, and FF2 is ready to latch the low level; because FF1
responds quickly, the circuit The delay is very small. The high level registered by FF1 will
soon be transmitted to the D port of FF2, and the high level will wash out the low level to
be latched by FF2 (that is, the low level of the D port of FF2 has not yet been reached.
stable, violating the holding time), which means that the holding time of the low level for
FF2 cannot be satisfied, causing FF2 to fail to update the data, and the low level to be
latched may produce a metastable state. Therefore, the transmission delay needs to be
greater than the holding time of FF2 . In addition, we can also know from this that the
analysis of hold time is one clock cycle edge earlier than the analysis of setup time ,
that is to say, data is transmitted at 0ns, and the setup time is checked at the next rising edge
of the clock ( 20ns moment ). D of FF2 Whether the port data is stable (if it is unstable, it
violates the setup time), and the hold time is to check whether the D port data of FF2 is
stable at the same time when the data is sent (that is, the 0ns time ) (if it is unstable, it
violates the hold time) ); It should be noted that the analysis of hold time is one clock
cycle earlier than the analysis of setup time .

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However, the hold time can generally be met, that is, the transmission delay is
generally greater than the hold time of the flip-flop. Even if it cannot be met, modification
measures can be taken during the back-end layout design (such as adding a buffer to the
path to increase the delay). hour). Therefore, when we constrain, we generally do not pay
attention to the holding time, but to the establishment time .

After a lot of nonsense above, I believe everyone has a certain understanding of this
constraint process. Let’s summarize it and perform clock modeling.

Through the above explanation, we know that, in general, if the delay of the combined
circuit between the register and the register is greater than Clock_cycle-Tsu (Clock_cycle is
the clock cycle, Tsu is the establishment time of the flip-flop), the function of the circuit
will be incorrect and will not be able to normal work. If the clock operating frequency of
the circuit is known, the maximum delay of the combinational circuit between the register
and the register is known, as shown in the following figure:

The maximum delay of path X in the figure should satisfy the following relationship:

Tclk-Q is the delay from pin CLK to pin Q of FF2, and Tsetup is the setup time of
FF3. Both parameters are provided by the process library. After the summary is completed,
let's model the clock, that is, constrain the path from register to register. The modeling of
the clock is relatively complicated, so we will explain it step by step first, and finally give
the constraint script.

The command to define a clock is: create_clock . Assuming that the clock period is
10ns, the command to define the clock is:

create_clock -period 10 [get_ports clk]

For the clock waveform:

When defining a clock (except for virtual clocks, which will be discussed later), we
must define the clock cycle (that is, the -period option) and the clock source (port or pin)
(that is, clk in the design). You can also add There are some options to define the duty
cycle, offset/skew and clock name of the clock. We can view the relevant options of the
command through man create_clock.

Once the clock is defined, we have constraints on the paths between registers. We can
use the report_clock command to view the defined clock and its properties. If we need to
use both edges of the clock (rising and falling), the duty cycle of the clock will affect the
timing constraints.

However, simply defining a clock cycle to constrain the path between registers is
obviously too ideal. Other clock attributes need to be added. Before adding, you need to
know the skew, jitter, and conversion of the clock. For the concepts of time (transition) and

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delay (latency) or the properties of these clocks, please see my other blog post for these
properties:

http://www.cnblogs.com/IClearner/p/6440488.html

This blog post details the modeling of the clock, which is the constraints of path 2.

③Constraints on path 1 (input port to register D) :

What is discussed here is that the same clock CLK is used before and after the module
, as shown in the figure below. As for using different clocks (for example, the previous
module is ClkA instead of Clk, then the constraints are different) will be discussed later.

In the figure above, at the rising edge of the Clk clock, the data sent through the
register FF1 of the external circuit is transmitted to the circuit to be synthesized through the
input port A, and is received by the internal register FF2 at the rising edge of the next clock.
The timing relationship between them is shown in the figure below:

For the module we want to synthesize, the combinational logic of DC integrated input, that
is, the circuit N above , the delay to obtain it is Tn , but does this Tn meet the
requirements (for example, meet the establishment time of the flip-flop)? Before
constraining, DC does not know, so by constraining this path, we tell DC what the external
delay (including register flip delay and combinational logic and line network transmission
delay) is, for example Tclk-q+Tm , after constraining the clock, DC will calculate the delay
left for circuit N on this path, which is Tclk-q+Tm . Then DC compares Tclk -(Tclk-q+Tm)
with Tn+Tsetup to see whether Tclk -(Tclk-q+Tm) is larger than Tn+Tsetup, that is, the
comprehensive delay Tn of circuit N is It is not too large. If Tn is too large, greater than
Tclk -(Tclk-q+Tm), then DC will be optimized to reduce delay. If the delay is still too large,
DC will report an error. Therefore, we need to constrain the input port and tell the delay of
the external circuit so that the DC constrains the input combinational logic.

If we know the delay of the external circuit of the input port (assumed to be 4 ns,
including flip delay and external logic delay), we can easily calculate the maximum
allowable delay left from the input of the integrated circuit to register N:

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In DC, use the get_input_delay command to constrain the delay of the input path:

set_input_delay -max 4 -clock CLK [get_ports A]

We specify how much time is used by the external logic and how much time is left for the
DC calculation to be left for the internal logic. In this command, the external logic takes 4
ns. For a circuit with a clock period of 10 ns, the maximum delay of the internal logic is
10 - 4 - Tsetup = 6.

For example, for the following circuit:

The input port delay constraints are as follows:

create_clock -period 20 [get-ports Clk]

set_input_delay -max 7.4 -clock Clk [get-ports A]

The corresponding timing relationship diagram is as follows:

If the setup time of flip-flop U1 is 1ns, the maximum delay allowed by N logic is:

20 - 7.4 - 1 = 11.6 ns

In other words: If the maximum logic allowed by N logic is 11.6ns, then the maximum
delay that can be obtained for the external input is 20-11.6-1=7.4ns.

The above is the case without considering uncertain factors. When considering
uncertain factors, there are:

When there is jitter and offset (assuming the uncertainty time is U), if the setup
time of flip-flop U1 is 1ns and the external input delay is D (including the delay of the
previous-stage register flip and combinational logic), then N logic The maximum
allowed delay S is:

20-DU-1=S, the delay of external input can also be obtained : 20-U-1-S=D

When the input combinational logic has multiple input ports, as shown in the figure below:

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Then you can use the following command to set constraints on all input ports except the
clock:

set_input_delay 3.5 -clock Clk -max [remove_from_collection [all_ inputs ]

[get_ports Clk] ]

remove_from_collection [all_inputs] [get_ports Clk]”; #The command indicates

to remove the clock Clk from all input ports.

If you want to remove multiple clocks, use the following command:

Remove_from_collection [all_inputs] [get_ports "Clk1 Clk2"]

④Constraints on path 3 (register to output port) :

After understanding the constraints of path 1, the constraints of path 3 become easy to
understand. The circuit diagram of path 3 and the external output circuit is as follows:

The rising edge of the clk clock sends data through the register FF2 of the internal
circuit, passes through the circuit S to be synthesized, reaches the output port B, and is
received by the FF2 arriving at the external register on the rising edge of the next clock.
The timing relationship between them is shown in the figure below. We need to constrain
the delay of the combined path circuit S. If we want DC to calculate whether its delay can
meet the timing relationship, we need to tell the DC what the approximate delay of the
external output is. :

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When we know the delay of the external circuit (assumed to be 5.4 ns), we can easily
calculate the maximum delay left for the output port of the circuit to be synthesized, as
shown in the following figure:

In DC, use the set_output_delay command to constrain the delay of the output path. For the
above circuit diagram, there are:

set_output_delay -max 5. 4 -clock Clk [get_ports B]

We specify how much time the external logic takes, and DC will calculate how much time
is left for the internal logic. For example, for the following circuit model:

The timing path constraints from the register to the output port are:

create_clock -period 20 [get_ports Clk]

set_output_delay -max 7.0 -clock Clk [get_ports B]

The corresponding timing relationship diagram is as follows:

If Tclk-q of U3 = 1. 0ns, the maximum delay allowed by S logic is:

20 - 7.0 - 1=12 ns, that is to say, if the final delay from S logic is greater than 12ns, then
this timing path will violate the rules and DC will report an error.

The above does not consider jitter and offset. The internal delay is S (including clk-q
and combinational logic delay), the external output delay is X (including the establishment
time of external combinational logic and subsequent registers), and the clock cycle is T,
then we have:

TS=X, knowing the maximum internal delay S, you can calculate the maximum
allowable external output delay X

When considering uncertainty factors such as jitter offset and other factors, assuming that
the uncertainty time is Y, then there is:

TYS=X, so the external output delay X can be obtained directly, or X can be

calculated indirectly through the internal delay time S (and uncertainty time Y) .

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Here are some actual facts about input path delay and output path delay. When
designing SOC, because the circuit is relatively large, the design needs to be divided. In a
design team, each designer is responsible for one or several modules. Designers often do
not know the external input delay and/or external output establishment requirements of
each module (these requirements may or may not be written in the design specifications,
and when not, the designer does not know), as shown below Shown:

At this time, we can set timing constraints for the input/output ports by establishing a
time budget (Time Budget), that is, preset these delays and discuss them first (or declare
them in the design specifications). But how many presets are appropriate? Here are the
basic principles:

DC要求我们对所有的时间路径作约束，而不应该在综合时还留有未加约束的路
径。我们可以假设输人和输出的内部电路仅仅用了时钟周期的40%。如果设计中所
有的模块都按这种假定设置对输人/输出进行约束，将还有20%时钟周期的时间作为
富余量( Margin)，富余量中包括寄存器FF1的延迟和FF2的建立时间，即:富余量=20%
时钟周期 - Tclk-q - Tsetup,如下图所示：

举个例子说，对于前面的电路，就要按照这么一个比例进行设置：

对应的约束为：

create_clock -period 10 [get-ports CLK]

set_input_delay -max 6 -clock CLK [all_inputs]

remove_input_delay [get ports CLK] ;#时钟不需要输入延迟的约束

set_output_delay -max 6 -clock CLK [all-outputs]

如果设计中的模块以寄存器的输出进行划分，时间预算将变得较简单，如下图所
示：

时间预算的约束为：

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create_clock -period 10 [get-ports CLK]

set_input_delay -max $Tclk-q -clock CLK [all_inputs]

remove_input_delay [get ports CLK] ;#时钟不需要输入延迟的约束

set_output_delay -max [expr 10-$Tclk-q] -clock CLK [all-outputs]

⑤路径4的约束

路径4是组合逻辑的路径，组合逻辑的约束可能需要虚拟时钟的概念。组合逻辑
可能有两种中情况，一种是前面电路中的路径4：

模块里面有输入端口到输出端口的组合逻辑外，也有时序逻辑，也就是模块里面有
时钟，那么就可以对于路径4，就下面的电路模型进行约束：

组合逻辑部分F的延时Tf就等于时钟周期T-Tinput_delay-Toutput_delay,时钟周期减去
两端，就得到了中间的延时约束了，对于上面的模型，可以这样约束为：

set_input_delay 0.4 -clock CLK -add_delay [get_ports B]

set_output_delay 0.2 -clock CLK -add_delay [get_ports D]

set_max_delay $CLK_PERIOD -from [get_ports B] -to [get_ports D]

当然，最后一句的约束可有可无。对于多时钟的同步约束，只需要修改相应的延时
和时钟就可以了，可以参考前面的多时钟同步时序约束那里。

当考虑有不确定因素时，假设F的延时是F，外部输入延时为E（clk-q+组合逻辑
延时），外部输出延时为G(组合逻辑延时+后级寄存器建立时间)，不确定时间为U，
时间周期为T，则有（最大频率下）：

T - F -E-U = G

另外一种是纯的组合逻辑，模块内部没有时钟：

这种时钟需要用到虚拟时钟的概念，后面介绍有虚拟时钟的约束时，再进行说明。

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3、实战
首先设计的模块如下所示：

设计（约束）规格书如下所示：

（时钟的定义）

（寄存器建立时间定义）

（输入输出端口的延时定义）

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（组合逻辑的定义）

上面的规格定义用来给我们进行时序约束使用，现在实践开始。

·创建.synopsys_dc.setup文件，设置好DC的启动环境

-->common_setup.tcl文件：

由于这里有物理库，因此可以使用DC的拓扑模式进行启动。

-->dc_setup.tcl文件：

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-->.synopsys_dc.setup文件：

-------------------------------------这一步时间不够下可以忽略------------------

·启动DC，查看target_library的信息

-->启动的时候，我们使用管道开关，把DC的启动信息保存到start_report.log里面
（dc_shell -topo是DC的启动命令，启动时产生的信息，通过 | tee -i 流入
start_report.log文件中）：

（我们也可以通过启动gui界面进行输入命令，也可以在shell中输入命令）

-->由于我们仅仅是需要查看target_library库的信息，因此我们只需要读入库：
read_db sc_max.db

-->然后我们查看与这个库相关联的工艺库：list_libs,结果为：

我们可以看到，sc_max.db是target_library的的文件名称，而target_library的库名字是
cb13fs120_tsmc_max

-->接着我们查看库信息：

这里我们使用重定向的命令，将报告的结果保存到哦lib.rpt这个文件中。redirect是重
定向的命令，-file是将命令产生信息保存到文件中，lib.rpt是要保存信息到文件，后
面的{}中存放的是要执行的命令。

然后在终端读取相应库的单位信息，时序单位为ns，电容单位为pf

------------------------------------------------------------------------------------------------

·创建约束

在完成启动文件的书写之后，我就需要根据设计规格书，进行书写约束了

-->时钟的约束（寄存器和寄存器之间的路径约束）：

1.时钟频率为333.33MHz，因此时钟周期就是3ns：

create_clock -period 3.0 [get_ports clk]

2.时钟源到时钟端口的（最大）延时即source latency是0.7ns

set_clock_latency -source -max 0.7 [get_clocks clk]

3.时钟端口到寄存器的时钟端口延时即network latency为0.3ns有0.03ns的时钟偏
移：

set_clock_latency -max 0.3 [get_clocks clk]

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4.时钟周期有0.04ns的抖动

5.需要为时钟周期留0.05ns的建立时间余量

这里我们就要设置不确定因素了，由于设计规格声明是对建立时间留余
量，因此我们主要考虑建立时间的不确定因素：

首先是时钟偏移为±30ps,则有可能是前级时钟往后移30ps，同时本级时钟往
前移30ps，对于建立时间偏移的不确定因素为30+30 =60ps；

然后是时钟抖动，前级的时钟抖动影响不到本级，因此只需要考虑本级的
时钟抖动，由于是考虑建立时间，因此考虑本级时钟往前抖40ps，即对于建立时间
抖动的不确定因素为40ps；

最后是要留50ps的建立时间不确定余量；

So for the settling time, the total uncertainty time is 60+40+50=150ps=0.15ns:

set_clock_uncertainty -setup 0.15 [get_clocks clk]

6. Clock conversion time is 0.12ns:

set_clock_transition 0.12 [get_clocks clk]

-->Input delay constraints (constraints on input paths):

1. It is stipulated that the maximum logic S delay of the data1 and data2 ports in the
module is 2.2ns. It does not directly tell the delay of the external logic, so we need to
calculate:

The maximum external delay is: clock period - clock uncertainty - delay of S - register
setup time = 3.0 - 0.15 - 2.2 - 0.2 = 0.45ns, so there is:

set_input_delay -max 0.45 -clock clk [get_ports data*]

2. For the sel port, since it is clearly and directly stated that the latest (maximum)
absolute delay from the external data sending end (referring to F3's clk) to the sel port is
1.4ns, that is to say, this absolute delay includes The latency delay of the clock is included,
but input_delay is not included. input_delay is the front-end logic delay relative to the
clock, which does not include the latency of the clock. Then you need to subtract the
latency of the clock (including source and network):

1.4ns-(700ps + 300ps) = 0.4ns, then there is:

set_input_delay -max 0.4 -clock clk [get_ports sel]

-->Output delay constraints (constraints on output paths):

1. It directly tells that the maximum delay of the external combinational logic in out1
is 0.42ns, and the establishment time of the subsequent stage flip-flop is 0.08ns, that is, the
external delay is 0.42+0.08=0.5ns:

set_output_delay -max 0.5 -clock clk [get_ports out1]

2. The internal delay is 810ns. Apply the previous formula: clock cycle - internal delay
(flip and internal combinational logic delay) - uncertainty time = external delay (external
combinational logic + setup time of the subsequent register), so There is: 3-0.81-
0.15=2.04ns, so there is:

set_output_delay -max 2.04 -clock clk [get_ports out2]

3. It means that the external delay only requires the establishment time of the
subsequent register:

set_output_delay -max 0.4 -clock clk [get_ports out3]

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-->Constraints of combinational logic:

According to the previous formula, we can get:

3-0.15-input delay-2.45=output delay, so you can get:

Input delay + output delay = 0.4ns

Since the design specifications do not stipulate this ratio, as long as the relationship
between input and output delays is satisfied and the above formula is satisfied, if there are
violations after synthesis, we can make appropriate adjustments later and set it to:

set_input_delay -max 0.3 -clock clk [get_ports Cin*]

set_output_delay -max 0.1 -clock clk [get_ports Cout]

-->Check syntax:

·Start DC

(·Check before reading in the design)

·Loading designs (and viewing designs)

It’s the same process here. Mainly read, current_design, link, check_design, which will not
be demonstrated in detail here.

·Apply constraints and view constraints

-->Directly execute source scripts/MY_DESIGN.con to apply constraints

-->Check whether there are any missing or conflicting key constraints:

check_timing, the return value is 1, indicating successful execution.

-->Verify that the clock is constrained correctly:

report_clock

report_clock-skew

report_port-verbose

-->Save the constrained design:

write -format ddc -hier -out unmapped/MY_DESIGN.ddc

·comprehensive

(Simple steps are the same as the process)

·Post-synthesis inspection (and optimization)

(Simple steps are the same as the process)

·Save the synthesized design

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(Simple steps are the same as the process)

Don’t forget your original intention: The original purpose of writing a blog is to record things that you easily forget, rather
than writing specifically for others to read like writing a book. Therefore, except for blog posts that are prohibited from
reprinting, other blog posts can be reprinted. Try your best to do better!

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ps: You can reprint, please indicate the source: http://www.cnblogs.com/IClearner/ other blog posts can be reprinted.

I recently completed synopsys ' DC workshop , which involves clock modeling /

constraints. Let's talk about clocks (and modeling) in digital. The main content is as
follows:

·Synchronous circuits and asynchronous circuits;

·Attributes of clock / clock tree: skew (skew) and clock jitter ( jitter ), delay (
latency ), and transition ( transition ) time;

·Internal clock;
Nickname: IC_learner
·Multiplexed clock; Age: 6 years and 9 months
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·Gated clock; Followers: 10
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·Traveling wave clock;

·Double-edge clock; < November 2023 >

dayone two three Four five six
· Clock constraints in Design Compiler . 29 30 31 1 2 3 4
5 6 7 8 9 10 11
·Supplement: Clock distribution strategy 12 13 14 15 16 17 18
twenty twenty t twenty t twenty
1. Synchronous circuit and asynchronous circuit 19 20 25
one wo hree four
26 27 28 29 30 1 2
First, let’s talk about synchronous circuits and asynchronous circuits. So first
3 4 5 6 7 8 9
we need to know what is a synchronous circuit and what is an asynchronous
search
circuit?

For synchronous sequential circuits, different articles have different looking around

opinions, and the definition method is roughly as follows: Most used link

① For a more strict definition: a circuit is a synchronous circuit and needs to meet my essay
the following conditions: my comment
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·Each circuit element is a register or a combinational circuit; latest comment
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Under the strict definition above, it can be concluded that the following circuit
Comprehensive (11)
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The following form is definitely a synchronous circuit: Verilog Topics(10)

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1. Tcl and Design Compiler (3) - DC synthesis

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CLKA , CLKC , CLKD , and CLKE are all divided by the 300M clock source, so this system is a - Control signals (47619)
4. Tcl and Design Compiler (8) - DC logic synth
synchronous circuit system. esis and optimization (42964)
5. (Digital IC) Introduction to low-power design
·When they do not come from the same clock source, as long as the periods of (1) - Low-power design goals and types of pow
CLOCK have a multiple relationship and the phase relationship between them is fixed, it can er consumption (35764)

be regarded as a synchronous circuit. For example, three clocks of 10ns, 5ns, and 2.5ns are Comment ranking
used in the circuit . This The three clocks are not divided by the same clock source, but the
1. Three analysis modes of static timing analys
periods of these three clocks have a multiple relationship and a fixed phase relationship: is (brief description) (16)
10ns is twice as long as 5ns , twice as long as 2.5ns , and the relationship between them is 2. Cross-clock domain signal transmission (1)
- Control signals (16)
an integer multiple; The phase relationship is fixed, so it is also considered a synchronous 3. Autumn recruitment is over(14)
circuit. 4. (Digital IC) Introduction to low-power design
(1) - Low-power design purpose and types of p
There is no multiple relationship between CLOCKs or the phase relationship ower consumption (14)
between them is not fixed. For example, two CLOCKs of 5ns and 3ns are used in the circuit . 5. Tcl and Design Compiler (6) - Basic timing p
ath constraints (12)
These two clocks do not come from the same clock source. There is no periodic
relationship between them, so they are asynchronous. circuit. Recommended rankings

1. Cross-clock domain signal transmission (1)

Regarding the question of whether to synchronize the clock, the specific situation
- Control signals (17)
needs to be analyzed in detail. The issue of synchronizing the clock will also be involved in 2. Tcl and Design Compiler (6) - Basic timing p
the later clock failure domain, so I will not elaborate further here to avoid more ath constraints (14)
3. Tcl and Design Compiler (3) - DC synthesis
troublesome explanations.
process (12)

In addition, some information shows that synchronous circuits are circuits composed 4. Clocks and constraints in digital design(12)
5. (Digital IC) Introduction to Low-Power Desig
of sequential circuits ( registers and various flip-flops ) and combinational logic circuits. n (1) - Low-Power Design Purpose and Types
The characteristic of the synchronous sequential logic circuit is that the clock terminals of of Power Consumption (11)

each flip-flop are all connected together and connected to the system clock terminal. The latest comment
state of the circuit can only change when the clock pulse arrives. The changed state will be
1. Re: A blog link from a senior colleague

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21/11/2023, 14:03 Clocks and constraints in digital design - IC_learner - Blog Park

maintained until the arrival of the next clock pulse. At this time, regardless of whether the Hello blogger, is this senior’s blog no longer
external input x changes or not, each state in the state table is stable. updated? It shows that it cannot be opened.
Can you help me update the link?

--Everything from yesterday has become who

2. Properties of clock / clock tree I am today
2. Re: Tcl and Design Compiler (2) - Overview
Generally speaking, we refer to the global clock, and the global clock is embodied of DC synthesis and Tcl syntax structure

in the chip as a clock tree. Hello, how to set up the syntax of checking tcl
using dcprocheck?
A clock tree is a clock mesh structure balanced by many buffer cells , as shown in
the figure below: --Weaving
3. Re: Tcl and Design Compiler (9) - Formal
verification after synthesis

Can you publish the contents of this file

./scripts/fm.tcl? Otherwise, we only know a set
of commands, but we don’t know which
commands they are.

--AIcoder96
4. Re:Tcl and Design Compiler (6) - Basic
timing path constraints

The design (constraint) specification is as

follows:
(Definition of clock)
(Definition of register setup time)
(Definition of delay of input and output ports)
First of all, I have to say that in addition to the period/frequency, phase, edge, and
...
level attributes, the actual clock also has other attributes, that is, it is not as regular How do you know these known conditions?
as the following: --AIcoder96
5. Re: Cross-clock domain signal transmission
(2) - Data signals
Hello poster, thank you for sharing. Your post
is very well written. Some of the circuit
structures are the first time I have seen them.
Thank you very much. I would like to ask
why? That's because the clock has the following properties ( "actual buff "): where this picture in the article (that is, the first
picture under the title "When the data rate (or
① Clock offset ( skew ) : When the clock branch signal reaches the clock port of the frequency of the sending clock) is slightly
higher than the receiving clock end") comes
the register, there is a delay such as wired network. Due to the delay, the clock
from...
signal arriving at the clock port of the register has a phase difference, which means --Beginner classmate
that it cannot be guaranteed that every One edge is aligned, and this difference is
called clock skew, also called clock skew. The offset of the clock is shown below:

In addition, the clock skew is not directly related to the clock frequency . The skew is
related to the length of the clock line and the load capacitance and number of the
sequential units driven by the clock line .

②Clock jitter ( jitter ) : Compared with the ideal clock edge, the actual clock has an offset
that does not accumulate over time, sometimes leads and sometimes lags, which is called
clock jitter , or jitter for short, as shown in the following figure:

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Clock jitter can be divided into random jitter ( Rj for short ) and inherent jitter (
Deterministic jitter ):

·The sources of random jitter are thermal noise, Shot Noise and Flick Noise ,
which are related to the electron and hole characteristics of electronic devices and
semiconductor devices . For example, the PLL of the ECL process has smaller random jitter
than the PLL of the TTL and CMOS processes ;

·The sources of fixed jitter are: switching power supply noise, crosstalk,
electromagnetic interference, etc., which are related to the design of the circuit
and can be improved by optimizing the design, such as selecting an appropriate power
supply filtering solution, reasonable PCB layout and wiring.

In other words: jitter has no direct relationship with clock frequency .

Clock offset and clock jitter both affect the delay difference ( phase difference ) of the
clock network branches . In Design Compiler , we use clock uncertainty to
represent the impact of these two situations.

③Clock transition time ( transition ) : The time when the rising edge of the clock
jumps to the falling edge or the falling edge of the clock jumps to the rising edge.
This time is not as shown in the figure below left without a clock jump at all, but like
As shown in the picture on the lower right, the transition time of the clock edge is
the conversion time of the clock (there will be relevant explanations later in the
constraint).

Ideal: clock with transition

time:

The switching time of the clock is related to the delay time of the unit (that is,
the device characteristics) and the capacitive load .

④Clock delay ( latency ) : The delay of the clock from the clock source (such as
crystal oscillator) to the flip-flop clock port , called the clock delay, including clock
source delay ( source latency ) and clock network delay ( network latency ) , as
shown in the figure below:

Clock source latency , also known as insertion delay , is the transmission time of the clock
signal from its actual clock origin to the clock definition point in the design (the input pin
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of the clock). The figure above is 3ns .

The clock network latency is the delay ( latency) caused by the transmission of the clock
signal from its defined point ( port or pin ) to the register clock pin through the buffer and
connection . The figure above is 1ns .

OK , that’s almost it for the additional buff properties of the clock.

3. Internal clock

I remember when I was just learning FPGA , in the verilog code, I often used the internally
generated clock, that is, using an internal signal to act as the clock edge sensitivity list of
another always block , as shown in the following figure :

In fact, it is not recommended to use this kind of internal clock. One reason is that the
logic that generates the internal clock is delayed, resulting in a delay in the generation of
A_clk . There will be a delay between Data and A_clk , and there will be a metastable
voltage regulator. ; The other problem is the driving ability of A_clk generated by the
trigger .

4. Multiplexed clock

In a system, it is very likely that multiple clocks will be used to drive some flip-flops
in turn. In order to adapt to different data rate requirements, clock switching is
performed. Sometimes in order to save power consumption, the high-speed clock
will be switched to a low-speed clock, or the clock sleep operation will be
performed. The multi-channel clock is shown in the figure below:

Such a clock will generally cause some problems, such as insufficient setup
time for the registers driven later when switching clocks. When certain conditions
are met, the clock of this multiplexer can also be used, and the requirements must
be met. have:

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·Once the clock multiplexing circuit is powered on and working, do not

change the multiplexing logic to avoid uncertain errors after the change.

·When testing, design the circuit to bypass the clock multi-channel logic
and select a common clock, that is, use a common clock for testing.

·When the clock is switched, the register must be in a reset state to avoid
insufficient establishment time after the switch and entering a metastable state.

·During clock switching, some transient errors may occur, but these errors
have no impact on the entire system.

For systems with very strict requirements, such as frequent clock switching,
whether it can be switched during reset, and short-term errors are not allowed,
then the clock cannot be switched like this, and other clock switching solutions
must be used or Clock synchronization is performed. As for the multi-clock
switching solution, I will learn and supplement it when I have time in the future.

5. Gated clock

Gated clocks are the darling of low-power designs. There is a lot of information
about gated clocks. Let’s write about gated clocks.

The gated clock means that when the enable signal is valid, the clock is turned on;
when the enable signal is invalid, the clock is turned off. After the clock is turned
off, the registers it drives are not active anyway, thus reducing dynamic power
consumption.

The initial circuit of the gated clock is:

There are many bugs in this kind of gated clock . Let’s first take a look at the bug
waveform of this circuit, that is, we will know the problem so that we can improve it:

As can be seen from the waveform diagram, if the gate enable signal is turned
on or off when the clock is high, the generated high level of the gate clock will be
cut off and become a glitch; the gate enable signal is Transitions while the clock is
low have no effect on the resulting gated clock. Therefore, our target point is the
flip at high level.

Therefore, we can set up a circuit so that the gate enable signal only flips when the
clock is low after passing through this logic circuit, but cannot flip or remain when
the clock is high. So we think of a low-level triggered latch. After the enable signal
passes through the low-level latch, if the enable signal jumps at a high level, the
output signal of the latch will not change. The circuit diagram is shown below:

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The waveform looks like this:

What needs to be noted here is:

When the gate control enable signal is active at a high level, that is, the high
level turns on the gate control clock and the low level turns off the gate control
clock, then the above circuit is used, that is: a low level triggered latch + AND gate.

When the gate enable signal is active at a low level, it must be replaced with: a
high-level triggered latch + OR gate.

PS : When it comes to glitches, especially glitches due to enable signals and clocks, latches
play a big role.

Generally speaking, when designing chips, we do not need to design the gated clock
ourselves. Most ASIC/SoC manufacturers have corresponding gated clock units.

6. Traveling wave clock

Traveling wave clock, that is, the output of one flip-flop is used as the clock input of
another flip-flop. It is often used in the design of asynchronous counters and
frequency division circuits, as shown in the following figure:

Although the principle of the asynchronous counter / frequency-divided clock is simple and
convenient to design, the cascaded clock ( traveling wave clock ) is most likely to cause
clock deviation. If there are too many stages, it is likely to affect the setup time and hold
time of the flip-flop it controls, so that The design becomes more difficult; the conversion
method is to use a synchronous counter.

7. Double edge clock

A dual-edge clock system refers to data transmission on both the rising and falling
edges of the clock:

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Obviously, the data transmission rate is doubled in this way. DDR is a technology that uses
double edges to transmit data. The transmission diagram is as follows:

However, in general, we do not recommend using dual-edge clocks because:

·Since both the upper and lower edges are used, the clock quality is
required to be very high, which is difficult to achieve with ordinary clock sources
and the cost is high.

·Due to the existence of uncertain factors such as clock jitter, the duty
cycle of the clock may easily change, thus easily causing violations of the setup
time and hold time.

·When a double-edge clock is used, clock constraints become

complicated. In addition, when a violation occurs somewhere, the path to the
violation is more difficult to find than a single-edge clock.

·Another point is that the test is more difficult. The test circuit of the
double-edge circuit must be different from the test circuit of the single-edge circuit.
When performing a scan test, both the upper and lower edge clocks must be
inserted into the multiplexer for selection.

8. Clock constraints in Design Compiler

The actual clock is modeled / constrained, which actually means setting these attributes.
The following explains how to constrain in Design Compiler .

By default, during logic synthesis, even if one clock drives many registers , DC
will not add a clock buffer to the clock connection to enhance the driving capability.
The clock input terminal is directly connected to all registers. The clock pin, that is
to say, for the clock connection with high fanout , DC will not check and optimize the
design rules, as shown in the left figure below. Adding a clock buffer to the clock
connection or clock tree synthesis is generally completed by a back-end tool. The back-end
tool performs clock tree synthesis based on the physical layout data of the entire design.
comprehensive. After adding the clock buffer, the entire clock tree can meet the skew,
latency and transition goals. The circuit after clock tree synthesis is shown in the figure
below on the right.

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The clock network in the upper left figure is ideal, and its delay (latency) , clock skew
(skew) , and transition time (transition) have default values ​of zero. Obviously, the ideal
clock network is different from the actual situation, and using the ideal clock network will
produce overly optimistic timing results. In order to describe the clock tree more accurately
during synthesis, we need to model the actual clock tree so that the results of logic
synthesis can match the results of the layout .

Well, the above is not the point, the following is the content:

We use the following commands to establish the clock attribute model:

create_clolk , set_clock_uncertainty , set_clock_latency , and

set_clock_transition respectively perform clock cycle, offset, delay, and conversion
constraints:

Modeling clock skew:

set_clock_uncertainty : Model the offset and jitter of the clock, that is, model the
deviation of the clock. The specific usage is:

Assume that the clock period is 10ns and the clock settling deviation is 0.5ns . Use the
following command to define the constraints :

create_clock -period 10 [ get_ports CL K ]

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set_ clock_ uncerta inty - setup 0. 5 [ get _ clocks CLK ]

Ideal clock:

Model only skewed clocks with setup times:

If the deviation is modeled for both setup and hold times, we have:

By default, if the "set-clock_uncertainty " command does not add the switch option " -
setup " or " -hold", then the command will assign the same setup and hold offset values ​to
the clock.

This is a way to model the deviation, that is, the setup time and hold time. In addition, the
deviation can also be modeled on the rising and falling edges of the clock, such as the
deviation on the rising edge. is 0.2ns, and the deviation of the falling edge is 0.5ns , then
there is:

set_ clock_ uncerta inty -rise 0. 2 -fall 0.5 [ get _ clocks CLK ]

Generally, we only constrain the setup time, that is, we only use the first method to
model clock deviation.

After modeling the setup time deviation, the relationship between clock cycle, clock
deviation and setup time is as shown in the figure below:

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Assume that the clock cycle is 10ns , the setup time deviation is 0.5ns , and the flip-
flop setup time is 0.2ns . At this time, you can see from the figure that the margin left for
the path between registers is reduced, that is, for The constraints between registers become
more stringent. The sum of register flip delays, combinational logic delays and line network
delays must be less than 9.3ns, otherwise the establishment time of FF2 will be violated .
This is something to note.

As for the hold time, before considering the clock offset, as mentioned earlier,
the delay of the combinational logic is greater than the hold time of the flip-flop (for
specific reasons, please refer to the previous description). After modeling the clock
offset, at this time, the clock cycle , the timing relationship between clock deviation
and hold time is as follows:

Modeling of clock transition times:

Since the clock is not an ideal square wave, set_clock_transition is used to simulate
the transition time of the clock. The default rising transition time is the time from 20% to
80% of the voltage, and the falling transition time is the time from 80% to 20% of the
voltage. If the switch option " -setup " or " -hold" is not added to the set_clock_transition
command , then the command gives the clock the same rising and falling transition times.
Normally, we only constrain the maximum conversion time. For example, if the maximum
conversion time is 0.2ns , then add the -max option:

set_clock_transition -max 0.2 [get_clocks CLK]

Modeling of clock delays :

The delay of the clock from the clock source (such as crystal oscillator) to the flip-flop
clock port is called the clock delay, including clock source delay ( source latency ) and
clock network delay ( network latency ) . We use set_clock_latency to model clock delay.
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Under normal circumstances, we separate the clock source delay ( source latency ) and the
clock network delay ( network latency ) because the clock source delay needs to be
modeled because DC really does not know how big the delay is, but for DC does not know
the delay of the clock network before placement and routing, but it can calculate the delay
of the clock network after placement and routing. Therefore, when synthesis is performed
after placement and routing, there is no need to delay the clock network, so it is These two
delays must be constrained separately.

Let’s talk about layout and wiring first: the clock cycle is 10ns, the time from the clock
source to the chip’s clock port is 3ns, and the time for the clock port to have an internal
flip-flop is 1ns, as shown in the figure below.

Then use the following command to model:

create_clock -period 10 [get-ports CLK]

set_clock_latency -source 3 [get_clocks CLK]

set_clock_latency 1 [get_clocks CLK]

Normally, we constrain the maximum delay, that is, add the -max option to indicate the
maximum delay (such as set_clock_latency -source -max 3 [get_clocks CLK]
means that the maximum time from the clock source to the chip clock port is 3ns ).

After layout and routing: you can calculate the actual line network delay, you need
to use

set_propagated_clock [get_clocks CLK] This command replaces the above

set_clock_latency 1 [get_clocks CLK] this command.

The basic clock modeling is OK . Let’s summarize and give the constraint script used in
our example, and the comparison between the ideal clock and the actual clock, as shown in
the figure below:

So the summary is that the modeling / constraints on a real clock look like this:

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Supplement 1: Clock distribution strategy

The frequency division of the clock should be considered from the beginning of
planning, that is, from the system level, rather than waiting until the back-end design.
Clock distribution strategy considerations include:

System clock distribution plan (mainly clock tree scheme, clock frequency of each
module, etc.);

The minimum delay of the clock (mainly defining the minimum delay requirement
based on the speed of system operation, this should overlap with the clock distribution
plan, I don’t know the details);

Clock buffering (this is a load consideration issue and is often an issue that
should be considered when designing a clock tree);

Eliminate clock skew (clock skew always exists, how to minimize it or achieve the
desired effect must also be considered);

Consideration of power-saving modes such as gated clocks and software and

hardware co-design (this requires detailed analysis of specific issues, and can also be
observed from the perspective of low-power design).

P.S.:

References for this article include:

Design Compiler 1, synopsys workshop

Practical tutorial on ASIC design, Yu Xiqing

Digital design and computer architecture, (U.S.) David MoneyHarris

et al.

The art of Hardware Architecture by Mohit Aroa

Fundamentals of IC Design, Xi'an University of Electronic Science

and Technology Press

Some pictures come from the above references and the Internet

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reprinting, other blog posts can be reprinted. Try your best to do better!

Category: Digital IC (front-end)/logic design skills

Tags: clock , digital design , digital IC design , synopsys , Design Compiler , clock constraints

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error in the article; thank you.

Recently, I have sorted out some knowledge about cross-clock domain design. On the
one hand, this is related to metastability. I will continue what I mentioned earlier and on the
other hand, it will be a review. The main content mainly revolves around cross-clock
domain. Overview of the main content:

·Cross clock domain and metastability

·Control signal transmission across synchronized clocks Nickname: IC_learner

Age: 6 years and 9 months
·Clocks from the same source, non-integer multiples of cycles across clock
Fans: 1690
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·Control signal transmission across asynchronous clock domains
< November 2023 >
dayone two three Four five six
1. Cross-clock domain and metastability 29 30 31 1 2 3 4
5 6 7 8 9 10 11
In layman's terms, across clock domains, there is data interaction between modules, 12 13 14 15 16 17 18
but the modules are not driven by the same clock, as shown in the following figure: twenty twenty t twenty t twenty
19 20 25
one wo hree four
26 27 28 29 30 1 2
3 4 5 6 7 8 9

search

looking around

Most used link

my essay
my comment
Module 1 on the left is driven by clk1 and belongs to the clock domain of clk1; my participation
latest comment
module 2 on the right is driven by clk2 and belongs to the clock domain of clk2. When clk1
My Tags
has a higher frequency than clk2, module 1 (relative to module 2) is called the fast clock
My Tags
domain, and module 2 is called the slow clock domain. Depending on whether clk1 and
Design Compiler (13)
clk2 are synchronous clocks, the above cross-clock domains can be divided into cross- Digital IC Design (12)
synchronous clock domains (clk1 and clk2 are synchronous clocks) and cross-asynchronous tcl (12)
clock domains (clk1 and clk2 are not synchronous clocks). Depending on whether the DC (12)
Comprehensive (11)
signal is a control signal or a data signal, it can be divided into control signal transmission Digital Backend (9)
and data signal transmission across clock domains. verilog topic (9)
Digital IC (8)
During signal transmission across clock domains, metastable conditions may occur. At Low power design (8)
this time, a synchronizer is required to synchronize to reduce the probability of metastable Common circuit modules (7)
More
propagation; note that the synchronizer here can only reduce the probability of metastable
propagation. The probability of propagation, if a metastable state occurs, the level after the Essay classification

metastable state stabilizes may not be the correct level. If the level after stabilization is FPGA design related (EDA tools, knowledge)
wrong, it is likely to cause errors in the subsequent logic. This It needs to be emphasized; of (6)
Linux system and related EDA environment(8)
Tcl and Design Compiler (15)

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course, under normal circumstances (I am talking about general circumstances here) Verilog Topics(10)
Some commonly used modules (12)
metastable states rarely occur, otherwise wouldn’t the logic behind it be broken? Static Timing Analysis and Primetime(2)
Memories, feelings, realizations and hopes in
According to the above content, it can be seen that synchronizers may be needed
life (12)
across clock domains to suppress the probability of downward propagation of metastable Digital IC (front-end)/logic design skills(15)
states. Different synchronizers are required depending on the situation. The general Digital IC front-end (simulation) verification (2)
Digital IC design back-end learning record (9)
situation is as follows:
Digital IC design basics(9)
Image Processing: From Getting Started to

Across synchronized clock domains Fast clock domain to slow clock do control s Giving Up (Manual Funny) (3)
Reprints and other blog posts (1)
main
Essay Archives

Across asynchronous clock domains Slow clock domain to fast clock do data sign September 2020(1)
main June 2020(4)
November 2019(1)
October 2019(2)
August 2019(4)
· Control signal transmission from fast clock domain to slow June 2019(1)
clock domain across synchronous clock domains ; March 2019(4)
December 2018(1)
· Control signal transmission from slow clock domain to November 2018(2)
block clock domain across synchronous clock domains ; May 2018(1)
April 2018(3)
· Transmission of data signals from fast clock domain to slow March 2018(1)

clock domain across synchronous clock domains; August 2017(8)

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· Transmission of data signals from slow clock domain to June 2017(2)
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block clock domain across synchronous clock domains ;
Reading rankings
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clock domain across asynchronous clock domains ; 1. Tcl and Design Compiler (3) - DC synthesis
process (55476)
· Control signal transmission from slow clock domain to 2. Clocks and constraints in digital design (503
84)
block clock domain across asynchronous clock domains ;
3. Cross-clock domain signal transmission (1)
· Transmission of data signals from fast clock domain to slow - Control signals (47619)
4. Tcl and Design Compiler (8) - DC logic synth
clock domain across asynchronous clock domains ;
esis and optimization (42964)
5. (Digital IC) Introduction to low-power design
· Transmission of data signals from slow clock domain to
(1) - Low-power design goals and types of pow
block clock domain across asynchronous clock domains ; er consumption (35764)

Looking at these eight major types, I feel guilty, but here is a spoiler first. In the Comment ranking
transmission of data (mainly the transmission of multi-bit data), whether it is cross-
1. Three analysis modes of static timing analys
synchronous or cross-asynchronous, the main (note the main) is the use of comparison is (brief description) (16)
Large synchronous isolators isolate and buffer data, such as FIFO and RAM; therefore, 2. Cross-clock domain signal transmission (1)
- Control signals (16)
synchronizers are generally designed in two situations: control signals (usually 1-bit
3. Autumn recruitment is over(14)
signals) and data . We will talk about data transmission across clock domains last. Today 4. (Digital IC) Introduction to low-power design
we mainly sort out the control signal transmission across clock domains. (1) - Low-power design purpose and types of p
ower consumption (14)
I talked about the difference between synchronous circuits and asynchronous circuits in a 5. Tcl and Design Compiler (6) - Basic timing p
ath constraints (12)
previous blog: http://www.cnblogs.com/IClearner/p/6440488.html . Here we have to adapt
to the situation and update the concept of traditional synchronous clocks: multiple clocks in Recommended rankings
the system, if the relative time difference between their edges is fixed (or the phase is 1. Cross-clock domain signal transmission (1)
fixed), then they are synchronous clocks. They can be generated by different clock sources, - Control signals (17)
but the phase between them is fixed through a phase-locked loop, so they are synchronous 2. Tcl and Design Compiler (6) - Basic timing p
ath constraints (14)
clocks. They may be generated by the same clock source, but after frequency division, the 3. Tcl and Design Compiler (3) - DC synthesis
phase between them changes with the initial phase and time. This type of clock can be process (12)

called a synchronous clock, but starting from this traditional concept, this is an 4. Clocks and constraints in digital design(12)
5. (Digital IC) Introduction to Low-Power Desig
asynchronous clock ( This is different from my blog above, please note), it is processed as n (1) - Low-Power Design Purpose and Types
an asynchronous clock. Okay, having said that much, let’s talk about it according to the of Power Consumption (11)

classification of clocks. latest comment

1. Re: A blog link from a senior colleague

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21/11/2023, 14:02 Cross-clock domain signal transmission (1) - Control signal - IC_learner - Blog Park

2. Control signal transmission across synchronous clocks Hello blogger, is this senior’s blog no longer
updated? It shows that it cannot be opened.
(1) Two synchronous clocks with the same frequency and phase :
Can you help me update the link?

The waveform looks like this: --Everything from yesterday has become who
I am today
2. Re: Tcl and Design Compiler (2) - Overview
of DC synthesis and Tcl syntax structure

Hello, how to set up the syntax of checking tcl

using dcprocheck?

--Weaving
3. Re: Tcl and Design Compiler (9) - Formal
verification after synthesis
These two clocks can be regarded as the same clock, that is, a single clock design, Can you publish the contents of this file
which allows one clock cycle to transmit data. Therefore, as long as it meets the ordinary ./scripts/fm.tcl? Otherwise, we only know a set
of commands, but we don’t know which
synchronous circuit design requirements (meeting the setup time and hold time, control
commands they are.
signal transmission The delay must be within a certain range), there will be no
--AIcoder96
metastability, and there will be no data loss. Generally, a synchronizer is not needed.
4. Re:Tcl and Design Compiler (6) - Basic
timing path constraints

The design (constraint) specification is as

(2) Two synchronous clocks with the same frequency and different phases
follows:
The waveform looks like this: (Definition of clock)
(Definition of register setup time)
(Definition of delay of input and output ports)
...
How do you know these known conditions?

--AIcoder96
5. Re: Cross-clock domain signal transmission
(2) - Data signals
Hello poster, thank you for sharing. Your post
is very well written. Some of the circuit
structures are the first time I have seen them.
This fixed phase can be regarded as a clock offset, and the allowed transmission time Thank you very much. I would like to ask
is less than one clock cycle, but as long as the output of the control signal is flipped under where this picture in the article (that is, the first

the control of clk1, so as long as it meets the general requirements of synchronous design picture under the title "When the data rate (or
the frequency of the sending clock) is slightly
(meeting the establishment time and hold time, the transmission delay of the control signal higher than the receiving clock end") comes
must be within a certain range), the timing can be met, metastable state will not occur, and from...
--Beginner classmate
data loss will not occur, so a synchronizer is generally not needed.

(3) Different frequencies, but there is a relationship between integer multiples

Assuming there is no initial phase difference (or even if there is an initial phase difference
that is fixed, it can be fixed later), the clock frequency of clk1 is 3 times that of clk2.

·When crossing from the fast clock domain to the slow clock domain (that is, the
control signal is transmitted from the module of clk1 to the module of clk2), the waveform
is as follows:

If clk1 sends a signal on the second rising edge, as long as the control signal arrives
within 3 cycles of clk1, there will be no metastable state;... If clk1 sends a signal on the
fourth rising edge, it is necessary When the control signal arrives within one cycle of clk1,
metastability will not occur. Therefore, as long as the time for the control signal to arrive at
the destination clock domain from the sending clock domain is less than the clock cycle of
clk1, there is no need for a synchronizer; in general, the control signal is triggered by a flip-
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flop and captured by a flip-flop, which generally satisfies this relationship, as shown below
:

However, it should be noted that this is from fast to slow. The slow clock domain may not
be able to sample the control signal and lose the control signal. In other words, my control
signal runs from clk1 to clk2 and remains for one clock (clk1) cycle. , but the clock edge of
your clk2 has not come yet. When the rising edge of clk2 comes, my control signal has
been updated (or invalidated). The above signal is taken just before clk1 sends a signal in
the clock cycle before the rising edge of clock clk2. , if it is not sent at that time, the control
signal will be lost, as shown below:

When the signal is sent on the second clock edge, it only lasts for one clock cycle, so
clk2 cannot capture it (this is a functional error, not just a metastable state in timing); only
on the fourth clock When the control signal is sent along the edge, clk2 can capture it.
Therefore, we need to delay the period of this control signal to 3 times the clk1 period. This
can be achieved through a counter or state machine. The extended waveform is as follows:

It can be seen that no matter when data is sent at this time, clk2 can capture it.

Therefore, under normal circumstances, a synchronizer is not needed, but the control
signal of the fast clock domain needs to be extended for an appropriate time (determined
according to the multiple relationship between clocks. The length of the control signal must
be ≥ the period of the capture clock, generally 1.5 times , the above figure is only 1x) to
avoid signal loss in the slow clock domain.
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·When the slow clock goes to the fast clock domain (that is, the control signal is
transmitted from the module of clk2 to the module of clk1), the waveform is as follows:

Obviously, the fast clock can sample the control signal of the slow clock, and it samples it
three times, and the output is:

The control signal of Clock2 reaches 3 times of the clk2 period. If only one clk period of
control signal is needed, it can be achieved through the rising edge detection circuit. The
output waveform is as follows:

3. The clocks have the same source, and the cycles span non-integer multiples of clock
domains.

When both clocks come from the same clock, after PLL division, two clocks are
generated. One clock is a non-integer multiple of the other clock, and the phase changes
with time. In this case, we can treat these two clocks as synchronous clocks or as
asynchronous clocks ; in traditional designs, such clocks will be treated as asynchronous
clocks . Let's take a look at whether a synchronizer should be added for such clock
processing.

If the clock frequency of the clock source is clk, after passing through the PLL, a clock
clk1 and a clock clk2 are generated:

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Assume that clk1 is the fast clock and clk2 is the slow clock. Since the control signal
is only transmitted between the flip-flops of the two clock domains, there is no logic
between the flip-flops, so the time for the control signal from the sending flip-flop to the
capturing flip-flop is very small, assuming t ps, when the sending edge is If the distance
between capture edges is greater than tps, metastable state will not occur (theoretical
situation does not consider factors such as clock offset, flipping, etc.). When the frequency
of clk1 is not an integer multiple of clk2, their phases change with time. After knowing the
frequencies of clk1 and clk2, you can know the theoretical phase relationship between clk1
and clk2, then it will There are the following situations:

(In fact, it is also divided into cases of whether to add a synchronizer or not)

(1) (Whether it is fast to slow or slow to fast across clock domains) there is a
minimum phase difference between the two clocks, and the minimum phase difference is
greater than t. As follows:

In this case here, the minimum phase difference of the clock is T>t, that is, the control
signal will not violate the setup time and time of the capture register. It should be noted that
this is a control signal transmission from the fast clock to the slow clock domain. To
prevent signal loss, the control signal needs to be extended to a certain length.

The waveform from slow clock to clock is not drawn, but it mainly conforms to the fact
that there is a minimum phase difference between the two clocks (whether fast to slow
or slow to fast), and the minimum phase difference is greater than t, so the setup time
and hold time will not be violated. , basically no metastable state will occur. Therefore in
this case, a synchronizer is not needed.

(2) (Whether it is fast to slow or slow to fast across clock domains) Among the two
clocks, the phase from the sending edge to the receiving edge is very narrow, less than t,
which means that the setup time and hold time of the capture register are violated, but the
next time The phase from the sending edge to the receiving edge is very large (without
violating the setup time and hold time of the capture register), as shown below:

Where the phase is small, the establishment time is insufficient, causing metastability. At
this time, we need to use our synchronizer. Here we solemnly introduce our synchronizer-
double D flip-flop. Its circuit diagram is as follows:

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It should be noted that there cannot be any combinational logic in the middle. The circuit
diagram and the timing relationship are as follows (the code will not be written, the circuit
is simple):

Once again, the double D flip-flop (flip-flop chain) can only suppress the downward
transmission of the metastable state (or reduce the probability of its downward
transmission), and may not be able to synchronize the correct value of the control signal.
This is different from the metastable state. It is related to the value after stabilization. In the
above figure, the metastable value of the first-level flip-flop happens to be high level, so the
output value of the second-level flip-flop after sampling is high level. If the metastable
value of the first-level flip-flop in the figure above is low level, then the output value of the
second-level flip-flop after sampling will be low level, that is, an incorrect control signal is
output.

Let me reiterate here, in this case (that is, when there is metastability), from slow to fast,
there is only a problem of metastable state; and from fast to slow transmission, not only
must the metastable state be suppressed downward There are propagation problems and the
problem of control signal loss. Here you need to extend the length of the control signal or
take other measures (discussed later).

(3) The phase difference between the adjacent sending and receiving edges of the two
clocks is very small, as shown in the figure below:

This situation can be said to be basically the transmission of control signals between
asynchronous clock domains. In this case, a trigger chain synchronizer must be added to
suppress the downward propagation of metastability. As in the previous situation, from
slow to fast, there is only the problem of metastable state; while from fast transmission to
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slow, there is not only the problem of suppressing the downward propagation of metastable
state, but also the problem of loss of control signal. Here we need to extend Control the
length of the signal or take other measures (will be discussed later).

4. Control signal transmission across asynchronous clock domains

In fact, the waveform across asynchronous clock domains is similar to the previous 3.
(3), except that the clocks of the two clock domains are completely unrelated clocks. In this
case, we can adopt a similar method to the previous one: first, the flip-flop chain must
suppress metastable transmission, and then there is the problem of fast clock to slow clock,
that is, the problem of sampling short pulse control signals. In addition to extending the
control signal, we can also use other methods. Let’s sort it out below:

(1) Handshake/Feedback Mechanism

Using a handshake feedback mechanism can suppress metastable transmission and

correctly transmit control signals. This handshake/feedback mechanism is useful for all
control signals across asynchronous clocks, but is mainly used in situations where fast to
slow clocks are prone to metastability. Having said so much, none of it is concrete. Let’s
take a look at something concrete - handshake/feedback mechanism circuit diagram:

The waveform is as follows (hand drawn....):

其实原理很简单，当控制信号变高时（adat与adat1），慢时钟域的触发器链（bdat1
和bdat2）进行采样，采样得到的高电平(bdat2)后，也就是确认采样得到控制信号
后，再通过触发器链反馈给快时钟域(abdat1和abdat2)，让快时钟域把控制信号拉低
（拉低的或者处理时长在后面有电路），就完成控制信号的正确跨时钟传输。本来
不想写代码了的，毕竟有电路了，但是想想还是贴一下代码吧，毕竟最近整理过程
中都没有写代码了，感觉有点生疏了，代码如下（如果有错请指出）：

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当然，在慢时钟域阶段，我们也可以添加边沿检测（上升沿）电路，一方面让输
出只有一个脉冲的控制信号，另一方面准确地进行控制，以防止亚稳态的干扰。

在上面的握手方案中，我们通过反馈信号进行控制信号的延时来让慢时钟域充分采
样得到控制信号，本质上是也是对控制信号的延时。这个延时的具体实现，需要对
控制信号的产生逻辑进行处理，来满足延时的要求，如下所示：

除了上面对控制信号处理之外，我们还可以对快时钟域的时钟动点手脚，具体电路
如下所示：

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这里通过让快时钟域触发器（特指rd_en触发器）的时钟停止工作的方式，让控
制信号保持一定的时间。时钟停止之后，rd_en触发器的输出就会保持不变，等到反
馈信号回来，告知慢时钟域采样得到高电平后，再恢复快时钟域的时钟，波形如下
所示：

时钟停止的逻辑电路（类门控电路）的代码如下所示（代码如果有错，欢迎指
出）：

当然，这是一个组合电路。这样子会令后面的输出电路产生毛刺，类似于门控
时钟那样，于是乎我们就可以使用门控时钟那样的技巧，防止输出产生毛刺。这里

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就不详细说明了。

（2）窄脉冲捕捉电路

前面的控制信号，它都需要反馈信号来把有效拉为无效，可以说这个控制信号
是不“自由”的。有时候，我们需要捕捉异步短脉冲控制信号，这个控制信号完全由
前面的逻辑电路生成，与我后面的电路信号无关，也就是说没有反馈信号，你也需
要采样到这个短脉冲控制信号。下面的窄脉冲捕捉电路可以捕捉到快时钟域产生的
异步窄脉冲控制信号，电路如下所示：

波形图如下所示：

从波形图中可以知道，这是利用了脉冲信号的上升沿进行输出脉冲信号，然后通过
后面反馈回来的信号进行清零，从而为下一次脉冲控制信号做好准备。需要注意的
是，窄脉冲控制信号的产生频率不能太快，也就是需要等到清零信号无效（三个触
发器的延时）后才能发出下一个脉冲控制信号，不然后面的慢时钟域采样电路无法
识别两次控制信号，而只当成一次控制信号处理。代码根据电路图写就好了=.=。

========================================== 分 割 线
=====================================================

控制信号的跨时钟域传输到这里就讲完了，下面进行总结一下：

·在跨时钟域的时候，不一定需要跨时钟域电路（同步器或者握手信号），接近
异步时钟或者就是异步时钟的时候跨时钟域就得加上了。

·在慢到快的时钟域中，加上触发器链基本上就可以了，主要是抑制亚稳态的传
播。

·但是在快到慢的时钟域中，不仅需要触发器链进行抑制亚稳态的传播，还要防
止慢时钟域采不到快时钟域的数据，因此就添加反馈/握手电路（这个反馈信号是指
跨时钟域的反馈信号）。

·在最后，介绍了窄脉冲控制信号捕捉电路，这个电路不需要添加反馈信号，也
就是说只要控制信号的频率不是快，只要有窄脉冲（不是毛刺），就可以捕捉得
到，而不需要反馈信号控制脉冲宽度（这个反馈信号是指跨时钟域的反馈信号，其
实还是需要反馈清0的）。

整理了好久才整理完=.=累，终于可以发了......

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PS：本文中的部分图片来自网络

不忘初心：写博客最初目的就是记录自己容易忘记的东西，而不是像写书那样专门写给别人看的。所以，除禁止转载的
博文外，其他博文可以转载。 尽自己的努力，做到更好！

分类: 数字IC（前端）/逻辑设计技巧

标签: 跨时钟域

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~~Record and organize the knowledge you have
learned, and then write it in a blog. From now
on, the blog will be a testimony that you have
not wasted your time, and it can also be

Three analysis modes of static timing analysis (brief description) regarded as a memory left to you. ~~Except for
blog posts that are prohibited from reprinting,
After discussions with industry seniors and reference to some books, the “personal other blog posts can be reprinted.
understanding” part of this article is incorrect, namely:

(Personal understanding:) In a library, although the circuit device unit has been
comprehensively mapped, the tool can obtain different unit delays by changing the surrounding
environment, so even if it is the same library, the calling process parameters are different. , the unit
delays are different, so there are the fastest path and the slowest path. (There is an error here).

For a comprehensive circuit netlist, in a certain pvt environment (that is, when only one library
is read in), the transition and load of the port are constrained, then the delay of a device in the
circuit netlist is Uniquely determined (obtained from library lookup table). In ovc mode, a device
only has two delay values.

Therefore, there are misunderstandings in the following library analysis (delay analysis) Nickname: IC_learner
Age: 6 years and 9 months
process, readers please pay attention! ! ! I will write a special article to correct it in the future.
Fans: 1690
Anyone who studies digital design (digital IC design, FPGA design) must learn Static Timing Followers: 10
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Analysis (STA). However, static timing analysis is a relatively large direction and involves a lot of content.
If you want to learn it systematically, it will take a lot of effort. Here we record the three analysis modes of
static timing analysis. The records here are just to record study notes, or essays, rather than systematically < November 2023 >

learning STA. This article comes from a static timing analysis question I encountered the day before dayone two three Four five six
29 30 31 1 2 3 4
yesterday. I felt a little confused, so I sent it to the group to ask for answers. After some discussion and
5 6 7 8 9 10 11
searching for information, the truth gradually emerged.
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latest comment
I checked some information and found that Synopsys' static timing analysis tool PrimeTime is
described in early userguides, such as the 2010.06 version: 1. Re: A blog link from a senior colleague

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21/11/2023, 14:05 Three analysis modes of static timing analysis (brief description) - IC_learner - Blog Park

Hello blogger, is this senior’s blog no longer

updated? It shows that it cannot be opened.
Can you help me update the link?

--Everything from yesterday has become who

I am today
2. Re: Tcl and Design Compiler (2) - Overview
of DC synthesis and Tcl syntax structure

Hello, how to set up the syntax of checking tcl

using dcprocheck?

--Weaving
3. Re: Tcl and Design Compiler (9) - Formal
verification after synthesis

Can you publish the contents of this file

./scripts/fm.tcl? Otherwise, we only know a set
of commands, but we don’t know which
commands they are.

--AIcoder96
However, in the last two or three years, the BC_WC mode has been ignored and changed to the other three 4. Re:Tcl and Design Compiler (6) - Basic
modes, such as the 2015.12 version: timing path constraints

The design (constraint) specification is as

follows:
(Definition of clock)
(Definition of register setup time)
(Definition of delay of input and output ports)
...
How do you know these known conditions?

--AIcoder96
5. Re: Cross-clock domain signal transmission
(2) - Data signals
Hello poster, thank you for sharing. Your post
is very well written. Some of the circuit
structures are the first time I have seen them.
Thank you very much. I would like to ask
where this picture in the article (that is, the first
picture under the title "When the data rate (or
the frequency of the sending clock) is slightly
higher than the receiving clock end") comes
Although the BC_WC mode is not explicitly written out in the user guide, this mode still exists, which from...
--Beginner classmate
means that this mode can still be used.

In the 2013.01 version of Cadence's timing analysis analysis tool Encounter Timing System, these
three analysis modes are also supported:

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The above tools are all in single mode by default . Returning to the question, I checked and found
that this question was asked 5 or 6 years ago (or even earlier). It is considered a very classic question.
Obviously, the question requires that the setup time and hold time be analyzed first in BC_WC mode.
Before solving the problem, let's take a look at how these three modes analyze setup time and hold time.

For the 2010.06 version of PT:

For the 2015.12 version of PT:

As you can see, 2015.12 does not provide a description of the WC-BC mode, but it is supported.

For ETS: No table is given, but it is similar to PT.

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Next, we will introduce how to analyze the path delay in these three modes. Here we only introduce the
analysis of the setup time, and introduce the hold time depending on the situation.

2. Single analysis mode (the default mode of the tool)

1.Mode introduction

In this mode, the tool will only check the setup time and hold time under a specified working condition .
The working condition may be one of the best, typical, and worst, but it can only be a single one. kind,

There is no configuration here:

(1) Establishment time analysis

Regarding the requirements for the setup time of the flip-flop timing path, the basic calculation formula for
the setup time in a single analysis mode is as follows:

The delay of the slowest path of the sending clock + the delay of the slowest data path
≤ the delay of the fastest path of the capture clock + clock cycle - the termination point timing unit setup
time

进行建立时间检查时,始发点触发器的发射时钟路径延时、终止点触发器捕获时钟路径沿和从
始发点到终止点的数据路径延时都是基于单一工作条件下所计算的路径延时。这是工作单一的一
个库中，也就是工具在同一工艺进程、温度、电源下，调用其他不同的工艺参数，得到最快、最
慢的时钟路径和数据路径。这是路径值是确定的。例如下面例子中（时间单位为ns）：

假设上述电路是在典型库中进行综合的，那么在分析建立时间的时候，工具通过调用不同的工艺
参数，得到最慢的发射时钟路径、最慢的数据路径和最快的捕获时钟路径：

时钟周期=4

发射时钟最慢延时 = U1+U2 = 0.8+0.6 = 1.4

最慢数据路径延时 =3.6

最快捕获时钟延时 = U1+U3 = 1.3

时序单元FF2的建立时间要求查库得到0.2

因此 ：建立时间的slack为：

1.3 + 4-0.2 - 1.4 - 3.6 = 0.1

（2）保持时间分析

保持时间的计算思路是一样的，这里只给出保持时间需要满足的公式，不再举具体例子。单一模
式下要满足的保持时间要求如下所示：

发射时钟最快路径延时 + 最快数据路径延时≥捕获时钟最慢路径延时 + 终止点时

序单元保持时间

2.题目计算

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对于前面的题目，由于题目的要求是在WC-BC模式下，但是假如是在单一模式，我们来看看
该如何分析：

单一库下工具提取到延时信息的理解如下：

下面分析题目中的路径：

对于F1和F2之间的建立时间分析如下所示：

时钟周期 = 2*4 = 8

最慢发射时钟路径（延时） = C1max + C2max = 1

最慢数据路径 = F1cqmax+L1max = 0.7+7 = 7.7

最快捕获时钟路径 = C1min + C2min + C3min = 0.6

F2的D端口建立时间 = 0.3

因此建立时间slack 为 ：

8 +0.6 - 0.3 - 1 - 7.7 = -0.4 （建立时间违规）

对于F1和F2之间的保持时间分析如下所示（题目没有要分析这条路径的保持时间）：

最快发射时钟路径：C1min + C2min = 0.4

最快数据路径：F1cqmin+L1min = 3.2

最慢捕获时钟：C1max + C2max + C3max = 1.5

F2保持时间 = 0.1

因此保持时间slack为:

0.4+3.2 - 1.5 - 0.1 = 2

同理可以分析单一模式下F3-F4路径的保持时间：

最快发射时钟路径：C1min + C2min = 0.4

最快数据路径：F3cqmin + L2min = 0.4

最慢捕获时钟：C1max + C2max + C4max+C5max = 2

F2保持时间 = 0.1

因此保持时间slack为:

0.4 + 0.4 - 2 - 0.1 = -1.3(保持时间违规)

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三、最好-最坏分析模式（BC-WC）
1.模式介绍

对于最好-最坏分析模式，静态时序分析工具会同时在PVT环境中的最好的和最坏的工作环境
下检查建立时间和保持时间。也就是说，使用这个方式的时候，至少需要读入两个库（环境），
一个用来设置最好的工作环境（或者说延时最小），一个用来设置最坏的工作环境（或者说延时
最大）。

（1）建立时间分析

最好-最坏分析模式中建立时间的基本计算公式与单一分析模式下建立时间的基本计算公式一
致，不同点在于计算建立时间所使用的工作环境不同，在计算建立时间过程中静态时序分析工具
调用逻辑单元的最大（max）延时时序库，并用来检查时序路径最大延时是否满足触发器建立时
间。

例如对下面电路进行建立时间分析：

时钟周期 = 4

发射时钟最慢路径延时（max库）=U1单元延时（max库）+U2单元延时（max库）
=0.7+0.6=1.3

最慢数据路径延时（max库）=3.5

最快数据路径延时（max库） =1.9

捕获时钟最快路径延时值（max库） = U1单元延时（max库）+ U3单元延时（max库）

=0.7+0.5=1.2

建立时间要求（max库） = 0.2

因此触发器之间路径的建立时间slack为：

1.2 + 4 - 0.2 -1.3 - 3.5 = 0.2

（2）保持时间分析

同样，最好-最坏路径分析模式中保持时间的基本计算公式与单一分析模式下保持时间的基本
计算公式一致。不同点在于计算保持时间所使用的工作环境不同。在计算保持时间过程中，静态
时序分析工具调用逻辑单元的最小(min)延时时序库，并用来检查时序路径最小延时是否满足触发
器保持时间的约束。 即进行保持时间检查时，始发点触发器的发射时钟延时、终止点触发器捕获
时钟延时和从始发点到终止点的数据路径延时都是基于最好工作条件下所计算的路径延延时

例如对下面电路进行保持时间分析：

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时钟周期 = 4

发射时钟最快路径延时（min库）=U1单元延时（min库）+U2单元延时（min库）=0.5+0.4=0.9

最快数据路径延时（min库）=1

最慢数据路径延时（min库） =2.3

捕获时钟最慢路径延时值（min库） = U1单元延时（min库）+ U3单元延时（min库）

=0.5+0.3=0.8

保持时间要求（min库） = 0.1

因此触发器之间路径的保持时间slack为：

0.9+1-0.8-0.1 = 1 （保持时间不违规）

2.题目计算

对于我们的题目，就是要求我们在BC-WC模式下进行分析建立时间和保持时间。现在就来分
析一下。

首先我们分析工具提取到延时信息：

这里我们需要注意，本来我在读入max库的时候，应该有会得到max库下的单元延时的最大最小
值；在读入min库的时候后，会得到min库下单元的最大最小值。题目中相当于只有一个库下单元
延时的最大最小值，这个库取了max库的最大延时，同时取min库的最小延时。因此在进行WC分析
的时候，我们就将max库中的单元延时最大和最小值看做相等进行处理，即max库中单元只有一个
固定延时值（即上面的max列表里面）。同理BC分析的时候，min库中的单元也只有一个延时值
（即上面的min列表里面）。

下面就对时序路径进行分析：

对于F1-F2路径的建立时间分析如下所示：

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时钟周期 = 2*4 = 8

最慢发射时钟路径（max库） = C1max + C2max = 1

最慢数据路径（max库） = L1max = 7

最快捕获时钟路径（max库） = C1maxmin + C2maxmin + C3maxmin=C1max + C2max + C3max

= 1.5 (maxmin表示max库下的最快路径)

F2的D端口建立时间 （max库）= 0.3

因此建立时间slack 为 ：

8 +1.5 - 0.3 - 1 -0.7- 7 = 0.5

对F3-F4路径的保持时间分析如下所示：

最快发射时钟路径（min库）：C1min + C2min = 0.4

最快数据路径（min库）：F3cqmin + L2min = 0.4

最慢捕获时钟（min库）：C1minmax + C2minmax + C4minmax+C5minmax =C1min + C2min +

C4min+C5min=0.8 (minmax表示min库下的最慢路径)

F2保持时间 = 0.1

因此保持时间slack为:

0.4 + 0.4 - 0.8 - 0.1 = -0.1 (hold time violation)

4. OCV analysis mode

In the chip variation related operating mode, like the best-worst analysis mode, the static timing
analysis tool will also check the setup and hold times under the best and worst operating conditions in the
PVT environment, that is, to Read in two libraries.

1.Basic OCV mode:

(1) Analysis of establishment time

The basic calculation formula of the setup time in the OCV analysis mode is consistent with the basic
calculation formula of the setup time in other analysis modes. The difference is that the working
environment used to calculate the fastest path and the slowest path is different. In the process of
calculating the setup time, the static timing The analysis tool calls the maximum delay timing library of the
timing unit to calculate the delay of the slowest path. At the same time, it calls the minimum delay timing
library of the logic unit to calculate the delay of the fastest path. It only checks whether the delay of the
timing path meets the trigger. Establish time constraints.

When doing a setup time check. The launch clock of the originating point flip-flop adopts the slowest
clock path under the worst conditions, the capture clock of the ending point flip-flop adopts the fastest
clock path under the best conditions, and the data path from the originating point to the ending point The
latency is the slowest data path latency under worst-case conditions.

For example:

clock period = 4

The slowest path delay of the transmit clock (max library) = U1 unit delay (max library) + U2 unit
delay (max library) = 0.7 + 0.6 = 1.3

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Slowest data path latency (max library) = 3.5

Capture clock fastest path delay value (min library) = U1 unit delay (min library) + U3 unit delay
(min library) = 0.5+0.3=0.8

Setup time requirement (max library) = 0.2

Therefore the establishment time slack of the path between triggers is:

0.8 + 4 - 0.2 -1.3 - 3.5 =- 0.2 (timing violation)

·Hold time: similar, no detailed description

(2) Calculation of questions

For our question, assuming we want to perform calculations in basic OCV mode, let's take a look:

First of all, the analysis of the library is the same as the WC-BC mode, so I will not repeat the explanation:

Then analyze the timing path:

The establishment time analysis of the F1-F2 path is as follows:

Clock period = 2*4 = 8

Slowest transmit clock path (max library) = C1max + C2max = 1

Slowest data path (max library) = F1cqmax+L1max = 0.7+7 = 7.7

Fastest capture clock path (min library) = C1min + C2min + C3min= 0.6

D port setup time of F2 = 0.3

Therefore, the creation time of slack is:

8 +0.6 - 0.3 - 1 -7.7= -0.4 (setup time violation)

The hold time analysis of the F3-F4 path is as follows:

Fastest transmit clock path (min library): C1min + C2min = 0.4

Fastest data path (min library): F3cqmin + L2min = 0.4

The slowest capture clock (max library): C1max + C2max + C4max + C5max =2

F2 hold time = 0.1

Therefore, the holding time slack is:

0.4 + 0.4 - 2 - 0.1 = -1.3 (hold time violation)

For the above question, when calculating and analyzing the setup time in the basic OCV mode, the
common paths C1 and C2 use the slowest delay of the max library when calculating the slowest transmit

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clock path; while when calculating the fastest capture clock path The fastest delay of the min library is
used. In other words, this analysis treats the output of the common path as two signals with different
propagation delays for delay calculation. However, when the chip actually works, the output of the
common path is a signal that drives the subsequent launch clock and capture clock. The above inspection
analysis is too pessimistic and not realistic, so it is extended to the following two modes.

2. OCV mode considering timing reduction:

The function of timing derate is based on the derating coefficient. The static timing analysis tool will
add or subtract an original delay value multiplied by the derating on each level of logic gates, connections
and ports in the timing path. The delay of the coefficient value is used as the final delay result. The purpose
of setting the timing reduction value is to make the timing analysis results more consistent with the actual
situation.

Using this method requires setting the derating coefficient, and the coefficient value needs to be
summarized through actual engineering experience. We will not discuss it in depth here, and the coefficient
is not given in the question, so we will not introduce it in depth.

3. Consider the OCV mode with clock path pessimistic removal (CPPR):

It can be divided into situations where timing reduction is not considered and timing reduction is
considered. This is not introduced here. If you are interested, you can refer to relevant information.

Other advanced analysis modes such as AOVC, POCV, etc. involve a lot of content, so I won’t write about
them. If you are interested, you can refer to the relevant information.

References:

"Static Timing Analysis and Modeling of Integrated Circuits", Liu Feng, 2016

PrimeTime User Guide, synopsys, 2015

PrimeTime Fundamentals User Guide, synopsys, 2010

"Encounter Timing System User Guide", cadence, 2013

Don’t forget your original intention: The original purpose of writing a blog is to record things that you easily forget, rather
than writing specifically for others to read like writing a book. Therefore, except for blog posts that are prohibited from
reprinting, other blog posts can be reprinted. Try your best to do better!

Category: Static Timing Analysis and Primetime

Tag: static timing analysis

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