Scaling of MOSFETs unit -3

Drain-induced barrier lowering (DIBL) and VT roll off

Because of the short-channel effect, channel formation is not entirely done by the gate, but now the
drain and source also affect the channel formation. As the channel length decreases, the depletion
regions of the source and drain come closer together and make the threshold voltage (VT) a function of
the length of the channel. This is called VT roll-off. VT also becomes function of drain to source voltage
VDS. As we increase the VDS, the depletion regions increase in size, and a considerable amount of
charge is depleted by the VDS. The gate voltage required to form the channel is then lowered, and thus,
the VT decreases with an increase in VDS. This effect is called drain induced barrier lowering (DIBL).

Double-diffused metal-oxide-semiconductor (DMOS)

There are LDMOS (lateral double-diffused metal oxide semiconductor) and VDMOS (vertical double-
diffused metal oxide semiconductor). Most power MOSFETs are made using this technology.

Power MOSFET Basics Working Principle and Applications

Power MOSFET

The Power MOSFET is a type of MOSFET. The operating principle of power MOSFET is similar to the
general MOSFET. The power MOSFETS are very special to handle the high level of powers. It shows the
high switching speed and by comparing with the normal MOSFET, the power MOSFET will work better.
The power MOSFETs is widely used in the n-channel enhancement mode, p-channel enhancement
mode, and in the nature of n-channel depletion mode. Here we have explained about the N-channel
power MOSFET. The design of power MOSFET was made by using the CMOS technology and also used
for development of manufacturing the integrated circuits in the 1970s.

What is a Power MOSFET?

A power MOSFET is a special type of metal oxide semiconductor field effect transistor. It is specially
designed to handle high-level powers. The power MOSFET’s are constructed in a V configuration.
Therefore, it is also called as V-MOSFET, VFET. The symbols of N- channel & P- channel power MOSFET
are shown in the below figure.

Power MOSFET

Basic Statures of Power MOSFET

There is three basic status in the power MOSFET which is following.

 On sate resistance
 Breakdown voltage
 Body diode

On State Resistance

If the power MOSFET is in ON sate, then it produces the resistive behavior in-between the drain &
source terminals. We can see in the following figure, that the resistance is the sum of many elementary
contributions. The RS resistance is the source resistance. It will show all resistance between the source
terminals of the package to the channel of the MOSFET.

Break Down Voltage

The power MOSFET is equivalent to the PIN diode, if it is in the OFF state and it is initiated by the P+
diffusion, the N- epitaxial layer and the N+ substrate. This structure is reverse biased when it is highly
nonsymmetrical structure and the space charge region extends principally to the lightly doped side,
which is the N- layers.

Even though, when the MOSFET is in the ON state, there is a no function of the N- layers. Moreover, it is
lightly doped rejoin, intrinsic resistivity is non-negligible and it is added to the MOSFET ON- state drain
to source resistance.
 Break Down Voltage

There are two important parameters to run both the breakdown voltage and the RDSon of the
transistor, which is the doping level and the thickness of the N- epitaxial layer. If the layer is thicker, it
has low doping level and the breakdown voltage is high. Similarly, thicker the layer, it has the high
doping level and the radon is low. Hence we can observe that there is a trade-off in the design of the
MOSFET, between the voltage rating and the ON state resistance.

Body Diode

The body diode can be seen in the following figure that the source metallization is connected to both
the N+ and P implantations. Even though the basic principle of the MOSFET requires only that the source
should be connected to the N+ zone. Thus, this would result in a floating P zone between the N-doped
source and drain. It is equivalent to an NPN transistor with a nonconnected base. Under some
conditions like high drain current, in the order of the same volts of an on-state drain to source voltage,
this parasitic transistor of NPN should be triggered and make the MOSFET uncontrollable.

Body Diode

The connections of the P implantation to the source metallization short the base terminal of the
transistor parasitic to its emitter and it prevents the latching. Hence this solution creates a diode
between the cathode & anode of the MOSFET and the current blocks in one direction.

For inductive loads, the body diodes utilize the freewheeling diodes in the configuration of H Bridge &
half bridge. Generally, these diodes will have a high forward voltage drop, the current is high. They are
sufficient in many applications like reducing part count.

Working with Power MOSFET and Characteristics

The construction of the power MOSFET is in V-configurations, as we can see in the following figure. Thus
the device is also called as the V-MOSFET or V-FET. The V- the shape of power MOSFET is cut to
penetrate from the device surface is almost to the N+ substrate to the N+, P, and N – layers. The N+
layer is the heavily doped layer with a low resistive material and the N- layer is a lightly doped layer with
the high resistance region.
 N – Channel Power MOSFET

Both the horizontal and the V cut surface are covered by the silicon dioxide dielectric layer and the
insulated gate metal film is deposited on the SiO2 in the V shape. The source terminal contacts with the
both N+ and P- layers through the SiO2 layer. The drain terminal of this device is N+.

The V-MOSFET is an E-mode FET and there is no exists of the channel in between the drain & source till
the gate is positive with respect to the source. If we consider the gate is positive with respect to the
source, then there is a formation of the N-type channel which is close to the gate and it is in the case of
the E-MOSFET. In the case of E-MOSFET, the N-type channel provides the vertical path for the charge
carriers. To flow between the drain and source terminals. If the VGS is zero or negative, then there is no
channel of presence and the drain current is zero.

The following figures show the drain & transfer characteristics for the enhancement mode of N-channel
power MOSFET is similar to the E-MOSFET. If there is an increase in the gate voltage then the channel
resistance is reduced, therefore the drain current ID is increased. Hence the drain current ID is
controlled by the gate voltage control. So that for a given level of VGS, ID is remaining constant through
a wide range of VDS levels.
Transfer & Drain characteristics

The channel length of the power MOSFET is in the diffusion process, but in the MOSFET the channel
length is in the dimensions of the photographic masks employed in the diffusion process. By controlling
the doping density and diffusion time, the channel length will become shorter. The shorter channels will
give, the more current densities which will contribute again to larger power dissipation. It also allows a
larger transconductance gm to be attained in the V-FET.

Long channel carbon nanotube transistor

(CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When
maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the
channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a
nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET) channel is assessed
qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated
CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that
long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in
silicon MOSFET while sustaining the same unit area at higher current density.

1. Introduction

Carbon nanotubes (CNTs) are gaining momentum in the current silicon technology as a complementary
nanostructure that could reform the device architecture. CNT modeling has been rigorously studied and
examined [1–5] to assess the performance of the device at the circuit level. Advancement of the
nanotechnology devices modeling is vital for the foreseeable future of carbon nanotube as switching
device, interconnect and memory in integrated circuits (ICs). An in situ growth single-walled carbon
nanotube (SWCNT), which integrates long channel 600 nm CNT channel, thin Al2O3 top gate contact,
and Palladium (Pd) metal source/drain contacts, has been demonstrated [6].
In addition, we report the potential of long channel 65 nm CNT as substitute to 45 nm silicon metal-
oxide semiconductor field-effect transistor (Si MOSFET) from the perspective of modeling for future
CNT-logic applications. We observe good agreement between CNTFET and Si MOSFET, respectively,
when simulating two-terminal drain current–voltage () characteristic. The projection has shed light on
the reduction of DIBL and high field effects [7] as well as reduction in long channel CNT which is a
widespread phenomenon in nanoscale Si MOSFET [8, 9]. We also demonstrate the effects of the channel
area restructuring on the maximum electric field as well as density of states (DOS) in the conductance of
CNT. Unlike MOSFET, it is revealed that the performance of CNT is enhanced when the source and drain
width is minimized rather than the length, primarily due to the gate-to-source-drain parasitic fringe
capacitances [10]. MOSFET scaling in accordance with Moore’s Law will reach its fundamental limitation
as a result of process controllability in the next 10 years. Consequently, it is necessary to ensure that
novel material is studied to provide alternatives to the current technologies and challenges in the new
era of nanotechnology.

2. Carbon Nanotube and MOSFET Modeling

The layout of a CNTFET device is depicted in Figure 1. The area of the channel is given by the
multiplication of the width, , of the source and drain contact and the length, , of the nanotube [6].
Details of the quasiballistic MOSFET device modeling can be found in previous work in [11, 12].

Figure 1: The unit area size of CNT channel with source and drain.

The carbon nanotube model [13] is a unified nanostructure model based on quantum transport theory
established by Datta [14]. This work extended the universal DOS spectral function [15] into the
numerical calculation for CNT conduction subbands. We have included multiband density of states to
account for multimode transport [16]. For an accurate simulation, the input parameters shown in
Table 1 for MOSFET and CNTFET are extracted from TSMC [17] and Javey et al. [18], respectively. The 60
nm nanotube device model incorporate quasiballistic transport scattering as confirmed by [18]. At 60
nm length, the carriers travelling on the CNT surface have smaller mean free path than acoustic phonon
which occurred at 300 nm.

Table 1: Device model input and output parameter at V.

The typical width of a high-tech CNTFET device is reported [10] to be 1 μm. The width of the CNT is
calculated to be , when both CNT and MOSFET devices are having identical channel area . In a case when
both devices can provide same level of current, channel area becomes when given the scaling
factor; and both parameter . CNT channel with length, , can provide the same current with . Even when
the physical widths of the CNT channel, , there is no area drawback provided . As nanotube channel
length increases, maximum electric field in CNT, reduces tremendously [19, 20]. As for CNT with nm,
the maximum electric field is found to be .
In the simulation of CNTFET, Landauer-Buttiker formalism is utilized [21]. The drain current, is given
aswhere is the ON-conductance, is the channel potential, is the Fermi energy, is the Boltzmann
Constant, is the temperature, is the charge of an electron, is the gate voltage, is the drain voltage,
and is the source voltage.
The quantum conductance limit of a ballistic SWCNT is . The theoretical framework of (1) derivation can
be found in [19, 20]. The quasi-one-dimensional (Q1D) density of state function of CNT [22] is given
bywhere and is the carbon-to-carbon (C–C) bonding energy, is the bandgap energy, is the spin
degeneracy, and is the valley degeneracy. On the other hand, the characteristics for a short channel
MOSFET can be expressed aswhere is the gate capacitance, is the gate-field dependent mobility, is the
saturation voltage at the point of current saturation, is the critical voltage, and is the threshold voltage.
At current saturation, (3) becomeswhere is ratio of drift velocity, with saturation velocity and at the
drain [11, 23].

3. Results and Discussion

Figure 2 shows the density of states for Q1D of zigzag CNT with three van Hove singularities. As the
energy span widens, more electrons are capable of occupying the singularities pinned between source
and drain Fermi levels.

SiC MOSFET design

challenges While the use of silicon carbide promises many advantages thanks to being a wide bandgap
material, there are also some noteworthy differences to silicon leading to a number of challenges when
making a SiC MOSFET based on the 4H-SiC poly type, the most prominent silicon-carbide polymorph
used for power semiconductor devices