1.

Run SoC Encounter

> encounter
or
> velocity
The Encounter window will pop up. Although we will do our work in the GUI window, you should always check the
Terminal (where we start Encounter) for error messages after each step because all the information is only printed
there.

2. To begin, click Design → Import Design

3. In the Design Import window, click Load...

then find the configuration file mod_m_counter.conf in folder script and click OK.

You should then find that Common Timing Libraries and LEF Files are filled up.
In the Design Import window, specify the Verilog Netlist file (generated by Design Compiler) and the Timing
Constraint File (.sdc) generated by synthesis, and the Max/Min/Common Timing Libraries and the LEF File from the
technology directories. You can either let Encounter automatically recognize your top level design (select Auto
Assign), or explicitly write in the top level design name (select By User) as shown above. There are also some settings
in the Advanced tab, set up by the configuration file, so you don't need to worry about that.
 Any options that you change, you can save these options in a configuration file *.conf (e.g. mod_m_counter.conf).
Click OK, your design is imported, and you can find the design status is In Memory at the top-right corner of the GUI
window.
4. Specify Floorplan
Click Floorplan →Specify Floorplan and then select Specify by Size and Core Size by: and Aspect Ratio. Set Ratio
(H/W) to 1 and Core Utilization to 0.7. Set Core Margins by: to Core to IO Boundary and all Core Margins to 40, then
click OK.

Now the main windows should look like this:

 Click Floorplan → Connect Global Nets. Here we need to add 4 connections. That is for each of Power (VDD) and
Ground (VSS) we need to bind the signal name to the pin name, and the signal name to the meaning of "high" or
"low" logic levels. First, make sure Apply All and Override prior connection are checked. You need this for each
connection. Select Pin and set Pin Name(s) to VDD and To Global Net to VDD too. Then press Add to List. Now Select
Tie High and clear Pin Name(s) and click Add to List. Now do both steps again for VSS (with Tie LOW). You should see
the following view:

In the end, click Apply, then Check, and finally Close. (Always check the command window for possible errors)
5. Power Planning
Click Power → Power Planning → Add Rings
In the add rings window, the power and ground nets (VSS VDD) should already be there. Select the same "H"
(horizontal) metal layer for Top and Bottom ring, and neighboring "V" (vertical) metal layer for Left and Right ring.
For example, for the Top and Bottom layer use METAL 5, and then you can use METAL 6 for the Left and Right layers.
Then, set all the Width and Spacing to 5, and select Center in channel for Offset, then click OK, as shown below.

At this point, the Encounter window should look like:

If your design is big and your floorplan looks quite large, you should consider adding stripes to lower the resistance
to the power and ground rings (it is actually optional). Click Power → Power Planning → Add Stripes. In the add
stripes window, the power and ground nets (VDD and VSS) should already be there. Use the same metal layer as the
vertical wire in your power rings (METAL6 in our case), and make sure Vertical is selected for direction. For width and
spacing, use values not larger than rings (preferably smaller). Select Number of sets and fill in the desired number.

This will generate several pairs of power and ground wires in vertical direction which are distributed in horizontal
direction as shown below:
6. Setup controls for power routing
Click Route → Special Route. In the special route window, the power and ground nets (VDD and VSS) should already
be there. Deselect Pad pins and Pad rings. The window should look like this:

In the Advanced tab click on Extension Control. For Standard cell pins and stripes choose Last pad rings or pad pins.
For Block pins choose Nearest Ring/Stripe. However, it is not guaranteed that those choices fit your design. The
routed wires may still stop before reaching your desired ring/strip. In such cases, try different extension control
options. In a large design, the special route may take a long time and have a lot of undesired connections, because
the same extension control options may not be applicable to all the parts. Then click OK to add VDD and VSS supply
lines, as shown:
 Now save you design as mod_m_counter_pre_place.enc (or something like that) from Design → Save Design As as
bellow:

7. Placement
Click Place → Standard Cells.
 Click OK. After it has finished, click Place → Check Placement and then OK. This will generate
mod_m_counter.checkPlace file in your current working directory. Read the report and make sure no violation has
happened. You can also check this via the console window. At this point, by clocking on Physical view button the
Encounter window should look like:

8. Check Timing
Click Timing → Analyze Timing. In the Timing Analysis window, make sure Pre-CTS is selected.

Click OK. This will first run a Trial Route (you can see the route result in Encounter window as shown below) and then
perform timing analysis based on the trial routing result.
Look in the Terminal window to see if there are any path violations:

If a violation happens, click Timing → Optimize and then click OK. After that, run Timing Analysis again. If violations
still exist, you should re-synthesize your HDL design, possibly using a slower clock, and redo all the procedures up to
this point. It is a good idea to optimize your design before moving to the next step even there is no violation.
 Execute report_timing in command window to see more details on the design’s critical path:

9. Clock Tree Synthesis (CTS)

Click Clock → Design Clock. Click Mode, then select Optimization tab under CTS mode, select Resize And Insert
Buffer/Inverter, then click OK.

Click Gen Spec. In Generate Clock Spec window, select from BUFX2 all through RFRDX4 and then click Add so that
they appear in the Selected Cells list, as shown
Click OK in Synthesize Clock Tree window and the design should look like this:

Perform Timing → Analyze Timing but with Post-CTS selected this time and check the result on command window. If
there is a violation, run Timing → Optimize (with Post-CTS and Setup and/or Hold selected) and do Analyze Timing
again to see if the problem is fixed. Now save you design as mod_m_counter_post_CTS.enc (or something like that).
Click Route → Trial Route. Select high effort and click OK, as shown:
 Click Timing → Extract RC and then click OK. Next, click Timing → Analyze Timing. Select Use Existing Extraction and
Timing Data and then click OK. Look at Terminal, find if any violation exists. If yes, try to run Timing → Optimize (with
Post-Route selected) to fix that.
10. Routing and Filler insertion
Click Route → Nanoroute → Route. Select Timing Driven (you can change effort) and SI Driven, then click OK, as
shown:

Look into the Terminal, make sure there are no violations or errors. Perform Timing → Analyze Timing with Post-
Route and Include SI selected and check the result on command window.
If there is a violation, run Timing → Optimize (with Post-Route and Setup and Include SI selected). Click SI Options
and select High for Effort Level. Click Done in Fix Crosstalk and OK in Optimization window. Do Analyze Timing (with
Include SI selected) to see if the problem is fixed.

Click Place → Physical Cells → Add Filler.

Click Select in front of Cell Name(s) and then select and add all the cells in the Cells List to Selectable Cells List, then
click OK.
 The design should look like this:

Once again, click Floorplan → Connect Global Nets. Click Apply, then Close. Perform Timing → Analyze Timing with
Post-Route and Include SI selected and check the result on command window. If there is a violation, run Timing →
Optimize (with Post-Route and Setup and Include SI selected).

11. Post routing analysis

Perform Verify → Verify Geometry and Verify → Verify Connectivity and check the Terminal to see if there is any
problem. Go to Design → Report and get Gate Count and Netlist Statistics if you want.

12. Run final timing analysis

Click Timing → Analysis Condition → Specify RC Extraction Mode.
Select Default, click OK. Click Timing → Extract RC and select all output files and then click OK.

Now Encounter has enough information for delay calculation. Click Timing → Calculate Delay. Specify the name of
the mod_m_counter_enc.sdf file, and then click OK.

Now you can save your design by clicking Design → Save → Netlist and selecting mod_m_counter_enc.v as the name.
You may also want to save your design as mod_m_counter_final.enc by clicking Design → Save Design As → SoCE.