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Vlsi Projects

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vrunda1664
Copyright
© © All Rights Reserved
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Global Techno Solutions®

VLSI/FPGA/CPLD (Transaction/Journal Papers)

Global Techno Solutions – GTS, a software development and solution providers concern
renders technology solutions to a diverse range of customer. Beginning its journey in the field of
information technology in the year 2003, GTS operates with the integrity to the highest standards of
business conduct.

Key Benefits to Students:

 Internship Projects from industry Exert with 19 years of Experience.


 IEEE Latest Papers with Complete Documentation and Review Materials.
 Projects in wide range of Domains.
 Module wise Demo and Laptop Configuration.
 100% Project Output assured.
 Certificates will be provided (Confirmation, Completion and LOR)
 100% Online Support.
 Supporting Journal Publishing (i.e. IEEE, Scopus etc.,)

CLICK HERE TO WHATSAPP

Whatsapp: 9025434960 Email: [email protected]


www.finalyearprojects.in
Global Techno Solutions®
VLSI/FPGA/CPLD (Transaction/Journal Papers)

1. .23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array

in SiGe BiCMOS for 5G Applications (Trans. Nov 2020)

2. A Client-Based Fast Channel Change Technique Using Multiple Decoder Clocks.(Trans.

Feb 2020)

3. A Discrete-Time MOS Parametric Amplifier-Based Chopped Signal Demodulator.(Trans.

Nov 2020)

4. A Highly Efficient Conditional Feed-through Pulsed Flip-Flop for High-Speed

Applications. (Trans. Jan 2020)

5. A Platform of Resynthesizing a Clock Architecture into Power-and-Area Effective Clock

Trees.(Trans. Oct 2020)

6. A Reconfigurable 64-Dimension K-Means Clustering Accelerator with Adaptive Overflow

Control.(Trans. April 2020)

7. An Analysis of DCM-based True Random Number Generator.(Trans. June 2020)

8. An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery

Circuits.(Trans. Nov 2020)

9. Gen Map: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-

Grained Reconfigurable Architectures.(Trans. Nov 2020)

10. Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise

Current Matching.(Trans. Nov 2020)

11. Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register.(Trans. Oct 2020)

12. Low-Cost and Power-Efficient Massive MIMO Precoding: Architecture and Algorithm

Designs.(Trans. Jul 2020)

13. Low-Cost and Programmable CRC Implementation Based on FPGA.(Early Access July

2020)

Whatsapp: 9025434960 Email: [email protected]


www.finalyearprojects.in
Global Techno Solutions®
VLSI/FPGA/CPLD (Transaction/Journal Papers)

14. Memristive Computational Memory Using Memristor Overwrite Logic (MOL) (Trans. Nov

2020)

15. Multi-Channel Signal Generator ASIC for Acoustic Holograms.(Trans. Jan 2020)

16. Performance Modeling for CNN Inference Accelerators on FPGA.(Trans. April 2020)

17. Phase Coherent Frequency Hopping in Direct Digital Synthesizers and Phase Locked

Loops.(Trans. June 2020)

18. Ultra-Low Power CMOS Image Sensor With Two-Step Logical Shift Algorithm-Based

Correlated Double Sampling Scheme.(Trans. Nov 2020)

19. A Low-Power, High-Performance Speech Recognition Accelerator .(Trans Dec 2019)

20. A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined

ADCs.(Trans Nov 2019)

21. Design of Adiabatic Quantum-Flux-Parametron Register Files using a Top-Down Design

Flow.(Trans Aug 2019)

22. Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree

Synthesis.(Trans Jan 2019)

23. Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors.(Trans

March 2019)

24. Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration.(Trans Feb

2019)

25. RotaSYN: Rotary Traveling Wave Oscillator Synthesizer.( Trans July 2019)

26. Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs.

(Trans Jan 2019)

27. Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-

D SoCs.(Trans Oct 2019)

Whatsapp: 9025434960 Email: [email protected]


www.finalyearprojects.in
Global Techno Solutions®
VLSI/FPGA/CPLD (Transaction/Journal Papers)

28. Self-synchronized Encryption for Physical Layer in 10Gbps Optical Links.(Trans June 2019)

29. Test-Friendly Data-Selectable Self-Gating (DSSG).(Trans Aug 2019)

30. A Reconfigurable Bidirectional Wireless Power Transceiver for Battery-to-Battery Wireless

Charging.(Trans Aug 2019)

31. A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power

Applications.(Trans Oct 2019)

32. A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor

Crossing Technique for Enhanced Power Efficiency.(Trans Dec 2019)

33. Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme.(Trans

April 2019)

34. WHT and Matrix Decomposition Based Approximated IDCT Architecture for HEVC.(Trans

June 2019)

35. Highly Linear Low-Power Wireless RF Receiver for WSN.(Trans May 2019)

36. A Low-Power Sensitive Integrated Sensor System for Thermal Flow Monitoring.(Trans Dec

2019)

Whatsapp: 9025434960 Email: [email protected]


www.finalyearprojects.in

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