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2019-Dec EED-213 226

This document contains a 14 question exam for a Digital Electronics and Logic Design course. It is divided into 4 sections with varying point values for each question. Section A contains 5 two-point questions, Section B contains 3 three-point questions, Section C contains 3 five-point questions, and Section D contains 1 ten-point question involving minimizing a Boolean function using K-maps and Quine-McCluskey method. The exam covers topics such as binary subtraction, error detection codes, race conditions in flip-flops, logic gate implementations, ripple counters, encoders and decoders, converters, flip-flop truth tables, modulo-N counters, multiplexers, shift registers, logic families, and Boolean function

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0% found this document useful (0 votes)
20 views2 pages

2019-Dec EED-213 226

This document contains a 14 question exam for a Digital Electronics and Logic Design course. It is divided into 4 sections with varying point values for each question. Section A contains 5 two-point questions, Section B contains 3 three-point questions, Section C contains 3 five-point questions, and Section D contains 1 ten-point question involving minimizing a Boolean function using K-maps and Quine-McCluskey method. The exam covers topics such as binary subtraction, error detection codes, race conditions in flip-flops, logic gate implementations, ripple counters, encoders and decoders, converters, flip-flop truth tables, modulo-N counters, multiplexers, shift registers, logic families, and Boolean function

Uploaded by

anshumanpayasi11
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Roll No.

National Institute of Technology, Hamirpur (HP)


Name of Examination: B.Tech. End Semester Examination (December-2019)

Branch: Electrical Engineering Semester: 3rd


Subject: Digital Electronics & Logic Design Subject Code: EED-213
Time: 3 Hours
Maximum Marks: 50

Note:
1. All the questions are compulsory
2. The marks of each question are indicated against the questions.

Section A
(Question 1 to 5 carry 2 marks each)
1. Using 2's complement subtract (84)16- (2A) 16.
2. Find the single error-correcting code for the information code 10111 for odd parity.
3. With neat and clean diagram; explain how race condition occurred in JK flip flop.
4. Implement and explain the working of three input OR gate operation using diode and
resistor.
5. Show that the NAND connection is not associative.

Section B
(Question 6 to 10 carry 3 marks each)
6. For the ripple counter shown in Figure 1, show the complete timing diagram for eight clock
pulses, showing the clock, Qo and Q, waveforms.

Figure 1.

7. Using Suitable examples make difference between encoder and decoder.


8. Design and implement 3-bit binary to gray code converter using PLA.

Page No. 1.
9. Tabulate truth table for the circuit as shown in Figure 2, and show that it acts as a T-type
flip flop. Tabulate excitation table for T-flip flop also.

Figure 2
10. Design and implement Mod 5 Counter with skipping number 3.

Section C
(Question 11 to 13 carry 5 marks each)

11. Implement the following function F(A,B,C,D)=- E (1,3,6,8,10,11,15) using 4:1


multiplexer and 1:8 Demultiplexer.
12. With neat and clean diagram, explain operation of universal shift register for the data
101011.
13. Discuss DTL and TTL logic circuit in detail.

Section D
(Question 14 carry 10 marks)

14. Solve the function: F (A, B, C, D, E, F) = m(6, 9, 13, 18, 19, 25, 27, 29, 41, 45, 57,61)

using K-Map and Quine - McCluskey method. Based on the observation make comparison
between these two methods in terms of advantage and disadvantage.

Page No. 2.

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