15/11/2023, 15:49 Digital Backend - Signal Integrity Analysis_Digital Backend Timing Analysis-CSDN Blog

Digital Backend – Signal Integrity Analysis

A liter in the ocean Published on 2021-08-23 11:46:23 5.9k reads Collection 137 Likes 12
Classification column: digital backend

digital backend The column contains this content 182 subscriptions 16 articles S

With the continuous advancement of photolithography and integrated circuit manufacturing processes, and the rapid adoption of chip feature s
deep submicrons to nanometers, people have benefited from the greatly improved functions of chips on the one hand, and on the other hand, when
between logic gates As the track length decreases, the gate switching time decreases, which means the output driver rise time becomes shorter, or
frequency can be higher . At the same time, all issues related to signal integrity (SI) have become more serious.

When it comes to crosstalk, people usually first think of the interaction and impact of PCB board-level signal lines. This is also true. Crosstalk is
associated with electromagnetic interference (EMI). Signal integrity analysis and research includes how macro-scale physical interconnections (e.g.
packages, circuit boards, connectors, cables, etc.) affect the quality of signals and power distribution and adopts new strategies, e.g., adopting new
integrity Design technology to validate designs using new modeling, simulation and measurement tools. Although chip design technology has adopt
considered signal integrity from chip to package, in fact, the analysis of package and chip is handled separately. Among the electrical characteristics
timing, crosstalk and power consumption are three important and interrelated analysis contents . Therefore, it is necessary to understand the ge
and phenomenon of crosstalk during the physical installation process of the chip, the factors that cause it, the harm caused to the chip and its preve
is, the analysis and practical solutions to crosstalk.

1. Signal crosstalk and functional failure

1. Generation of crosstalk
Crosstalk on a chip is noise caused by parasitic coupling between interconnect lines , which reflects the non-ideal nature of the physical w
the refinement of chip feature sizes, the physical size and spacing of interconnect lines become smaller, resulting in an increase in the coupling effe
interconnect lines, and crosstalk is generated and enhanced.

Crosstalk can cause signal delays and glitches, which can affect the timing performance and normal functions of the chip. When analyzing cros
call the network that generates the crosstalk signal source the aggressor network (aggressor net or attacker), and the network that is subject to cr
called the victim network (victom net). When the signal on the offending network changes between 0 and 1 levels, corresponding crosstalk noise w
generated on the victim network. This conversion noise can make the signal conversion on the victim network slower, faster, or cause non-monoton
conversion. , thereby interfering or destroying the signal. If noise causes a non-monotonic transition in the signal, a spurious pulse will be produced
glitch . There are many types of glitch interference, which are mainly divided into (1) overshoot, where the signal on the victim node exceeds the po
voltage; (2) undershoot, which means the signal on the victim node is lower than the ground voltage. These pulses destroy the state saved by the g
rendering the gate inoperative or acting incorrectly, causing malfunctions in flip-flops and latches with gate inputs, as shown in the figure below .

2. Noise tolerance
A CMOS circuit unit can withstand a certain level of noise without causing unit output failure . This characteristic is called noise immunity, and
it through noise tolerance. According to the voltage transfer characteristic (VTC) curve, when it is at the unity gain point, the signal change rate is th
this time, there are two ways to define the noise margin: single-source noise margin (SSNM, single- source noise margin) and multiple-source noise
(MSNM, multiple-source noise margin). Actual noise in a project will come from any one or more stages in the circuit.

Signals that compromise a network can be strong (e.g., have a short rise time or a high slew rate), or they can be weak (e.g., have a long rise
low slew rate). Signal crosstalk can be additive or subtractive. The relative signal polarity between the offending network and the victim network dete
coupling or crosstalk effect between them , which is often called the Miller effect.

2. Crosstalk signal analysis

Crosstalk can cause signal delays and glitches , which can affect the timing performance and normal functions of the chip. The tools currently
industry for crosstalk analysis include Cadence's CeltIC or Synopsys' PT to analyze crosstalk pulses and crosstalk delays.
A liter in the ocean focus on 12 137

https://blog.csdn.net/qq_21842097/article/details/119864145?spm=1001.2101.3001.6650.5&utm_medium=distribute.pc_relev… 2/6
15/11/2023, 15:49 Digital Backend - Signal Integrity Analysis_Digital Backend Timing Analysis-CSDN Blog

1. Crosstalk analysis
The content of crosstalk analysis is mainly divided into two aspects, namely the analysis of crosstalk pulses and the analysis of crosstalk delay
are respectively reflected in the calculation of voltage sensitivity values ​and the calculation of delays . Crosstalk analysis can be performed at variou
chip design, and they all analyze two different types of noise problems simultaneously.

When analyzing noise, factors that need to be considered include: timing window, noise threshold setting, noise library and noise model select
coupling capacitor filtering.

(1) The application of time window (TWF, timing window format) file is an important tool in noise analysis. It can reflect the signal flip situation when
actually working in a relatively real-time manner, thereby truly analyzing the impact of noise and avoiding overly pessimistic noise. Analyze the
reduce the difficulty of design.

As shown in the figure, the two mutually influencing signal lines O1 and O2 in the figure are signals transmitted through the two gate circuits I1
Assume that the signal transformation window of I1 is between 2ns and 6ns, and the signal of I2 The conversion window is between 5ns and 9ns, th
signals only meet in the time domain between 5ns and 6ns, so you only need to analyze the noise within this range. If the time window is between 2
and I2 If the time window of the signal is between 6ns and 9ns, the two signals have no interleaved time, so the noise influence between them can b
EDA tools generally assume that there is no time window, calculate the noise problem, filter the low-noise network, and then read in the time window
the high-noise network, thereby reducing the complexity andFollow
time of
theanalysis.
blogger to read the full article

1个可以免费学习IC后端的网站（推荐） 广告
数字ic后端_入门/进阶/实战_快速入门_IC免费学习资源网

Digital backend interview questions

Very comprehensive numerical back- end interview questions, summarized for a long time, I hope it will be helpful to you again.

Reading notes and summary of " Signal Integrity Analysis " DBLLLLLLLL's blog
In order to reduce the voltage rail collapse of the power distribution system, it is necessary to add multiple decoupling capacitors between the power supply and ground.

Learn signal integrity from scratch --7-SI analysis and simulation qq_29476769's

After we determine the information of the signal to be analyzed (including rate, interface level, rise time, etc.), as well as the driver and receiver models, we can calculate

Signal integrity analysis ---crosstalk and reflections Popular recommendations Fighting monsters and upgrading
Definition of signal integrity : Signal Integrity (SI) refers to the signal quality on the signal line. Poor signal integrity is not caused by a single factor, but by a combination o

(9) Static timing analysis of digital backend STA qq_43193623’s

STA: Static timing analysis Purpose: Without using dynamic excitation, statically analyze delay and check whether the timing is satisfied. STA runs through the entire bac

Some basic concepts of digital IC back-end implementation sinat_41774721's

IC backend

Digital Backend – Timing Verification Canghai Yisheng's

Timing verification is to use timing analysis and other methods to verify whether the design meets timing closure.

Autumn Recruitment Collection- Digital Backend xunran111's

Collection of autumn tips for digital backend

Understanding of some issues and concepts XPhp95's B

In the article directory PR stage, FloorPlan needs to carry out: determining the area, setting pins, placing memory, adding ENDCAP and WELLTAP, etc. What are the gen

Basic concepts of digital back-end IC design m0_60873488's

Migration of metal ions due to the action of electric fields in metal conductors. Finally, the net in the chip is short-circuited or open-circuited, thus affecting the life of the c

An overall view of digital back-end design technology

Describes the overall technical overview of IC digital back-end design. The chip design process is introduced.

Digital backend processes and tools

Digital back-end processes and tools at the School of Communications, University of Electronic Science and Technology of China

Mini program backend - simple music A liter in the ocean focus on 12 137

https://blog.csdn.net/qq_21842097/article/details/119864145?spm=1001.2101.3001.6650.5&utm_medium=distribute.pc_relev… 3/6