A BIST Scheme for On-Chip ADC and DAC Testing

Jiun-Lang Huang, Chee-Kian Ong, and Kwang-Ting Cheng

Electrical and Computer Engineering
University of California, Santa Barbara

Abstract used for testing other kinds of ADC’s.

In this paper, we present a BIST scheme for testing on- The proposed BIST scheme in this work employs the
chip AD and DA converters. We discuss on-chip generation delta-sigma modulation technique [7] to generate the re-
of linear ramps as test stimuli, and propose techniques for quired linear ramp for testing the converters. Since we do
measuring the DNL and INL of the converters. We validate not rely on the on-chip AD and DA converters for stimulus
the scheme with software simulation—5% LSB (least signif- generation and data conversion, our BIST strategy does not
icant bit) test accuracy can be achieved in the presence of require the existence of both on-chip AD and DA convert-
reasonable analog imperfection. ers, which makes it feasible for most mixed-signal IC’s.
For ADC testing, we use the proposed BIST strategy to
1 Introduction perform the “linear histogram testing” ([8]) and measure
differential/integral non-linearities (DNL/INL). For DAC
Testing the analog/mixed-signal circuitry of a mixed- testing, we propose a test scheme that employs an analog
signal IC has become a difficult task. The main challenges comparator and two counters for measuring the DAC pa-
originate from the fact that most analog/mixed-signal cir- rameters. The DAC BIST strategy is immune from the com-
cuits are tested by functionality, which is both expensive mon offset voltage of the analog comparator since it is can-
and time-consuming. To resolve the problem, one promis- celed out in the analysis process and thus has little effect on
ing strategy is the the built-in self-test (BIST) approach in the test accuracy.
which both stimulus generation and measurements are per- We demonstrate how the test stimulus, i.e., a linear ramp,
formed on-chip. In this work, we focus on an efficient BIST that can achieve the desired test accuracy is generated,
scheme for testing on-chip AD and DA converters. and perform a series of software simulation to show that
Recently, several BIST schemes for DA and AD con- the stimulus quality has high tolerance to analog variation.
verters were proposed. In [1], the authors utilize the on-chip Measurements of DNL and INL for DA and AD convert-
delta-sigma DAC for sine wave generation and digital signal ers are also implemented in software—a measurement ac-
processing (DSP) techniques for data analysis. However, curacy of 5% LSB can be achieved in the presence of rea-
the technique needs both on-chip ADC and DAC, and inten- sonable analog imperfections.
sive computation, which is not always possible. The BIST In Section 2, we give an overview of the delta-sigma
approach reported in [2] relies on analog circuitry and ref- modulation technique, and DAC/ADC testing. In Section 3,
erence voltages for measurements, which makes it vulner- we illustrate the proposed BIST architecture and the test
able to analog imperfections. The oscillation-test method procedures for the converters. Section 4 discusses the issues
proposed in [3] does not need functional test stimuli. Nev- of generating the linear ramp suitable for our BIST scheme.
ertheless, it is not clear the impact of the control logic delay Simulation results are shown in Section 5 to validate our
and the imperfect analog BIST circuitry on the test accu- ideas. We then conclude the work in Section 6.
racy. The work in [4] proposes an efficient polynomial fit-
ting algorithm for DAC and ADC BIST. The transfer map 2 Preliminaries
of a converter is fitted to a polynomial from which various
parameters like offset, gain, and harmonic distortion can be 2.1 Delta-Sigma modulation based signal genera-
derived. The drawback is again the need of both on-chip tion
ADC and DAC. In [5], the authors propose a BIST method- For on-chip test stimulus generation, we use the delta-
ology for testing AD converters, which is intended to reduce sigma modulation based approach proposed in [7]. A soft-
the number of the ADC output bits that have to be mon- ware delta-sigma modulator converts the desired signal to
itored externally. In [6], a BIST design of current-mode a one-bit digital stream. The digital 1’s and 0’s are then
algorithmic ADC is proposed. The methodology cannot be transferred to two discrete analog levels by a one-bit DAC

1
 ADC
under
1-bit pattern sel test
memory 1-bit DAC LPF
code/index
analog
memory
gen sel
comparator sel
load DAC +
inc
pattern -
under index
DAT
counter
test counter
control
logic
positive
reset
acquire

Figure 1. The BIST scheme.

followed by a low-pass filter which removes the out-of- which corresponds to 1 LSB, is
P
=1


2n,2 T (i)
band high-frequency modulation noise, and thus restores
the original waveform. In practice, one extracts a segment w= i

2n ,2
from the delta-sigma output bit stream that contains an inte-
ger number of signal periods. The extracted pattern is stored and one can obtain the differential and integral non-linearity
in on-chip memory, and periodically applied to the the one- (as fraction of 1 LSB):

T (i) , w) =w
bit DAC and low-pass filter to generate the desired stimulus. DNLi = (
2.2 The converter parameters 0 if i = 0
INLi,1 + (DNLi + DNLi,1 ) =2 otherwise
INLi =
In this work, we are interested in measuring the non-
linearities, i.e., DNL and INL, of the converters. For a DAC, 3 The BIST scheme
INL indicates the deviation of actual output values from the
ideal straight I/O curve, and DNL is a measure of the ir- The overall BIST structure for the proposed ADC/DAC
regularity or non-uniformity in the increments of its output BIST scheme is depicted in Fig. 1. The required functional
voltage or current. blocks and control signals are as follows:
Unlike the DAC, the ADC has a discrete output set but 1-bit pattern memory stores the delta-sigma modulated one-
a fuzzy input, a continuum of input voltage for each output bit digital stream for generating a linear ramp. When
code. The edges of the fuzzy input segments (or decision activated (by gen), its contents are periodically applied
levels) are only statistical quantities, i.e., the most possible to the 1-bit DAC.
values at the existence of dynamic error and noise. One can 1-bit DAC transfers the digital values (1’s and 0’s) to two
adapt most of the DAC parameters to those for ADC—the discrete analog levels.
voltage levels produced by a DAC are analogous to code LPF is a low-pass filter that removes the out-of-band modu-
centers (the centers of the fuzzy input steps) in an ADC. lation noise and thus restores the desired linear ramp.
However, the definition of DNL is different. If the decision The pattern counter generates the desired input codes for
levels are known, one can compute the statistical step width the DAC under test. The load signal loads the counter
for each output code and subtract the average step size to with DAT , and the inc signal increments its contents.
obtain the DNL value.
The analog comparator outputs 1/0 if the the analog quan-
2.3 The linear histogram testing tity in the positive end is greater/less than that in the
For ADC testing, we use the “Linear Histogram Test- negative end.
ing” approach. The analog input is a linear ramp that covers The index counter is reset by the reset signal and incre-
the full-scale range (FSR) of the ADC, and the outputs of mented in each clock cycle.
the ADC are analyzed to create the Tally and Weight arrays The code/index memory acquires and stores the ADC output
(more details can be found in [8].) code or the index counter value when the acquire sig-
Assume that the ADC is an n-bit one, and its output nal is high. The collected data are then analyzed to
codes are c0 ; c1 ; : : : ; c2n ,1 . The Tally array, denoted by T , make the pass/fail decision.
has 2n , 2 elements corresponding to c1 ; c2 ; : : : ; c2n ,2 (the sel directs the output of the LPF to the desired block (the
tallies for code c0 and c2n ,1 are not valid because their in- ADC under test or the analog comparator), and selects
put ranges are not doubly bounded,) and T (i) is the number the input source for the code/index memory (from the
of occurrences of output code ci . The average step width, ADC under test or the index counter.)

2
Note that Fig. 1 shows the BIST structure for testing both v2n - 1
LPF O/P
DAC and ADC. The two counters, and the analog compara- DAC O/P vi DAC O/P

tor are for DAC testing only. v i +1

v2
3.1 Testing the AD converter v1 v i -1

A typical timing diagram for ADC testing is shown in v0

LPF O/P
positive

Fig. 2 (the 1-bit pattern memory stores one period of saw- (b)
tooth waveform in this example.) To test the AD converter, positive
v i +1
we first load the pattern memory with the pre-computed acquire
increment
vi DAC O/P
one-bit delta-sigma stream, direct the LPF output to the t0 LPF O/P

ADC under test, and let the ADC be the input source of t1 v i -1
the code/index memory. The gen signal is then set to high t2n - 1

to activate the signal generation. The acquire signal is set

positive
(a) (c)
to high when the LPF output enters the useful portion of
the sawtooth, which is the part of the linear rising ramp that Figure 3. The DAC testing procedure.
covers the FSR of the ADC, and is set to low when the LPF
v1 is sufficiently greater than v0 , positive goes down and
stays low till the linear ramp reaches v1 when t1 is recorded.
output leaves the useful portion. The ADC output codes
collected when acquire is high are analyzed to derive the
If the transfer map of the DAC under test is monotone in-
Tally and Weight arrays from which the INL and DNL of
creasing and the differences between the output levels of
the ADC can be computed.
Assumes that the duration of the high acquire signal is
adjacent codes are large enough for the analog comparator
l clock cycles. With an n-bit ADC, the required memory to generate a rising edge with respect to each input code,
one will be able to record ti ’s for all the input codes. In
space for storing the ADC output codes is l n-bit words.
such a case, the value of the pattern counter will be c0 and
For example, an 8-bit ADC and 4k collected ADC codes
needs 4k byte memory space.
positive is high at the end of the process.
The DAC parameters are computed from the collected
3.2 Testing the DA converter indices. First, the average separation between adjacent
When testing the DAC, the pattern memory is loaded codes, which corresponds to 1 LSB, is
with the encoded sawtooth waveform, the LPF output is di-
rected to the analog comparator, and the input source of the
w = (t2n ,1 , t0 ) = (2 , 1) n

code/index memory is the index counter. Also, the pattern One can then compute DNL and INL (as fraction of 1 LSB)
counter is loaded with c0 and the index counter is reset. Our by:
DAC BIST scheme uses the linear ramp together with an
analog comparator to measure the analog output levels cor- DNLi =
t , t ,1 , w) =w
( i i

responding to each DAC input code. The idea is illustrated 0 if i = 0

INLi =
in Fig. 3(a). The analog comparator continuously compares INLi,1 + DNLi otherwise
the DAC and the LPF outputs. At the beginning of the linear
ramp (which covers the DAC’s FSR), the former is greater It can be shown that INL2n ,1 = 0 because the approach
and positive is low. When the value of the linear ramp is uses the straight line that passes c0 and c2n ,1 as the lin-
greater than v0 , the output value corresponding to code c0 , earized output line.
the positive signal becomes high. Upon the detection of a In the case when the transfer map of the DAC under test
rising edge at the positive signal, the controller increments is not monotone increasing, e.g., vi+1 < vi (Fig. 3(b)), or
the pattern counter and informs the code/index memory to vi+1 , vi is too small (Fig. 3(c)) to have a rising edge at the
record the current contents of the index counter, i.e., t0 . If positive signal corresponding to ci+1 , the pattern counter’s
value will be ci+1 instead of c0 at the end of the process. To
measure tj for j  i + 1, we restart the process as before
acquire except that we don’t load the pattern counter (so its value
f the
on o m will remain ci+1 at the beginning of the process.) The first
rising edge at the positive will then correspond to ci+1 and
fu l porti avefor
use oth w
to
saw
ti+1 is recorded. As the process continues, tj for j > i +
FSR of ADC

LPF O/P
1 will be recorded, too. If necessary, the process may be
repeated several times to collect all the ti ’s.
output corresponding to
The index counter must be able to count up to the length
of the useful portion of the rising ramp, l, and the memory
one run of 1-bit pattern

Figure 2. Timing diagram for ADC testing. space for storing the indices is thus 2n log2 l-bit words. For

3
 0.04
example, with an 8-bit DAC and linear ramp of 4k clock
cycles, the required memory space is 28 12-bit words.
0.035

0.03

3.3 The test accuracy 0.025

cutoff
0.02
The test strategy for both AD and DA converters is to
0.015
represent the separation between two analog quantities in
0.01
terms of the number of occurrences (ADC) or the number 0.005
of clock cycles (DAC); therefore, quantization error is in-
evitable. The quantization error can be as large as 2=w LSB,
0
0.5 0.6 0.7 0.8 0.9 1
ratio

where w is the average code occurrences for ADC testing

and the average code output separation for DAC testing. For Figure 4. Finding the best shape of the saw-
instance, the quantization error can be as large as 1/8 LSB tooth waveform.
for w = 16.
In addition to the inherent quantization error for the lin- test accuracy is 5% LSB for both AD and DA converters.
ear ramp approach, the noise associated with the generated To maximize the length of the rising ramp in the sawtooth
linear ramp, i.e., its deviation from the ideal straight line, waveform, the 1-bit pattern memory stores exactly one pe-
also contributes to the measurement error. Let the RMS riod of a sawtooth waveform. The selection of the software
value of the deviation be ", the overall test error is approxi- modulator depends on the ratio of the FSR of the convert-
mately upper bounded by ers to the output range of the 1-bit DAC. In general, higher
2 2" order configurations are preferred if stability is not compro-
w + FSR=2 n mised. For our setup, we use the second-order configuration
and set the peak-to-peak value of the sawtooth waveform to
assuming an n-bit converter (the factor 2 reflects the fact be 70% the 1-bit DAC output range. To decide the shape of
that the error can affect the measured values of both sides.) the sawtooth waveform that maximizes the length of the us-
4 Stimulus generation able linear ramp, we first define the non-linearity associated
with a series of evenly sample points R = r0 ; r1 ; r2 ; : : : ; rl
In this section, we discuss how to generate the linear as s
r , (ai + b))2
ramp that achieves the desired measurement accuracy and
(
show that the stimulus quality is tolerant to analog process "= l
i

variation.
The slow-rising linear ramp for testing the converters is where l is the length of the series, and y = ai + b is R’s best-
a portion of the rising ramp of a sawtooth waveform. Since fit line (least square error.) Let be the ratio of the rising
the sawtooth waveform is a multi-tone signal, the restored ramp to the period of the sawtooth waveform. We perform
waveform at the output of the low-pass filter is distorted (es- a series of simulation that varies the value from 0.5 to 1
pecially at the peaks) because of the missing high-frequency and the cutoff frequency of the 2nd order Butterworth low-
components. pass filter from 0.2% to 4% the output frequency of the 1-
As we have discussed in Section 3.3, the test accuracy bit pattern memory (to evaluate the effect of variation in
is improved as the length of the linear ramp (that maps to the low-pass filter.) For each combination of and cutoff
the FSR of the converters) increases and the corresponding frequency, the test accuracy is computed by
RMS deviation decreases. In general, one can control (to
a certain extent) the length of linear ramp and its RMS de- 2 2
viation by (1) adjusting the depth of the pattern memory, w + FSR=28
(2) choosing the order and configuration of the delta-sigma
modulator for generating the one-bit digital stream, and (3) where w is the length of the linear ramp that maps to the
modifying the shape of the encoded sawtooth wave, i.e., the FSR divided by 28 , and " is the corresponding RMS devi-
ratio of the rising ramp to one period. In the following, we ation. Note that the first term represents the quantization
will focus on finding the best shape of the sawtooth wave- error, and the second term the error caused by the non-
form since the first two are usually constrained by hardware linearity of the generated linear ramp. The simulation re-
configuration and cannot be adjusted at will. sult is shown in Fig. 4. The x and y-axis represent and
The configuration of our current setup is as follows: (1) cutoff frequency, respectively. Using 5% LSB as the ac-
the memory depth of the 1-bit pattern memory is N = 214 , curacy threshold, each circle/dot represents a configuration
(2) the nominal output levels of the 1-bit DAC are 5 volts, that satisfies/fails the desired accuracy. One can see that
(3) the FSR for both converters is 3 volts, and (4) the res- the desired accuracy is realizable only for 0:7 <  1.
olutions of both converters under test are 8-bit. The desired We choose = 1 for our sawtooth waveform because it is

4
 DNL - Error INL - Error

most immune from the variation in the LPF (with accept- 0.05 0.05

able LPF cutoff frequency ranging from 0.3% to 3.6% the

pattern memory clock rate).

LSB

LSB
Let the nominal output levels of the 1-bit DAC be b. At
0 0

the existence of analog imperfection, the two output levels

are perturbed to b +  + and ,b +  ,, respectively. The over-
-0.05 -0.05
50 100 150 200 250 50 100 150 200 250
code index code index

(a) ADC: DNL error (b) ADC: INL error

all effect is equivalent to multiplying the nominal 1-bit DAC
outputs by m = 1+( + ,  , ) =2b followed by the addition
DNL - Error INL - Error
0.05 0.05

of a DC component c = ( + ,  , ) =2, which theoretically

will not affect the linearity of the generated ramp. We use

LSB

LSB
0 0

= 1 and cutoff frequency 0.6% the pattern memory out-

put frequency, and perturb both the positive and negative -0.05
50 100 150 200 250
-0.05
50 100 150 200 250

output levels of the 1-bit DAC for up to 4% deviation. Sim- code index code index

(c) DAC: DNL error (d) DAC: INL error

ulation results show that the test accuracy has little variation
over the deviations in the DAC output levels—the accuracy
Figure 5. Simulation results
ranges from 0.035 LSB to 0.039 LSB (the accuracy for the
nominal case is 0.036 LSB.)
ware setup, and (2) extending the scheme for testing other
From the above simulation, one can see that the stimulus
analog functional blocks.
generation scheme is highly tolerant to the analog imperfec-
tions in both the 1-bit DAC and the low-pass filter. Acknowledgment
This work was supported in part by the
5 Simulation results MARCO/DARPA Gigascale Silicon Research Center
To validate the proposed technique, we perform numeri- (http://gigascale.eecs.berkeley.edu). Their support is
cal simulation by applying the generated linear ramp to AD gratefully acknowledged.
and DA converters with known DNL and INL values. (The
setup is as described in Section 4.) From simulation, the References
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axis are the code indices and measurement errors as fraction sign, pages 491–4, November 1994.
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