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2.1 8086 SIGNALS

The 8086 Microprocessor is a 16-bit CPU available in 3 clock rates, i.e. 5, 8

and 10MHz, packaged in a 40 pin CERDIP or plastic package. The 8086
Microprocessor operates in single processor or multiprocessor configurations to
achieve high performance. The pin configuration is as shown in fig1. Some of
the pins serve a particular function in minimum mode (single processor mode)
and others function in maximum mode (multiprocessor mode) configuration.
The 8086 signals can be categorized in three groups. The first are the signals
having common functions in minimum as well as maximum mode, the second
are the signals which have special functions in minimum mode and third are the
signals having special functions for maximum mode.

Figure 2.1.1 8086 signals

[Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M.Bhurchandi]

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The following signal description are common for both the minimum and
maximum modes. AD15-AD0: These are the time multiplexed memory I/O
address and data lines. Address remains on the lines during T1 state, while the
data is available on the data bus during T2, T3, TW and T4. Here T1, T2, T3,
T4 and TW are the clock states of a machine cycle. TW is a wait state. These
lines are active high and float to a tristate during interrupt acknowledge and
local bus hold acknowledge cycles.
A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and
status lines. During T1, these are the most significant address lines or memory
operations. During I/O operations, these lines are low. During memory or I/O
operations, status information is available on those lines for T2, T3, TW and T4
.The status of the interrupt enable flag bit(displayed on S5) is updated at the
beginning of each clock cycle. The S4 and S3 combined indicate which segment
register is presently being used for memory accesses as shown in Table 2.1.1.
These lines float to tri-state off (tristated) during the local bus hold acknowledge.
The status line S6 is always low (logical). The address bits are separated from
the status bits using latches controlled by the ALE signal.
S4 S3 Indication
0 0 Alternate Data
0 1 Stack
1 0 Code or none
1 1 Data
Table 2.1.1 S4 & S3 status

[Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M.Bhurchandi]

BHE/S7-Bus High Enable/Status:
The bus high enable signal is used to indicate the transfer of data over the
higher order (D15-D8) data bus as shown in Table 2.1.2. It goes low for the data
transfers over D15-D8 and is used to derive chip selects of odd address memory
bank or peripherals. BHE is low during T1 for read, write and interrupt

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acknowledge cycles, when- ever a byte is to be transferred on the higher byte of

the data bus. The status information is available during T2, T3 and T4. The signal
is active low and is tristated during 'hold'. It is low during T1 for the first pulse of
the interrupt acknowledges cycle.

BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd
address
1 0 Upper byte from or to even
address
1 1 None
Table 2.1.2 Bus high enable status
[Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M.Bhurchandi]
RD-Read:
Read signal, when low, indicates the peripherals that the processor is performing
a memory or I/O read operation. RD is active low and shows the state for T2, T3,
and TW of any read cycle. The signal remains tristated during the 'hold
acknowledge'.
READY:
This is the acknowledgement from the slow devices or memory that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the 8086. The
signal is active high.
INTR- lnterrupt Request:
This is a level triggered input. This is sampled during the last clockcycle
of each instruction to determine the availability of the request. If any interrupt
request is pending, the processor enters the interrupt acknowledge cycle. This can
be internally masked by resetting the interrupt enable flag. This signal is active high
and internally synchronized.

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TEST:
This input is examined by a 'WAIT' instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
NMI-Non-maskable Interrupt:
This is an edge-triggered input which causes a Type2 interrupt. The NMI is
not maskable internally by software. A transition from low to high initiates the
interrupt response at the end of the current instruction. This input is internally
synchronized.
RESET:
This input causes the processor to terminate the current activity and start
execution from FFFF0H. The signal is active high and must be active for at least
four clock cycles. It restarts execution when the RESET returns low. RESET is also
internally synchronized.
CLK-Clock Input:
The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle. The range of
frequency for different 8086 versions is from 5MHz to 10MHz.
VCC:
+5V power supply for the operation of the internal circuit. GND ground
for the internal circuit.
MN/MX:
The logic level at this pin decides whether the processor is to operate
in either minimum (single processor) or maximum (multiprocessor) mode.
THE FOLLOWING PIN FUNCTIONS ARE FOR THE MINIMUM MODE
OPERATION OF 8086.

M/IO - Memory/IO:
This is a status line logically equivalent to S2 in maximum mode. When it is
low, it indicates the CPU is having an I/O operation, and when it is high, it indicates
that the CPU is having a memory operation. This line becomes active in the previous

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T4 and remains active till final T4 of the current cycle. It is tristated during local bus
"hold acknowledge".

INTA -Interrupt Acknowledge:

This signal is used as a read strobe for interrupt acknowledge cycles. In other
words, when it goes low, it means that the processor has accepted the interrupt.
It is active low during T2, T3 and TW of each interrupt acknowledge cycle.
ALE-Address latch Enable:
This output signal indicates the availability of the valid address on the
address/data lines, and is connected to latch enable input of latches. This signal is
active high and is never tristated.
DT /R -Data Transmit/Receive:
This output is used to decide the direction of data flow through the
transreceivers (bidirectional buffers). When the processor sends out data, this
signal is high and when the processor is receiving data, this signal is low. Logically,
this is equivalent to S1 in maximum mode. Its timing is the same as M/I/O. This is
tristated during 'hold acknowledge'.
DEN-Data Enable
This signal indicates the availability of valid data over the address/data lines.
It is used to enable the transreceivers (bidirectional buffers) to separate the data
from the multiplexed address/data signal. It is active from the middle ofT2 until
the middle of T4 DEN is tristated during 'hold acknowledge' cycle.
HOLD, HLDA-Hold/Hold Acknowledge:
When the HOLD line goes high, it indicates to the processor that another
master is requesting the bus access. The processor, after receiving the HOLD
request, issues the hold acknowledge signal on HLDA pin, in the middle of the next
clock cycle after completing the current bus (instruction) cycle. At the same time,
the processor floats the local bus and control lines.
When the processor detects the HOLD line low, it lowers the HLDA signal.
HOLD is an asynchronous input and it should be externally synchronized.If the

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DMA request is made while the CPU is performing a memory or I/O cycle, it
will release the local bus during T 4 provided:
1. The request occurs on or before T 2 state of the current cycle.

2. The current cycle is not operating over the lower byte of a word (or

operating on an odd address).

3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A Lock instruction is not being executed.

So far we have presented the pin descriptions of 8086 in minimum mode.

THE FOLLOWING PIN FUNCTIONS ARE APPLICABLE FOR MAXIMUM

MODE OPERATION OF 8086.
S2, S1, S0 -Status Lines:
These are the status lines which reflect the type of operation, being carried
out by the processor. These become active during T4 of the previous cycle and
remain active during T1 and T2 of the current bus cycle. The status lines return to
passive state during T3 of the current bus cycle so that they may again become
active for the next bus cycle during T4. Any change in these lines during T3
indicates the starting of a new cycle, and return to passive state indicates end of the
bus cycle. These status lines are encoded in Table 2.1.3.
S S S Indication
2 1 0

0 0 0 Interrupt
acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code Access

1 0 1 Read Memory

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1 1 0 Write Memory

1 1 1 Passive

Table 2.1.3 Status lines S2,S1 & S0

[Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M.Bhurchandi]

LOCK: This output pin indicates that other system bus masters will be
prevented from gaining the system bus, while the LOCK signal is low. The
LOCK signal is activated by the 'LOCK' prefix instruction and remains
active until the completion of the next instruction. This floats to tri-state off
during "hold acknowledge". When the CPU is executing a critical
instruction which requires the system bus, the LOCK prefix instruction
ensures that other processors connected in the system will not gain the
control of the bus. The 8086, while executing the prefixed instruction,
asserts the bus lock signal output, which may be connected to an external
buscontroller.

QS1, QS0-Queue Status:

These lines give information about the status of the code prefetch
queue. These are active during the CLK cycle after which the queue
operation is performed. These are encoded as shown in Table2.1.4.

QS1 QS2 Indication

0 0 No operation
0 1 First byte opcode from the
Queue
1 0 Empty Queue
1 1 Subsequent byte from the
Queue
Table 2.1.4. Queue Status

[Source: Advanced Microprocessors and Microcontrollers by A.K Ray & K.M.Bhurchandi]

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RQ/GT0, RQ/GT1-ReQuest/Grant:
These pins are used by other local bus masters, in maximum mode, to force
the processor to release the local bus at the end of the processor's current bus
cycle. Each of the pins is bidirectional with RQ/GT0 having higher priority than
RQ/ GT1, RQ/GT pins have internal pull-up resistors and may be left
unconnected. The request Grant sequence is as follows:
1. A pulse one clock wide from another bus master requests the bus access to8086.

2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from

8086 to the requesting master, indicates that the 8086 has allowed the local bus
to float and that it will enter the "hold acknowledge" state at next clock cycle.
The CPU's bus interface unit is likely to be disconnected from the local bus of
the system.
3. A one clock wide pulse from another master indicates to 8086 that the 'hold'

request is about to end and the 8086 may regain control of the local bus at the
next clock cycle. Thus each master to master exchange of the local bus is a
sequence of 3 pulses. There must be at least one dead clock cycle after each bus
exchange. The request and grant pulses are active low. For the bus requests those
are received while 8086 is performing memory or I/O cycle, the granting of the
bus is governed by the rules as discussed in case of HOLD, and HLDA in
minimum mode.

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