Module 2

• Introduction to the ARM Instruction Set :

– Data Processing Instructions ,
– Branch Instructions,
– Software Interrupt Instructions,
– Program Status Register Instructions,
– Coprocessor Instructions,
– Loading Constants,
– Simple programming exercises.
• Text book 2: Ch 3:3.1 to 3.6 ( Excluding 3.5.2)
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 Module 2

ARM programming using Assembly language:

Writing Assembly code,
Profiling and cycle counting,
instruction scheduling,
Register Allocation,
Conditional Execution,
Looping Constructs

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 Convention
• ADD r3,r1,r2 instruction adds the two values stored in registers r1 and r2
(the source registers), writes the result to register r3 (the destination
register).

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Module _2_Full 4
 Data Processing Instructions
• The data processing instructions manipulate data within registers.
• They are :
– move instructions
• (MOV,MVN,LDM,LDR,ADR,MRS,MSR,STC,STM,STR)
– arithmetic instructions
• (ADD,ADC,QADD,QDADD,SUB, RSC,QSUB,,RSB,SBC)
– logical instructions
• (AND,EOR,ORR,BIC)
– comparison instructions
• (CMP,CMN,TEQ,TST)
– multiply instructions
• (MLA,MUL,SMULL,SMULxy,SMULwy,SMAL,SMLAxy,SMLALxy)
– Branch instructions
• (B,BL,BLX)
– Interrupt instructions
• SWI Module _2_Full 5
 Move Instructions
• Purpose: copies N into a destination register Rd, where N is a
register or immediate value.

Example:
• Assume R1=8, R2=5
MOV r1, r2
• r1r2
• After execution : R2=5, R1=5 (Note that R2 is unaltered)
MVN r0, #0x00FF
• r0  ~0x00FF
• After the execution: r0 = 0xFFFFFF00

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 Questions
• 1) Give the instruction to Load the constant
0xff00ffff to r0 using an MVN.
• 2) Assume R1=8, R2=5
What is the content of R1 after the execution of
MVN R1,R2

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• 1. Answer: MVN r0, #0x00FF0000
• 2. Answer: R2=5, R1=~5=~00000005=oxfffffffa

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 Barrel Shifter
• N can be a register or immediate value
A register Rm that has been pre processed
by the barrel shifter prior to being used by
a data processing instruction.
• Data processing instructions are processed
within the arithmetic logic unit (ALU).
• A unique and powerful feature of the ARM
processor is the ability to shift the 32-bit
binary pattern in one of the source registers
left or right by a specific number of
positions before it enters the ALU.

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 Example: barrel shifter
• A logical shift left (LSL) to register Rm before moving it to the
destination register. Condition flag is updated only if S is present
in the instruction.
Purpose The MOV instruction copies the shift operator result N into register Rd. N represents
the result of the LSL operation
Usage Example MOV R1,R2,LSL #2
Explanation Moves the contents of register r5 and copies them into register r7
Pre-Condition R1=5, R2=8
Instruction Usage
MOV R1,R2,LSL #2 ; r1 = r2<<2
0000 0000 0000 0000 0000 0000 0000 1000
=0x08
➔0000 0000 0000 0000 0000 0000 0010 0000
= 0x20
After Execution R2= 8, R1 = 20H, No change in the content of R2
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Module _2_Full 11
Purpose Usage (example)
Immediate MOV r5,#23
MOV r2,#2
Register MOV r7,r5
Logical shift left by immediate MOV r7,r5,LSL #2
Logical shift left by register MOV r7,r5,LSL r2
Logical shift right by immediate MOV r7,r5,LSR #2
Logical shift right with register MOV r7,r5,LSR r2
Arithmetic shift right by immediate MOV r7,r5,ASR #2
Arithmetic shift right by register MOV r7,r5,ASR r2
Rotate right by immediate MOV r7,r5,ROR #2
Rotate right by register MOV r7,r5,ROR r2
Rotate right with extend MOV r7,r5,RRX
Module _2_Full 12
• MOV R0, R2, LSL #2 @ R0:=R2<<2
@ R2 unchanged
• Example: 0…0 0011 0000
Before R2 0x00000030 =0x00000030
After R0=0x000000C0 R2=0x00000030

Module _2_Full 13
MOV R1,R2,LSL #1 Assume R1=5, R2=8 0000 0000 0000 0000 0000 0000 0000 1000
After : R2=8, R1=16 0000 0000 0000 0000 0000 0000 0001 0000
MOV R1,R2,LSR #1 Assume R1=5, R2=8 0000 0000 0000 0000 0000 0000 0000 1000
After : R2=8, R1=4 0000 0000 0000 0000 0000 0000 0000 0100

MOV R1,R2,ROR #1 Assume R1=5, R2=90000 0000 0000 0000 0000 0000 0000 1001
After : R2=8, R1=80000004 1000 0000 0000 0000 0000 0000 0000 0100

MOV R1,R2,ROL #1 Assume R1=5, R2=9 0000 0000 0000 0000 0000 0000 0000 1001
After : R2=8, R1=00000012 0000 0000 0000 0000 0000 0000 0001 0010

MOV R1,R2,ASR #1 Assume R1=5, R2=80000009 1000 0000 0000 0000 0000 0000 0000 1001

After : R2=8, R1=C0000004 1100 0000 0000 0000 0000 0000 0000 0100
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• Before R2 0x00000030
• After R0=0x0000000C R2 Unchanged

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 ASR

• MOV R0, R2, ASR #2 @ R0:=R2>>2

• @ R2 unchanged
• Example: 1010 0…0 0011 0000
• Before R2 0xA0000030
• After R0=0xE800000C
• R2=0xA0000030

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 ROR

MOV R0, R2, ROR #2 @ R0:=R2 rotate,

@ R2 unchanged
Example: 0…0 0011 0001
Before R2 0x00000031
After R0=0x4000000C R2=0x00000031

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 RRX

• MOV R0, R2, RRX @ R0:=R2 rotate,

• @ R2 unchanged
• Example: 0…0 0011 0001
• After R0=0x80000018, C=1
R2=0x00000031

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Shifted register operands

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Shifted register operands

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 • RRX provides the value of the contents of a
register shifted right one bit. The old carry flag is
shifted into bit[31].
• If the S suffix is present, the old bit[lsb –bit or 0th ]
is placed in the carry flag.

MOV r7,r5,RRX Assume R7=5, 0111 0000 0000 0000 0000 0000 0000 1000
R5=0x70000008 1 1011 1000 0000 0000 0000 0000 0000 0100
Old carry is C i.e=1
After the operation: oxB8000004

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• MOVS: this instruction copies the content from source
to destination register and updates Status register.
• MOVS r0, r1, LSL #1:
– This instruction shifts R1 left side by one place and then it
copies to R0. After the execution status register CPSR will
be updated.
Instruction Usage Post Condition
MOV r1, #0x80000004 R1=0x80000004
Before c 1000 0000 0000 0000 0000 0000 0000 0100
MOV r0 ,#0x00000000 After C 0000 0000 0000 0000 0000 0000 0000 1000
MOVS r0, r1, LSL #1
R0=0x00000080
cpsr= nzcvqiFt_USER
CPSR= nzCvqiFt_USER
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 Conditional instructions
• It is usually used after CMP instructions
• The CMP instruction updates cpsr
• MOV conditional instruction executes based on flags
• MOVEQ R0,R1
– R1 is moved to RO only if Z is set.
• usage :
– CMP r0,r1 ; compares ro and r1 sets flag accordingly.
– MOVEQ r0,r1 ; updates r0=r1 if Z is set.

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 Arithmetic Instructions
• The arithmetic instructions implement
addition and subtraction of 32-bit signed and
unsigned values.

N is the result of the shifter operation

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Instruction Usage Space for Answer
Pre conditions: Note that after the execution, cpsr is unaltered because the instruction
r1=0xF0000000 are not suffixed with S like ADDS
R2=0x00000005
ADD r0,r1,r2 R1=0xF0000000, R2=0x00000005, R0=0xF0000005
ADD
R0r1+r2
ADC r0,r1,r2 R1=0xF0000000 ,R2=0x00000005, R0=0xF0000006
ADC
cpsr = nzcvqiFt_USER
r0 r1+r2+carry
SUB r0,r1,r2 R1=0xF0000000, R2=0x00000005,R0=0xEFFFFFFB
SUB
R0r1-r2

SBC r0,r1,r2 R1=0xF0000000, R2=0x00000005, R0=0xEFFFFFFA

SBC
cpsr = nzCvqiFt_USER
R0r1-r2-carry
RSB r0,r2,r1 R1=0xF0000000 R0=0x10000000
RSB
R0=r1-r2
RSC r0,r2,r1 R1=0xF0000000, R2=0x00000005, R0=0x10000004
RSC
cpsr = nzCvqiFt_USER
R0r2-r1-carry

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 Using the Barrel Shifter with Arithmetic Instructions
Instruction Post condition
MOV r0,#0xF0000000 R0= 0xF0000000 R1=0x00000005
MOV r1,#0x00000005 R0=0x0000000F
ADD r0, r1, r1, LSL #1
MOV r0,#0xF0000000 R0 = 0xF0000000 R1=0x70000005
MOV r1,#0x70000005 CPSR=nzcvqiFt_USER
ADDS r0, r1, r1, LSL #1 R0=0x5000000f CPSR=nzCvqiFt_USER
MOV r0,#0xF0000000 R0 = 0xF0000000 R1=0x70000005
MOV r1,#0x70000005 CPSR=nzCvqiFt_USER (R1+1+(R1<<1)

ADCS r0, r1, r1, LSL #1 R0=0x50000010 CPSR=nzCvqiFt_USER

MOV r0,#0xF0000000 R0= 0x5000000f CPSR=nzCvqiFt_USER
SUBS r0, r0, #1
cpsr = nzcvqiFt_USER
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 Logical Instructions
Logical instructions perform bitwise logical
operations on the two source registers
Syntax: <instruction>{<cond>}{S} Rd,Rn,N

Instruction Explanation

ORR r0,r1,r2 Logical OR between registers R1 and R2, Result in R0 i.e r0= (r1 |r2)

BIC r0, r1, r2 Register r0 contains a binary pattern where every binary 1 in r2
clears a corresponding bit location in r1. r0= (r1 & ~r2)
AND r0,r1,r2 Logical AND between registers R1 and R2, Result in R0. r0= (r1 & r2)

EOR r0, r1, r2 Logical XOR between registers R1 and R2, Result in R0. r0= (r1 ^r2)

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Module _2_Full 28
 Logical Instructions
MOV R1 ,# 0X00004506
MOV R2 ,# 0X00000045
ORR R0,R1,R2 ;R0= 0X00004545
BIC R0, R1, R2 ;R0= 0X00004500
ANDS R0,R1,R2 ;R0= 0X00000000 CPSR: Z
EOR R0, R1, R2 ;R0= 0X00004545
[BIC:
R1: 0100010100000110

R2: 0000000001000101 * R0: 0100010100000000

~R2: 1111111110111010

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 Comparison Instructions
• The comparison instructions are used to
compare or test a register with a 32-bit value.
• These instructions update the cpsr flag bits
after the operation and but do not affect other
registers.
• Syntax: <instruction>{<cond>} Rn, N
• In these instruction, S suffix is not necessary ,
because the instruction itself updates flags.

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Instruction Explanation

CMP R0, R1 CMP comparison instruction. The CMP is effectively a subtract instruction
with the result discarded. After execution the z flag changes to 1 or an
uppercase Z if result is zero. This change indicates equality. (flags set as a
result of Rn – N).
TEQ R0, R1 Test for equality of two 32-bit values, flags set as a result of Rn ∧ N TEQ is
logical exclusive OR operation.
TST R0,R1 TST instruction is a logical AND operation. flags set as a result of Rn & N.
CMN R0,R1 compare negated, flags set as a result of Rn + N.

MOV R0 ,# 6 ; R0=6
MOV R1 ,# 9 ; R1=9
CMP R0,R1 ; Nzcv 1001 == 0110 ? Negative
CMP R0,R0 ; nZCv 0110==0110 ? Equal, zero flag
CMP R1,R0 ; nzCv 0110 ==1001 ? Not equal, Greater
CMN R0,R1 ; nzcv R0 and ~R1➔ 0110 and 0110
TEQ R0,R1 ; nzcv XOR( 0001001, 000110)
TST R0,R1 ; nZcv Module _2_Full00
AND(0001001,000110) all zero i.e Z 31
 first internals portion
Multiply Instructions
• The multiply instructions multiply the contents of a pair of registers
and, depending upon the instruction, accumulate the results in with
another register.
Instruction Purpose Syntax Operation

MLA Multiply and Accumulate MLA{<cond>}{S} Rd,Rm,Rs,Rn Rd=(Rm*Rs)+Rn

MUL Multiply MLA{<cond>}{S} Rd,Rm,Rs Rd=Rm*Rs

SMULL Signed Multiply Long SMULL<{<cond>{S} RdLo,RdHI,Rm,Rs [RdHiRdLo= Rm*Rs

UMULL Unsigned Multiply Long UMULL<{<cond>{S} RdLo,RdHI,Rm,Rs [RdHiRdLo= Rm*Rs

SMLAL Signed multiply Accumulate Long SMLAL<{<cond>{S}}RdLo,RdHI,Rm,Rs [RdHiRdLo]= [RdHiRdLo]+Rm*Rs

UMLAL Un Signed Multiply Accumulate Long UMLAL<{<cond>{S} RdLo,RdHI,Rm,Rs [RdHiRdLo]= [RdHiRdLo]+Rm*Rs

The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL) produce a 64-bit result.
The result is too large to fit a single 32-bit register so the result is placed in two registers labelled
RdLo and RdHi.
Before: Before:
R0=0x00000000 MUL R0,R1, R2 R0= R1*R2=0x00000004
R1=0x00000002 MLA R0,R1, R2, R3 R0=R1*R2+R3=0x00000008
R2=0x00000002 UMULL R0,R1, R2, R3 R1R0= R2*R3=0x00000008
R3=0x00000004 UMLAL R0,R1, R2, R3 R1R0= R1R0+R2*R3
R4=0x00000004
Module _2_Full R1R0=00000000 00000008 32
 Branch instruction
• A Branch instruction changes the flow of
execution or is used to call a routine.
• The address label is stored in the instruction as a
signed pc-relative offset
• Different types of branch instructions are
• B
• BL
• BX
• BLX

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 Branch Instructions
Instruction/ Purpose Explanation Working
Syntax
B It is unconditional jump instruction, Pc=label, unconditional
Branch to transfer control target jump
instruction

B<cond>label This is conditional branch

instruction
BL The Branch with Link, or BL, Pc=label, lr= address of
Branch with Link instruction is similar to the B next instruction after the
BL<cond>label instruction but overwrites the link BL
register lr with a return address.
It performs a subroutine call.
BX To return from a subroutine to Pc=Rm, 0xFFFFFFFE, T=Rm
Branch exchange calling part, the content of link & 1
BX<cond> Rm register is copied to the pc.
BLX Pc=lable, T=1
Branch exchange with Pc=Rm, 0xFFFFFFFE, T=Rm
link &1
Module _2_Full lr= address of next34
BLX<cond>label |Rm
instruction after the BLX
 Branch Instruction :sample program
;to find factorial of a number (data area is ignored)
AREA FACT_C, CODE, READONLY
ENTRY
START LDR R1,#5 ; to find fact of 5
BL FACT_SUB ; call subroutine pc-label
STOP B STOP ; call using B , backward

FACT_SUB MOV R0,#1

LOOP CMP R1, #0
BEQ LAST ; conditional branch , Forward
MUL R0,R1,R0
SUB R1,R1,#1
B LOOP ; unconditional branch , backward
LAST BX LR ; pc=lr to return to calling part
END

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 Load-Store Instructions
• Load-store instructions transfer data between
memory and processor registers.
• There are three types of load-store instructions:
– Single-register transfer,
– multiple-register transfer,
– swap

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 Loading constants using LDR and ADR
LDR instruction with a pc-relative address to read the constant from a literal pool.
ADR can only be used to load address literal which is from same segment.

Instruction Syntax Meaning Operation

LDR LDR Rd, =constant load constant pseudo instruction. Rd➔32-bit constant
This writes a 32-bit constant to a
register. It defaults to a memory
read
ADR ADR Rd, label load address pseudo instruction Rd➔32-bit relative
writes a relative address into a address
register, which will be encoded
using a pc-relative expression

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 Factorial
AREA FACT_C, CODE, READONLY
ENTRY
START ADR R4,N ; loads address of N using ADR
LDR R1,[R4] ; similar to
LDR R1,=N
LDR R5,=FACT ; loads address of Fact using LDS
LDR R0,=1 ; loads constants 1 using LDR
LOOP CMP R1, #0
BEQ LAST ; multiply and reduce, continue if not 0
MUL R0,R1,R0
SUB R1,R1,#1
B LOOP
LAST STR R0,[R5] ; store the result
STOP B STOP
N DCD 0x05 ; read only data
AREA FACT_D, DATA, READWRITE
FACT DCD 0X0 ; read write data area
END
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 Single-Register Transfer
These instructions are used for moving a single data item in and out of a register
The data types supported are signed and unsigned words (32-bit), half words (16-bit),
and bytes.

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 LDR and STR
• LDR and STR instructions can load and store data on a boundary alignment
that is the same as the data type size being loaded or stored.
• LDR can only load 32-bit words on a memory address that is a multiple of four
bytes—0, 4, 8, and so on
• LDR loads a word from the address stored in register and places it into register
STR goes the other way by storing the contents of register to the address
contained in register.
• Register which holds address is called is called the base address register.
AREA Ex, CODE, READONLY R1= 0x00000010
ENTRY R2= 0x00000020
start [0x00000010]=0x10
MOV r1,#0x00000010 [0x00000020]=0x30
MOV r2,#0x00000020

LDR r0, [r1] ; loads 32-bit R0 [0x00000010] R0= 0x10

STR r0, [r2] ; stores 32-bit [0x00000020]r0
stop B stop [0x00000020]=0x10
END
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Single-Register Load-Store Addressing Modes
• The ARM instruction set provides different modes for
addressing memory: Pre index with write back, Pre index, Post index

• Pre index with write back calculates an address from a base register plus address
offset and then updates that address base register with the new address.
• The pre index offset is same as the pre index with write back but does not
update the address base register.
• Post index only updates the address base register after the address is used

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Module _2_Full 42
• A signed offset or register is denoted by “+/−”, identifying that it is either a
positive or negative offset from the base address register Rn. The base address
register is a pointer to a byte in memory, and the offset specifies a number of
bytes.
• In Register ,the address is calculated using the base address register and a
specific register’s contents.
• In Immediate , the address is calculated using the base address register and a
12-bit offset encoded in the instruction
• Scaled register address is calculated using the base address register and a barrel
shift operation.
• Pre-index with writeb ack calculates an address from a base register plus
address offset and then updates that address base register with the new
address
• The pre-index offset is the same as the pre-index with write-back but does not
update the address base register.

Module _2_Full 43
 LDR example
Instructions After execution
LDR r0, [r1, #4]! r0 = 0x02020202
Pre-index with write-back r1 = 0x00009000
Assume:r0 = 0x00000000,r1 = 0x00090000 r0= [r1+4]=[0x000090000+4] 0x02020202
mem32[0x00009000]=0x01010101 R1r1+4=0x00009004
mem32[0x00009004]=0x02020202 base register does change. i.e write back
LDR r0, [r1, #4] r0 = 0x02020202
Pre-index r1 = 0x00090000
Assume: r0 = 0x00000000,r1 = 0x00090000 r0= r1+4=0x00009004= 0x02020202
mem32[0x00009000]=0x01010101 r1=r1
mem32[0x00009004]=0x02020202 base register does not change., no write back
LDR r0, [r1], #4 r0 = 0x01010101
Post-index r1 = 0x00009000
Assume: r0 = 0x00000000, r1 = 0x00090000 R0[r1] = 0x01010101
mem32[0x00009000]= 0x01010101 R1=r1+4= 0x00009004
mem32[0x00009004]= 0x02020202 After operation R1 updates
Module _2_Full 44
 STR example
Instructions After execution
STR r0, [r1, #4]! r0 = 0x00008000, r1 = 0x00009004
Pre-index with write-back [r1+4]Ro
Assume: r0 = 0x00008000,r1 = 0x00090000 [0x00009004]  0x00008000
r1=r1+4=0x00009004+4=0x00009004 R1 updates
STR r0, [r1, #4] r0 = 0x00008000, r1 = 0x00090000
Pre-index [r0]= [r1+4]
Assume: r0 = 0x00008000,r1 = 0x00090000 =[0x00009000+4]=[ 0x00009004]= 0x00008000
r1=r1, no change in r1
STR r0, [r1], #4 r0 = 0x01010101
Post-index r1 = 0x00009004
Assume: r0 = 0x00008000, r1 = 0x00090000 [r1]=r0 i.e [0x90000]= 0x00008000
[r1]= [r1+4]= 0x00009004 after operation r1 updates

Module _2_Full 45
 Example, usage, working for LDR
Type of Addressing Instruction Ro Base register R1+
Preindex with writeback LDR r0,[r1,#0x4]! mem32[r1 + 0x4] 0x4
Preindex with writeback LDR r0,[r1,r2]! mem32[r1+r2] r2
Preindex with writeback LDR r0,[r1,r2,LSR#0x4]! mem32[r1 + (r2 LSR 0x4)] R1=(r2 LSR 0x4)
Preindex LDR r0,[r1,#0x4] mem32[r1 + 0x4] No change
Postindex LDR r0,[r1,r2] mem32[r1 + r2] No change
Postindex LDR r0,[r1,r2,LSR #0x4] mem32[r1-(r2 LSR 0x4)] No change
Postindex LDR r0,[r1],#0x4 mem32[r1] 0x4
Postindex LDR r0,[r1],r2 mem32[r1] r2
Postindex LDR r0,[r1],r2,LSR #0x4 mem32[r1] (r2 LSR 0x4)

Module _2_Full 46
 Multiple-Register Transfer
• Load and Store instructions can transfer
multiple registers between memory and the
processor in a single instructions
• Transfer occurs from base register Rn pointing
into memory.

STORE multiple Instructions are: STMIA,STMIB,STMDA,STMDB

LOAD multiple Instructions are: LDMDB,LDMDA,LDMIB,LDMIA
Module _2_Full 47
A: Ascending D: Descending
40000000 40000018

40000004 40000014

40000008 40000010

4000000C 4000000C

40000010 40000008

40000014 40000004

40000018 40000000

Module _2_Full 48
IA Data LDMIA LDMIA R0!, {R1-R3}
40000000 0x11111111 40000000 0x11111111
Before:
40000004 0x22222222 40000004 0x22222222 R0:40000000
40000008 0x33333333 40000008 0x33333333 After:
R0:40000000C
4000000C 0x44444444 4000000C 0x44444444 R1:0x11111111
R2:0x22222222
40000010 0x55555555 40000010 0x55555555
R3:0x33333333
40000014 0x66666666 40000014 0x66666666
40000018 0x77777777 40000018 0x77777777

Module _2_Full 49
 Working of LDMIA: LDMIA ro!,[r1-r3]

Before execution After Execution LDMIA ro!,[r1-r3]

Mem32[0x80010]=0x01 R1[R0] R0=R0+4 ,
Mem32[0x80014]=0x02 R2[R0+4], R0=R0+4
mem32[0x80018]=0x03 R3[R0+8] R0=R0+4
R0=0x00080010,
R1=0x00000000, R0=R0+8
R2=0x00000000, R1=0x0000001 R2=0x0000002,R3=0x0000003,
R3=0x00000000 R0=0x000001c Increment after

Module _2_Full 50
IA Data LDMIB LDMIB R0!, {R1-R3}
40000000 0x11111111 40000000 0x11111111
Before:
40000004 0x22222222 40000004 0x22222222 R0: 40000000
40000008 0x33333333 40000008 0x33333333 After:
R0:40000000C
4000000C 0x44444444 4000000C 0x44444444 R1:0x22222222
R2:0x33333333
40000010 0x55555555 40000010 0x55555555
R3:0x44444444
40000014 0x66666666 40000014 0x66666666
40000018 0x77777777 40000018 0x77777777

Module _2_Full 51
 Working of LDMIB: RO!,[R1-R3] ;

Before execution After Execution LDMIB ro!,[r1-r3]

Mem32[0x80010]=0x01, R0=R0+4
Mem32[0x80014]=0x02, R1[R0] ,
mem32[0x80018]=0x03, R2[R0+4],
Mem32[0x8001c]=0x04 R3[R0+8]
R0=0x0008010 , R0=R0+12
R1=0x0000000 R1=0x0000002 R2=0x0000003,
R2=0x0000000,,R3=0x0000000 Module _2_FullR3=0x0000004, R0=0x000001c 52
DA Data LDMDA LDMIA R0, {R1-R3}
40000018 0x11111111 40000018 0x11111111
Before:
40000014 0x22222222 40000014 0x22222222 R0: 40000000
40000010 0x33333333 40000010 0x33333333 After:
R0:40000000C
4000000C 0x44444444 4000000C 0x44444444 R1:0x11111111
R2:0x22222222
40000008 0x55555555 40000008 0x55555555
R3:0x33333333
40000004 0x66666666 40000004 0x66666666
40000000 0x77777777 40000000 0x77777777

Module _2_Full 53
Working of LDMDA: LDMDA RO!,[R1-R3]

Before execution After Execution LDMDA ro!,[r1-r3]

Mem32[0x80020]=0x05, R3[R0], R2[R0-4],
Mem32[0x8001C]=0x04, R1[R0-8],
Mem32[0x80018]=0x03 R0=R0-0c
R0=0x00080020,R1=0x0000000 , R3=0x0000005 , R2=0x00000004,
R2=0x00000000 ,R3=0x0000000 R1=0x00000003,R0=0x0000014
Module _2_Full 54
DB Data LDMDB LDMIA R0, {R1-R3}
40000018 0x11111111 40000018 0x11111111
Before:
40000014 0x22222222 40000014 0x22222222 Ro: 40000000
40000010 0x33333333 40000010 0x33333333 After:
R0:40000000C
4000000C 0x44444444 4000000C 0x44444444 R1:0x22222222
R2:0x33333333
40000008 0x55555555 40000008 0x55555555
R3:0x44444444
40000004 0x66666666 40000004 0x66666666
40000000 0x77777777 40000000 0x77777777

Module _2_Full 55
 LDMDB

Before execution After Execution LDMDB ro!,[r1-r3]

Mem32[0x8001C]=0x04, RoRo-4,
Mem32[0x80018]=0x03, R3[R0], R2[R0-4], R1[R0-8],
Mem32[0x80014]=0x02 R0=R0-0c
R0=0x00080020, R3=0x0000005 R2=0x0000004,
R1=0x0000000 , R1=0x0000003, R0=0x0000014
R2=0x0000000
,R3=0x0000000 Module _2_Full 56
 Pre index writeback

After the execution

To copy 3 LDMIA ro!,[r1-r3]
R0
66 77 88 88 R1=66
0x1C R2=77
0x10 0x14 0x18 0x1C
R3=88
To copy 3 LDMIB ro!,[r1-r3]
R0 66 77 88 99 R1=77
0x14 0x1C 0x1C R2=88
0x10 0x18
R3=99

To copy 3 LDMDA ro!,[r1-r3]

R1=99
66 77 88 99 R0
0x10 R2=88
0x10 0x14 0x18 0x1C R3=77

To copy 3 LDMDB ro!,[r1-r3]

66 77 88 99 R1=88
0x10 R2=77
0x10 0x14 0x18 0x1C R3=66
Module _2_Full 57
•
SWAP instruction
The SWAP instruction is a special case of a load –store instruction.
• It swaps the contents of memory with the contents of a register.
• Swap instruction is important for implementing semaphores and
mutual exclusion in an operating system.
Instruction Explanation Usage Working
SWP Swap word between memory SWP Rd,Rm,[Rn] T= mem32[Rn],,
and a register Mem32[Rn]=Rm,, Rd=T
SWPB Swap a byte between memory SWPB Rd,Rm,[Rn] T= mem8[Rn], Mem8[Rn]=Rm
and a register Rd=T
Example

Instruction Explanation Before After

SWP r0,r1,[r2] Swap word between memory Mem32[0x9000]=0x12345678 R0=0x12345678
and a register R0=0x00000000 Mem32[0x9000]= 0x11112222
R0= mem32[R2] R1=0x11112222 R1=0x11112222
Mem32[R2]=R1 R2=0x00009000 R2=0x00009000

Module _2_Full 58
Block transfer
Mov R9,#0x10000000 ; start of Source block
Mov R10,#0x20000000 ; start of destination block
Mov R11,#0x10000020 ; end of source block
Loop LDMIA r9!, {r0-r7} ; load 8 words of data from src
STMIA r10!, {r0-r7} ; store 8 words of data in dest
CMP r9, r11 ; compare src index with end of src block
BNE loop

0x10000000=R9 0x00000011➔R0 0x20000000=R10 0x00000099R0

0x10000004 0x00000022➔R1 0x20000004 0x00000088R1
0x10000008 0x00000033➔R2 0x20000008 0x00000077R2
0x1000000c 0x00000044➔R3 0x2000000c 0x00000066R3
0x10000010 0x00000055➔R4 0x20000010 0x00000055R4
0x10000014 0x00000066➔R5 0x20000014 0x00000044R5
0x10000018 0x00000077➔R6 0x20000018 0x00000033R6
0x1000001c 0x00000088➔R7 0x2000001c 0x00000022R7
0x10000020=R11 0x00000099 0x20000020 0x00000011

Source Memory Destination Memory

Module _2_Full 59
 Stack operations
• The ARM architecture use load-store multiple instructions to carry out stack operations.
• For push load instruction and for pop store instruction
• The direction of a stack must be set before the stack operation
• The direction can be upward growth or downward in memory.
• A stack is either
– ascending (A- grow upwards-towards higher memory locations)
– descending (D-grow downwards-towards lower memory locations).
• When full stack (F) is used, the sp points to an address that is last used.
• When empty (E) is used, the sp points to an address that is unused, i.e. after the last item on
the stack.
• Stack Addressing modes are: FA- Full Ascending, FD- Full Descending, EA-Empty Ascending, ED-Empty
Descending.

Address POP LDM PUSH STM

Mode Instruction instruction Instruction instruction
(load) (store)
FA Full Ascending LDMFA LDMDA STMFA STMIB
FD Full Descending LDMFD LDMIA STMFD STMDB
EA Empty Ascending LDMEA LDMDB STMEA STMIA
Module _2_Full 60
ED Empty Descending LDMD LDMIB STMED STMDA
 SP
FA: Ascending Stack FA: Descending
40000000 0x11111111 SP 40000018 0x11111111

40000004 40000014

40000008 40000010

4000000C 4000000C

40000010 40000008

Ascending
SP pointing to last used memory

EA: Ascending EA: Descending

40000000 0x11111111 40000018 0x11111111

40000004 SP 40000014
SP
40000008 40000010

4000000C 4000000C

40000010 40000008
Ascending Module _2_Full 61
SP pointing to next unused memory
 PUSH demo: STMFD(➔ STMDB)
Before: After:
R1=0x02 R1=0x03
R4=0x03 R4=0x02
Sp=0x80014 Sp=0x8000c

STMFD Sp!, {r1,r4}

Full stack i.e SP points to last used location.Stack grows from higher to lower- downward
SP decremented first to point to next unused location, then registers content are loaded
The equivalent instruction is STMDB

PUSH demo: STMED(➔ STMDA)

Before:
R1=0x02 After:
R4=0x03 R1=0x03
Sp=0x80010 R4=0x02
Sp=0x80008
STMED Sp!, {r1,r4}
First register contents are stored and then SP decremented to point to next unused location
The equivalent instruction is STMDA
Module _2_Full 62
 PUSH demo: STMFA(➔ STMIB)
Before: After :
R1=0x02 R1=0x02
R4=0x03 R4=0x03
Sp=0x80010 Sp=0x80018
STMFA Sp!, {r1,r4}
SP incremented first to point to next unused location, then registers content are loaded
The equivalent instruction is STMIB
PUSH demo: STMEA(➔ STMIA)
Before:
R1=0x02
R4=0x03
Sp=0x80014

STMEA Sp!, {r1,r4}

First register content are stored and then SP incremented to point to next unused
location. The equivalent instruction is STMIA

Module _2_Full 63
 Software Interrupt Instructions
• A software interrupt instruction SWI causes software interrupt
exception, which provides a mechanism for application to call
operation system routines.
• Syntax: SWI SWI_Number
Instruction Purpose Working
SWI Software Interrupt lr_svc=address of instruction following the SWI
spsr_svc=cpsr
pc=vector+0x8
cpsr mode=SVC
cpsr I=1 (mask IRQ interrupts)

Module _2_Full 64
 Program Status Register Instructions
Instruction Purpose Working Type
MRS Copy program status register to a Rd=psr MRS {<condition} Rd, <cpsr
general purpose register |spsr>
MSR Move a general purpose register to Psr[field]=Rm MSR {<condition} <cpsr
a program status register |spsr}_<fields>,Rm
MSR Move an immediate value to a Psr[field]=#imm MSR {<condition} <cpsr
program status register |spsr}_<fields>,#immediate

Before: cpsr=nzcvqIFt_svc
MRS r1,cpsr
BIC r1,r1,#0x80
MSR cpsr_c,r1
After: cpsr=nzcvqiFt_SVC
Above set of instructions will store cpsr Module
in R1 _2_Full
and negates n flag. 65
 Loading Constants
• There is no ARM instruction to move a 32-bit constant into
a register.
• To aid programming there are two pseudo instructions are
used to move a 32-bit value into a register.

Module _2_Full 66
 Example
AREA Program, CODE, READONLY
ENTRY
Main LDR R0,=Num1 ; loads address of Num1 to R0
ADR R1,stop ; loads address of stop to R1 –relative to PC
stop B stop
AREA Data1,DATA, READONLY
Num1 DCW 0x706F
ALIGN
END

Module _2_Full 67
 (Important)
To copy a word data to another location
AREA LARGEST , CODE, READONLY
ENTRY
START
LDR R1,=VALUE1 ; loads the address of first varaibel
LDR R2,[R1] ;get its data
LDR R4,=RESULT ; loads address of destination
STR R2,[R4] ; stores the data at destination
VALUE1 DCD 0X44444444 ; ; source data
AREA DATA2,DATA,READWRITE
RESULT DCD 0X0 ; data word destination
END

Before execution After execution

VALUE1: 0x44444444 VALUE1: 0x44444444
RESULT: 0x0 RESULT: 0x44444444
Module _2_Full 68
To copy string to another location
AREA StrCopy, CODE, READONLY
ENTRY
start LDR r1, =srcstr ; Pointer to first string
LDR r0, =dststr ; Pointer to second string
BL strcopy ; Call subroutine to do copy
stop B stop
strcopy
LDRB r2, [r1],#1 ; Load byte and update address
STRB r2, [r0],#1 ; Store byte and update address
CMP r2, #0 ; Check for zero terminator-\0
BNE strcopy
BX LR ; Return to main
srcstr DCB "First string - source",0
AREA Strings, DATA, READWRITE
dststr DCB "Second string - destination",0
END
Before After
srcstr ➔ "First string - source",0 srcstr ➔ "First string - source",0
dststr ➔"Second string - destination",0 dststr ➔"Second string - destination",069
Module _2_Full
 Write an ARM7 program to find the
bigger of two given numbers & store
AREA StrCopy, CODE, READONLY
ENTRY
start LDR r0, =N1 ; Pointer to first string
LDR r1, =N2 ; Pointer to second string
LDR R2,=BIGG
LDR R3,[R0]
LDR R4,[R1] Before execution
CMP R3,R4 N1 ➔ 19
MOVGE r3, r4 N2 ➔ 20
STRB R4,[R2] BIGG ➔ 0
STOP B STOP
N1 DCB 19 After execution
N2 dcb 20 N1 ➔ 19
AREA Strings, DATA, READWRITE N2 ➔ 20
BIGG DCB 0x0 BIGG ➔ 20
END

Module _2_Full 70
Write an ARM7 program for transferring a block
of data word from one block to another
AREA StrCopy, CODE, READONLY
ENTRY
start LDR r1, =src ; Pointer to first string
LDR r0, =dst ; Pointer to second string
LDR r3,=n
LDR R4,[R3]

copy LDRB r2, [r1],#1 ; Load byte and update address

STRB r2, [r0],#1 ; Store byte and update address
SUB R4,R4,#1
CMP r4, #0 ; Check for zero terminator
BNE copy
stop B stop
src DCB 12,45,67,65,54, Before-src,dst After-srs,dst
n DCB 05 12 0 12 12
AREA Strings, DATA, READWRITE 45
dst DCB 0x0 45 45
END 67
67 67
65
65 65
54 Module _2_Full 71
54 54
 Write an ARM7 program to generate
Fibonacci series
AREA fibc, CODE, READONLY
ENTRY
start LDR r0, =0 ;load first no of fib series 0
LDR r1, =1 ; load second no. of fib. 1
LDR r3,=0
LDR r4,=fib ; storage for fib nos.

NEXT ADD R2,R0,R1 ; add two fib nos.

STR R2,[R4],#4 ; store the generated no. in fib array-storage
MOV R0,R1 ; reassign previous 2nd no as new first and result as second number
MOV R1,R2
ADD R3,R3,#1 ; increment counter
CMP R3, #10 ; if not generated 10 proceed..
BNE NEXT
STOP B STOP
AREA fibd, DATA, READWRITE
fib DCB 0x0

Module _2_Full 72
 Salient features of ARM instruction set
• All instructions are 32 bits long.
• Most instructions execute in a single cycle.
• Most instructions can be conditionally executed.
• A load/store architecture – Data processing instructions act only on registers
• Three operand format: opcode Rd, Rs, N
• Combined ALU and shifter for high speed bit manipulation
• Specific memory access instructions with powerful auto ‐indexing addressing modes.
• 32 bit and 8 bit data types – and also 16 bit data types on ARM Architecture v4.
• Flexible multiple register load and store instructions
• Instruction set extension via coprocessors ƒVery dense 16 ‐bit compressed instruction
set (Thumb)

Module _2_Full 73
 Explain briefly co-processor
instructions of ARM processor
• Coprocessor instructions are used to extend the instruction set.
• A coprocessor can either provide additional computation capability or be used
to control the memory subsystem including caches and memory management.
• CDP{<cond>} cp, opcode1, Cd, Cn {, opcode2}
• <MRC|MCR>{<cond>} cp, opcode1, Rd, Cn, Cm {, opcode2}
• <LDC|STC>{<cond>} cp, Cd, addressing
• CDP: coprocessor data processing—perform an operation in a coprocessor
• MRC and MCR: coprocessor register transfer—move data to/from coprocessor
registers
• Ex: MRC p15, 0, r10, c0, c0, 0
– transferring the contents of CP15 register c0 to register r10
– MRC cp, opcode1, Rd, Cn, Cm {, opcode2}
• LDC and STC: coprocessor memory transfer—load and store blocks of memory
to/from a coprocessor
Module _2_Full 74
• Write a program to display message Hello
world using ARM 7 instruction
• Develop an ALP to find factorial of given
number using LOOKUP table and ARM
instruction set
• Write ARM assembly language program to add
two 32-bit numbers

Module _2_Full 75
• Write a program to display message "Hello
world" using ARM7 instructions
AREA LARGEST , CODE, READONLY
ENTRY
START LDR R0,= STRING
SWI 0x2
SWI 0X11 ; to TERMINATE
STRING DCB "HELLO WORLD\N"
END
Module _2_Full 76
 I/O operation using SWI

• swi 0x00 : Display Character on Stdout r0: the character

• Example:
MOV R0,#’A
SWI 0x00
• swi 0x02 : Display String on Stdout r0: address of a null
terminated ASCII string
• Example:
ldr r0,=String
swi 0x02
String: .asciz "Hello world\n"
swi 0x11 ;Halt execution
Module _2_Full 77