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10 - Io

This document discusses input and output (I/O) techniques in computer systems. It describes how I/O devices are slower than the CPU and memory and require I/O modules to interface with them. The three main I/O techniques discussed are programmed I/O using polling, interrupt-driven I/O, and direct memory access (DMA). Programmed I/O wastes CPU time polling devices, while interrupt-driven I/O and DMA improve efficiency by allowing other processing when waiting for I/O. DMA specifically allows high-speed transfer of data between memory and I/O devices without using the CPU. Memory-mapped and isolated I/O addressing techniques are also summarized.

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Nadun Sasanga Kumarasinghe
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31 views21 pages

10 - Io

This document discusses input and output (I/O) techniques in computer systems. It describes how I/O devices are slower than the CPU and memory and require I/O modules to interface with them. The three main I/O techniques discussed are programmed I/O using polling, interrupt-driven I/O, and direct memory access (DMA). Programmed I/O wastes CPU time polling devices, while interrupt-driven I/O and DMA improve efficiency by allowing other processing when waiting for I/O. DMA specifically allows high-speed transfer of data between memory and I/O devices without using the CPU. Memory-mapped and isolated I/O addressing techniques are also summarized.

Uploaded by

Nadun Sasanga Kumarasinghe
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Input & Output

CS2053 Computer Architecture


Computer Science & Engineering
University of Moratuwa

Dr. Sulochana Sooriyaarachchi


Dr. Chathuranga Hettiarachchi
Acknowledgement: Dr. Dilum Bandara
Input & Output
Main
Memory

System Bus
CPU

I/O Devices

 Wide variety of peripherals


◼ Different volumes of data, in different formats, & different speeds
 All slower than CPU & RAM
 Controlled via I/O modules/controllers
◼ Interface to CPU & Memory
◼ Interface to 1 or more peripherals
2
External Devices
 Interact with humans
◼ Monitor, printer, keyboard, mouse
 Machine readable
◼ Monitoring & control
◼ e.g., process scheduling, CPU/casing temperature
monitoring, fan speed control
 Communication
◼ Network Interface Card (NIC)
◼ Modems
◼ Dongles – Bluetooth, Wi-Fi, 3G, 4G

3
Generic Model of I/O Module

Source: William Stallings, Computer Organization and Architecture, 8th Edition


I/O Module Functions
 Control & Timing
 CPU communication
 Device communication
 Data buffering
 Error detection

5
Source: http://lilt.ilstu.edu/cheri/itk254/sc/inputoutput/InputOutput_print.html
I/O Module Functions – Example

Source: http://lilt.ilstu.edu/cheri/itk254/sc/inputoutput/InputOutput_print.html
SweRVolfX

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SweRVolfX IO at low level

8
Input Output Techniques
 Programmed I/O
◼ Polling
 Interrupt driven I/O
 Direct Memory Access (DMA)

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Programmed I/O
 CPU has direct control over I/O
◼ Continuously sense status – Poll
◼ Read/write commands
◼ Transferring data
 CPU waits for I/O module to complete operation
 Wastes CPU time

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Addressing I/O Devices
 Under programmed I/O data transfer
is like memory access
◼ Use LOAD/STORE instructions
 Each device is given a unique
identifier
◼ Address[15:6]
 CPU commands contain identifier
(address)
 Registers within I/O controller are
identified by
◼ Address[5:2]
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I/O Mapping

Source: http://me-lrt.de/memory-map-port-isolated-input
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I/O Mapping (Cont.)
Memory Mapped I/O Isolated I/O
 Devices & memory share  Separate address spaces
same address space
 I/O looks just like memory  Need I/O or memory
read/write select lines
 No special commands for  Special commands for I/O
I/O ◼ Limited set
◼ Large selection of memory
access commands

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E.g. Memory mapped - GPIO
Three memory-mapped registers:
– Read Register: value read from pin
– Write Register: value to write to pin
– Enable Register: 1 = output, 0 = input

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Interrupt Driven I/O
 No repeated CPU checking of device
◼ No waiting
◼ CPU does its own work
 I/O module interrupts CPU when ready
 Steps
◼ CPU issues read command
◼ I/O module gets data from peripheral whilst CPU does
other work
◼ I/O module interrupts CPU
◼ CPU requests data
◼ I/O module transfers data
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Interrupt Processing (Cont.)

Source: William Stallings, Computer 16


Organization and Architecture, 8th Edition
Direct Memory Access (DMA)
 Programmed & interrupt driven I/O require active
CPU intervention
◼ Transfer rate is limited
◼ CPU is tied up in data transfer
 DMA is the answer
◼ Additional module (hardware) on bus
◼ DMA controller takes over from CPU for I/O
 Provide a way of bypassing CPU when transferring data
between memory & IO

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DMA (Cont.)
Memory
Memory

CPU CPU
DMA

IO
device IO
device

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3 Techniques for
Input of a Block of Data

Source: William Stallings, Computer


Organization and Architecture, 8th
Edition 19
Blocks of a Computer
Processor

Disk/DMA
controller

Disk Disk
DMA
Sy stem us

controller

Network
Interface
b
Main
memory

Printer K ey board

Figure 4.19. Use of DMA controllers in a computer system.

20
THANK YOU

21

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