National Computing Education Accreditation Council

NCEAC

NCEAC.FORM.001-D

COURSE OUTLINE

INSTITUTION University of Management & Technology, Lahore

PROGRAM (S) TO BE BS Computer Science
EVALUATED
Course Description:
Course Code CS2031
Course Title Digital Logic Design.
Credit Hours 3
Prerequisites by Applied Physics
Course(s) and
Topics
Assessment Quizzes 15%,
Instruments with Class Participation + Assignments. 10%,
Weights Midterm Exam: 25%,
(homework, Case Study/Project/Report Writing/Presentation: 15%,
quizzes, midterms, Final Exam: 35%
final, programming
assignments, lab
work, etc.)
Course Moderator Dr. Muhammad Adnan
URL (if any) Course: CS2031 - Digital Logic Design - Dr. Muhammad Adnan - V1 - OC (umt.edu.pk)
Textbook (or M. Morris Mano and Micheal D. Ciletti, “Digital Design with an introduction to the Verilog HDL
Laboratory Manual VHDL and System Verilog”, 6th Edition, Prentice Hall, Dec 5, 2018
for Laboratory ISBN-10: 9353062012, ISBN-13: 978-9353062019
Courses)

Reference Material

a) Morris Mano and Charles R. Kime, “Logic and Computer Design Fundamentals”,
Prentice Hall. Latest Edition
b) Tocci and Widmer, "Digital Systems: Principles and Applications". Prentice Hall. Latest
Edition

Course This course aims at the digital design process with respect to computer hardware and state-of-the-
Goals/Objectives art hardware design methodologies. The key aspects of this course are:
a) To perform the conversion among different number systems
b) Understand Boolean algebra and its basic properties to simplify Boolean functions
c) Optimization of simple logic using Karnaugh maps, and use of "don't care".
d) Familiarization with basic logic gates to demonstrate how to design, build and analyze
digital module with combinational (such as Adders, Subtractor, Multiplier, Comparator,
Encoders and Decoders, Multiplexers)
e) Understanding of basic sequential logic components: SR Latch, D Flip-Flop and their
usage in Synchronous Counters.
f) Learn basics of Shift Registers, PLA, PAL, RAM and Arithmetic-Logic Units (ALUs).

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NCEAC

NCEAC.FORM.001-D

Course Learning Outcomes (CLOs):

CLOs Description Domain & BT Level *

e Learning
Measurabl

Outcomes

CLO 1 Apply fundamental concepts of digital logic design C3 (Apply)

including logic gates, number systems & binary coded
systems
CLO 2 Perform Gate level minimization using Boolean algebra & C3 (Apply)
K-map.
CLO 3 Analyze sequential and combinational circuit. C4 (Analysis)

CLO 4 Design small-scale combinational and synchronous C6 (Synthesis)

sequential digital circuit.

* BT= Bloom’s Taxonomy, C=Cognitive domain, P=Psychomotor domain, A= Affective domain

Mapping of CLOs to Program Learning Outcomes (PLOs):

CLOs/PLOs CLO 1 CLO 2 CLO 3 CLO 4

PLO 1: Academic Education

PLO 2: Knowledge for Solving Computing Problems

PLO 3: Problem Analysis   

PLO 4: Design and Development of Solutions 

PLO 5: Modern Tool Usage

PLO 6: Individual and Teamwork

PLO 7: Communication

PLO 8: Computing Professionalism and Society

PLO 9: Ethics

PLO 10: Life Long Learning

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NCEAC.FORM.001-D

Tentative Course Plan

Week Topics Chapter Assessment CLOs
Number System, Operations and Codes
Introduction to Digital Logic Design, Digital and Analog
Lecture
1 Quantities, Binary Digits, Basic Logic Functions, Decimal, CLO1
Notes
Hexadecimal, Octal and Binary Numbers, Decimal-to-
Binary Conversion, Binary Arithmetic
Number System, Operations and Codes Lecture
2 Complements of Binary Numbers, Signed Numbers, Binary Notes CLO1
Quiz 1
Coded Decimal (BCD), Digital Codes Error, Codes
Logic Gates Lecture
3 The Inverter, AND Gate, OR Gate , NAND Gate, NOR Notes CLO1
Quiz 2
Gate, Exclusive-OR and Exclusive-NOR Gates
Boolean Algebra and Logic Simplification Lecture
Boolean Operations and Expressions, Laws and Rules of Notes
4 CLO1
Boolean Algebra, DeMorgan’s Theorems, Boolean Analysis
of Logic Circuits, Logic
Boolean Algebra and Logic Simplification Lecture
Simplification Using Boolean Algebra Standard and Notes
5 Quiz 3 CLO1
Canonical Forms of Boolean Expression, Boolean
Expressions and Truth Tables,
Boolean Algebra and Logic Simplification Lecture
6 The Karnaugh Map, Karnaugh Map SOP Minimization and Notes Assignment 1 CLO2
POS Minimization, Don’t Care Conditions
Combinational Logic Lecture
Design Procedure, Basic Combinational Logic Circuits, Notes
7 Implementing Combinational Logic, The Universal Property CLO3
of NAND and NOR gates, Combinational Logic Using
NAND and NOR Gates
Lecture
8 Mid –Term Midterm Exam
Notes
Functions of Combinational Logic Lecture
Code Conversion, Half and Full Adders, Parallel Binary Notes
9 Assignment 2 CLO4
Adders, Half and Full Subtractors, Parallel Binary
Subtractors
Functions of Combinational Logic Lecture
10 Quiz 4 CLO4
Half and Full Subtractors, Parallel Binary Subtractors Notes
Functions of Combinational Logic Lecture
Quiz 5
11 Decoders, Encoders, Multiplexers (Data Selectors) Notes CLO4
Demultiplexers
Latches, Flip-Flops, and Timers Lecture
Latches, Flip-Flops (RS, D type, JK), Triggering of Flip Notes
12 Quiz 6 CLO3
flops (Master Slave, Edge Triggered), Flip-Flop Operating
Characteristics, State reduction and assignment
13 Counters Lecture Assignment 3 CLO4
Finite State Machines, Asynchronous Counters, Notes
Synchronous Counters.

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Shift Registers Lecture

14 Registers, Shift Register Operations, Types of Shift Register, Notes CLO4
Bidirectional Shift Registers, Shift Register Counters
Data Storage Lecture
15 Notes CLO4
PLA, PAL, RAM, ROM and Flash memory.

16 Final Final Exam

Laboratory Project
Projects/Experiments Done
in the Course
Programming Assignments None
Done in the Course
Class Time Spent on (in 3 hours per week
credit hours)
Oral and Written Presentations
Communications

*-Tentative Mapping of CLOs to Direct Assessments

CLO Quiz-1 Quiz-2 Quiz- Quiz- Quiz-5 Quiz-6 Assign Assign Assign Projec Midter Final
3 4 1 2 3 t m
1   
2    
3    
4     

Instructor Name: Dr. Muhammad Adnan

Instructor Signature ____________________________