Please do not share these notes on apps like WhatsApp or Telegram.

The revenue we generate from the ads we show on our website and app
funds our services. The generated revenue helps us prepare new notes
and improve the quality of existing study materials, which are
available on our website and mobile app.

If you don't use our website and app directly, it will hurt our revenue,
and we might not be able to run the services and have to close them.
So, it is a humble request for all to stop sharing the study material we
provide on various apps. Please share the website's URL instead.
 STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)

Subject Name: VLSI Design Subject Code: EC701

Subject Notes
UNIT-IV

Structured Digital Circuits and Systems:

Random Logic and Structured Logic Forms, Register Storage Circuits, Quasi Static Register Cells, A Static
Register Cell, Micro coded Controllers, Microprocessor Design, Systolic Arrays, Bit-Serial Processing Elements,
Algotronix .

Random logic forms:

Random logic is describing a particular style design of any digital circuit. Some IC circuit are placed within a layout in
much the same way that small scale chip are placed on wire wrap circuit board and then interconnected. The particular
types of small- scale logic functions may be needed at irregular places within a circuit, the circuit packages and their
interconnection wiring sometimes appear to have been randomly placed.
Random logic is a tag commonly used to describe digital circuits that lack regularity of circuit function, placement
and interconnection.
Advantages of random logic:
Efficient use of silicon. Fast operation.
Disadvantages:
Lengthy IC layout times. Difficulty of testing. Costly modification step

Structured Logic Forms:

Structure logic is term used to distinguish logic forms that do show reliability in their layout and interconnection.
Digital integrated circuits have been designed with highly structured layouts for many years. Most notable among
there are all forms of memory chips. Memory chips, such as the 1M-bit dynamic RAM from Texas Instruments are
composed of many identical memory cells and are naturally structured as regular arrays of these cells. Because of
the potential sales volume for many parts, considerable effort is expended in reducing the size of the basic memory
cell, causing memory chips to be among the densest of all IC’s.
Because of the complexity of many new chips, random logic design is no longer feasible for large chips.
Most new digital integrated circuits increasingly use structured logic forms such as PLA’s, micro program ROMs, gate
arrays and standard cells to displace random logic design.

Regularity factor
Regularity factor is defined as the ratio of the total number of transistors on the chip to the drawn transistors,
where total transistors includes all possible ROM and PLA transistor placements.
A design that requires a unique layout for a circuit element and then uses this circuit element n times without
change would exhibit a regularity factor of n.
A design with unique layout for each circuit component would exhibit a regularity factor of 1. For a given complexity of
design, a higher regularity factor normally indicates reduced design and layout costs.
Table 4.1: Regularity Factor for microprocessor
Chip name Numbered of devices Regularity Factor
8080 4600 1.1
8085 6200 3.1
8086 29000 4.4
68000 68000 12.1

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

1
 STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)

Register Storage Circuits:

1) Quasi Static Register Cells: Figure 4.1 shows a way to combine two inverters, two pass transistor and non
overlapping two phase clock to provide a quasi static register cell. Quasi-static register cell uses exactly the same
components as a two stage dynamic shift register and interconnected in a different way.
The output of a first inverter is connected directly to the input of a second invertors one pass transistor called the
input pas transistor, controls the input to the first inverter. The second pass transistor called the feedback transistor
controls a feedback path from the output of the input of the first inverter.
2

1. Load

D R

R’

Fig. 4.1 Quasi Static Binary storage cell

Operation: When a binary value is to be stored in the register cell, the input pass transistor is turned on and the
feedback transistor is turned off. This is accomplished through use of a load signal ANDed with clock phase φ1 to
control the gate of the pass transistor. φ2 is low so that the feedback path is broken at this time.
When the input pass transistor is turned on, any signal applied to D input of the register cell is passed to the gate of the
first inverter, resulting in the same logic value at the output R of the second inverter (after two successive inversions)
When the input pass transistor is turned off, the value at the input node of the first inverter is stored dynamically on
the parasitic capacitance of that node, The value at the output of the-second inverter is actively driven and is logically
equivalent to the stored value at the input of the first inverter.
During the φ2 clock phase the output of the second inverter is fed back to the input of the first inverter, thus
reinforcing its logic value. As long as this feedback condition is applied often enough, the quasi-static register cell will
maintain its stored value.
Quasi-static register cells were common in early microprocessors. For example, registers in the Motorola 6800 series
of microprocessors were composed of an extension of the basic quasi-static cell that permitted dual-port read and
write as shown in fig 4.2 . This cell, provides two gated load (write) signals on one clock phase, so the register can be
loaded from either of two buses. A feedback path to refresh the stored logic value is provided on the alternate clock
phase. The controller (not shown) that generates the write signals should logically AND them with φ1 to avoid conflict
with the feedback path that is controlled by φ2. The register output, taken from the center of the register cell, drives
a pull-down transistor. The output of this transistor is directed through pass transistors to one of two possible buses
providing dual-port read. This cell requires four control signals (each externally gated by clock phase), an alternate
clock signal φ2 to control the feedback path, two bus lines (each bus line is common to one input and one output
path), power, and ground.

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

2
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

Downloaded from www.rgpvnotes.in, whatsapp: 8989595022

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

 STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)
1) Memory Organization / MicroROM:
Figure 4.6 shows a typical memory organization for a microcoded controller consisting of a microROM and a
memory address register (MAR). While most semiconductor memory chips are organized with a wide address
bus and a narrow data bus (nine multiplexed address lines and one data line for most 256k DRAMs), the memory
(microROM) for a microcoded controller usually has a wide data bus relative to its address bus (perhaps 72 or more
data lines compared with 12 or fewer address lines). Most of these data lines are dedicated to driving control points
within the system. A few data lines are used to provide next- address information to the next-address
sequencer. The next-address sequencer uses this address information along with status inputs from the controlled
process to calculate the address of the next microinstruction.
A microROM organized as in Fig. 4.6 would contain almost 300k bits (212 x 72 = 294,912) of control information
and would consume a correspondingly large silicon area.

Micro ROM M
12 Address lines
4096 x 72 R

12 Next Address

60 Control lines

Registers / ALU / shifter/ buses

Fig .4.6 :Block diagram of MicroROM architecture

An alternative form for the microROM is shown in Fig. 4.7. This two-level microprogram memory consists of a
relatively small micro ROM driving a secondary memory called a nanoROM. This organization is based on two
reasonable assumptions. First, only a few of the 272 possible control word combinations of Fig. 4.6 are
necessary in a given system. Second, many of the control words that are necessary will be required repeatedly. If
fewer than 256 unique control words are necessary, for example, and the microprogram memory is organized
as shown in Fig. 4.7, only about 50k bits (212 x 8 + 28 x 72 = 51,200) of control memory are required. This reduction
in memory size is not free; the two-level microROM is slower than a single-level memory because a memory
access must traverse two memory units to produce data.

Nanoinstruction Microinstruction
8
ROM ROM

72 Control and address 12 Address

Fig .4.7 : Two level Microprogram memory

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

5
 STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)
2) Comparison Between PLA and Micro-programmed Forms of FMSs:
(1) A Micro-programmed control unit is more complex than the corresponding PLA FSM because of the next address
generation circuitry.
(2) A PLA FSM can be complied automatically once the state equation for the system are determine this is much
more difficult for a micro-programmed FSM.
(3) The PLA FSM is normally best for small, simple systems where minimum design time arid circuit area are required
because the peripheral circuitry for a micro-programmed FSM depends on the application and is thus not
automatically generated.
(4) The microprogram machine is usually more desirable for larger systems over the PLA FSM.

Microprocessor Design:
The evolution of microprocessors provides an interesting study in the development of structured logic forms.
The earliest microprocessors is the Intel 4004 and 8008 were born to counteract the high development costs for
custom large-scale integrated circuits.
As the complexity of microprocessor has increased, the design time and costs have also expanded. Development of
structured designs using regular logic forms has been required to allow the evolution of microprocessor data path. In
which, the data path consists of registers, shifter and ALU and the control unit consists of the micro ROM, MAR, next-
address sequences, IR and PC.
The data path for microprocessor usually formed with 8, 16 or 32 bit identical bit path. As a result of their identical bit
paths there is an inherent regularity within the data path for microprocessor. The control unit has varied structures
with most manufactures choosing microcoded or PLA controllers.

1) Data path description:

The data path is the place where the microprocessor executes operations such as addition, subtraction, shifts, rotates
and Boolean logical functions on data. The data path is also known as execution unit.
A typical n-bit data path structure consisting of a dual-port register array, a barrel shifter, an ALU, interconnection
buses and support circuitry. The block diagram of Microprocessor data path is shown in Fig4.8.
Select A Select B Timing Shift constant ALU operation

Register address decode Shift decode Operation decode

Dual port register array Barrel shifter ALU

Data bus Data bus

Fig. 4.8 Block diagram of microprocessor data path

Data flows along n parallel paths in the horizontal direction, while control of the data flow and ALU operations in
provided vertically from the top of the data path. Execution of a typical data path operation requires selection of
operands from two registers execution of an operation on the two selected operands, and placement of the result in
a register.
The use of a dual port register array is convenient for the fast execution of microprocessor programs. This local
storage is usually provided within the data path as a small array of static memory cells. These are organized as an n x
m structure where n is the width is bits of microprocessor data bus and m is the number of register provided. With a
dual-port register array contents from two separate registers can be fetched simultaneous to minimize the delay
before execution of an operation can being.
The memory cell structure of a dual-port register array is quite similar to that of an SRAM cell. The memory cell used
for the dual-port register array of the Berkeley RISC processor is shown in Fig.4.9 . In this circuit, the designers took
advantage of the provision of double line data access to allow the contents from two registers to be obtained
simultaneously.

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

6
 STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)

Select A

Bus B Bus A

Fig. 4.9 : Memory structure of dual port register

S cell
ct
Both data lines must be gated to the storage cell with complementary values for a operation. However the contents of
the storage cell may be read by getting the cell to data line. If provision is made to drive the two select lines A and B,
separately for operation, then it is possible to obtain the data from a first register along one line of the data bus (bus
A), while the data from a second register is obtain along the other rail of the data bus (bus B). So the data from the
second bus will be the complement of the cell data must be inverted.
2) Barrel Shifter :
A second component that is included in the data path for many microprocessors is a structure that allows the contents
of the data path to be shifted or rotated. A variable-length shift of a bit on the data path requires the possibility of
connecting the selected bit to anyone of several other bit paths. A 1-to-n multiplexer circuit for each bit will
accomplish the desired connection. An ideal means of implementing multiplexer circuits is provided by the pass
transistor available within MOS integrated circuits.
A particularly useful circuit structure to implement a shift or rotate is known as a barrel shifter. This circuit structure
can be explained by first considering Fig.4.10, which shows the circuit diagram of a general-purpose bus multiplexer
for a 4-bit data path. This multiplexer circuit requires 16 pass transistors to allow connection of any bit line to
any other bit line. If each pass transistor could be selected individually, 16 control lines would be required.
Because most requirements are for parallel shifts with all bits moved the same number of bit positions, only four
shift possibilities are really necessary.

B3

S32 S31 S30

S33 D3

S21 S20
S23 S22
B2

S10
S13 S12 S11 D2

B1
S03 S02 S01 S00

Fig. 4.10 : General bus multiplexer(16 control line, S00 to S33)

Figure 4.11 shows a better circuit with the pass transistors connected in groups of four, reducing control line
requirements from 16 to 4 separate control lines, 50-53. A particular control line might be selected by encoding a 2-

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

7
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

 STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)

Systolic Array:
The ability to place hundreds of thousands of transistors on a single integrated circuit and then replicate that circuit
inexpensively has led many researchers to propose the use of connected sets of identical integrated circuits to solve
problems in parallel. One class of parallel processors has been given the name systolic arrays because the data Flow
through the array.
The concept of systolic processing combines a highly parallel array of identical processors with local interconnections
and rhythmic data flow. The array of processors may span several IC’s. The connections are formed so that data the
data is accepted and processed at each level stage with result ready for output to the next stage as new data arrives at
the current stage.
The objective is to keep most processors busy doing useful work to reduce the time to achieve a result.

1) Bit-Serial Processing Elements:

The prospect for placing n parallel processing stages on a silicon die for large n. The size of the typical processing stages
and the interconnection buses require too much silicon area. A partial solution to this problem uses bit-serial
processing stages. These stages are smaller than their m-bit parallel counterparts by at leasing factor of m, allowing m
times as many stages to be placed on a silicon die.
If the processing stages are designed properly, individual stages will interconnect directly as they are placed, thereby
eliminating inter-connection buses. This technique of interconnection by default is generally useful within IC design
saving both layout time and silicon area.
Initially it might appear that bit-serial processing stages are a factor of 1/m as fast as parallel processing stages. This
could negate the gain achieved by placing m times as many processors on a silicon die. However, bit-serial multipliers
and adders can be designed to eliminate carry propagation delay. This allows a net processing speed advantage when
m bit-serial processing stages m-bit parallel processing stage.
The ability to create special purpose processors to provide parallel solution of time consuming problems may be the
next major step in increasing computational speeds. The concept of systolic processing with many processors working
in lock step fashion is an important means to achieve this goal.
An example of a simple bit-serial multiplier is given in Fig. 4.13. The algorithm for this particular bit-serial
multiplier requires the multiplicand b in parallel and the multiplier a in bit-sequential form. During the first
iteration, the first bit of the multiplier ao is input and ANDed with the parallel multiplicand b, producing a set of
variables called summands. The summands are added by the full adders to compute a set of partial product bits and
the first product bit Po. Carries and partial product bits are saved and shifted through unit delay registers so they are
available for the next step. As the second multiplier bit a1 is shifted in, it is ANDed with the multiplicand and added
to previous carries and partial product bits. This produces a second bit of the product P1. At each iteration the
weight of each stage doubles, allowing the carry to be fed back within the same stage. This operation continues until
the multiplier a is exhausted and the entire product has been shifted out of the multiplier.

Fig. 4.13: Simple Bit-Serial Multiplier

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

9
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

Thank you for using our services. Please support us so that we can
improve further and help more people.
https://www.rgpvnotes.in/support-us

If you have questions or doubts, contact us on

WhatsApp at +91-8989595022 or by email at [email protected].

For frequent updates, you can follow us on

Instagram: https://www.instagram.com/rgpvnotes.in/.