Concepts of Digital Design

Introduction to Verilog

1
 The Verilog Language
• A hardware description language (HDL) used for
modeling, simulation and synthesis of digital
electronic systems
• One of the two most commonly-used languages in
digital hardware design (VHDL is the other)
• Virtually every chip (FPGA, ASIC, etc.) is designed in
part using one of these two languages
• Combines structural and behavioral modeling styles
• IEEE standard 1364-1995
• Verilog-2001 extends the initial Verilog-95 specification

2
 Simulation
• Simulation is used to verify the functional
characteristics of models at any level of abstraction
• One of the main uses of Verilog/VHDL is simulation
• To test if the RTL code meets the functional
requirements of the specification, we must see if all
the RTL blocks are functionally correct.
• To achieve this we need to write a testbench, which
generates clk, reset and the required test vectors
• Simulation is needed after every refinement step
– Behavioral, zero-delay gate level, timing, post P&R
simulation

3
 How Are Simulators Used?
• Testbench generates stimulus and checks
response
• Coupled to model of the system
• Pair is run concurrently

Stimulus

Testbench System Under Test

Response
Result
checker

4
 Learn by Example: Combinational Logic
Adder: a circuit that does addition
Here’s an example of binary addition:
Adding two N-bit 1101
numbers produces an
(N+1)-bit result +0101

10010

“Ripple-
carry
adder”

5
 1-bit Adder

Build Truth Table and use Sum of Products (SOP)

Α Β Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0 Sum: S  A  B  C
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 Carry Out:
1 1 0 0 1 CO  A'BC  AB'C  ABC'  ABC
1 1 1 1 1  (A'  A)BC  (B'  B)AC  AB(C'  C)
 BC  AC  AB

6
 1-bit Adder
module: Basic unit of description One line comment

// This is a behavioral module of 1-bit adder

module fulladd (Cin, x, y, s, Cout); I/O ports with which the module
input Cin, x, y; communicates externally with other
output s, Cout; modules

assign s = x ^ y ^ Cin;
assign Cout = (x & y) | (x & Cin) | (y & Cin);

endmodule Continuous assignment: the RHS is

evaluated again every time the value
of an operand changes. The LHS is
assigned that value.

This is an example of Behavioral Description

7
 4-bit Adder Structural Description
Multiple lines comment
/* This is a structural module of 1-bit adder
*/
module adder4 (carryin, X, Y, S, carryout);
input carryin;
input [3:0] X, Y;
Instantiation of the module fulladd
output [3:0] S;
output carryout; Arguments correspond to formal
wire [3:1] C; parameters of modules

fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);

fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);

endmodule 8
 Alternative N-bit Adder
module addern #(parameter n=32) (carryin, X, Y, S, carryout);
input carryin;
input [n-1:0] X, Y; n=32 sets default value for parameter n
output [n-1:0] S;
output carryout; reg is a data type that indicates a
reg [n-1:0] S; driver that can store a value.
reg carryout; If a signal is not reg, it is a wire
reg [n:0] C; An always statement is only triggered at (@) the
integer k; condition in the parenthesis (sensitivity list).
We execute the always statement only when X or Y or
always @(X, Y, carryin) carryin change
begin
C[0] = carryin;
for (k = 0; k < n; k = k+1)
begin
S[k] = X[k] ^ Y[k] ^ C[k];
C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]);
end
carryout = C[n];
end
endmodule
Behavioral Description 9
 Another one
module addern #(paramtere n=32) (carryin, X, Y, S, carryout, overflow);
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout, overflow;
reg [n-1:0] S; S, X, Y are arrays
reg carryout, overflow;

always @(X or Y or carryin)

begin
S = X + Y + carryin;
carryout = (X[n-1] & Y[n-1]) | (X[n-1] & ~S[n-1]) | (Y[n-1] & ~S[n-1]);
overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1];
end

endmodule

Behavioral Description
10
Language Elements and Expressions
 Numbers in Verilog
• Integer numbers
– Simple decimal notation
• 32, -15
– Base format notation : [size in bits]’base value
– Base is one of d or D (decimal), o or O (octal), b or B (binary), h
or H (hex). Use s for signed.
• 5’O37 // 5 bit octal number 37
• 4’D2 // 4 bit decimal number 2
• 4’B1x_01 // 4 bit binary number 1x01.
• 7’Hx // 7 bit hex xxxxxxx
• 8’shFF // Signed hex equal to -1
• 4’d-4 // Not legal. The sign is before the size.
• -4’d4 // 4-bit binary number -4. The sign is before the size
• (2+3)d’10 // Not legal. Size cannot be an expression
– The underscore character (_) is legal anywhere in a number
except as the first character, where it is ignored
– When used in a number, the question mark (?) character is the
Verilog alternative for the z character.
12
 Numbers in Verilog
• Real numbers
– Decimal notation
• 32.0, -11.06
• 2. // Not legal. Must have a digit on either side of
decimal
– Scientific notation
• 23.51e2 // 2351.0
• 23_5.1e1 // 2351.0
• 5E-4

13
 Strings in Verilog
• A string is a sequence of chars within double
quotes
– “Verilog is cool!”

14
 Four-valued Data
• Verilog’s nets and registers hold four-valued data

• 0, 1
– Obvious
• Z (high impedance)
– Output of an undriven tri-state driver
– Models case where nothing is setting a wire’s value
• X (unknown or undecided)
– Models when the simulator can’t decide the value
– Initial state of registers
– When a wire is being driven to 0 and 1 simultaneously
– Output of a gate with Z inputs

15
 Two Main Data Types
• Wires represent connections between things
– Do not hold their value
– Take their value from a driver such as a gate or other module
– A signal is wire by default

• Regs represent data storage

– Behave exactly like memory in a computer
– Hold their value until explicitly assigned in an initial or always
block
– Can be used to model latches, flip-flops, etc., but do not
correspond exactly
– Shared variables with all their attendant problems

16
 Nets and Registers
• Wires and registers can be bits, vectors, and arrays

wire a; // Simple wire

wire [15:0] dbus; // 16-bit bus
wire #(5,4,8) b; // Wire with rise delay 5, fall
delay 4, and turn-off delay (hiZ) 8
reg [-1:4] vec; // Six-bit register
integer imem[0:1023]; // Array of 1024 integers
reg [31:0] dcache[0:63]; // A 32-bit mem with 64
entries
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 Operators
• Arithmetic operators
• X = (A+B)-C // binary plus and minus
• X = -Y // unary minus
• X = Y*Z // multiplication
• X = A/B // division
• X = A%B // modulus is the remainder with
// the sign of the dividend.
// 7%4 = 3, -7%4 = -3, 7%-4 = 3
• X = A**B // exponent (Only in Verilog 2001)

18
 Operators
• Relational operators
– The result is 0 (false), 1 (true), or x (either operand
has an x or z bit)
• 23 > 45 // false (value 0)
• 52 < 8’hxFF // result is x
• ‘b1000 >= ‘b01110 // false. Smaller sized operand is
zero-filled

19
 Operators
• Equality operators.
– 2’b10 == 4’b0010 // true
– ‘b11x0 == ‘b11x0 // unknown because there
is a bit in in either operand which is x (or z)
– ‘b11x0 === ‘b11x0 // true. In case equality, x
and z are compared strictly as values

20
 Operators
• Logical operators.
– A && B // logical AND
– A || B // logical OR
– !A // logical NOT

21
 Operators
• Bit-wise operators
– ~A (unary negation)
– & (binary and)
– | (binary or)
– ^ (binary xor)
– ~^ (binary XNOR)

AND (&) OR (I)

0 1 X Z 0 1 X Z

0 0 0 0 0 0 0 1 X X
1 0 1 X X 1 1 1 1 1
X 0 X X X X X 1 X X
Z 0 X X X Z X 1 X X

22
 Operators
• Reduction operators
• A = ‘b0110, B = ‘b0100, C = ‘b0x1
• &B is 0 // logical AND of all bits
• |B is 1 // logical OR of all bits
• ~&A is 1 // logical NAND of all bits
• ^B is 1 // logical XOR of all bits
• ~^B is 0 // logical XNOR of all bits
• &C is 0 // at least a bit is 0
• |C is 1 // at least a bit is 1
• ^C is x // if any bit is x or z, result is x

23
 Operators
• Shift operators
– A >> B // logical right shift
– A << B // logical left shift
– A >>> B // right shift for signed numbers (Only
Verilog 2001)
– A <<< B // left shift for signed numbers (Only
Verilog 2001)

• Conditional operator
– cond_expr? expr1 : expr2
24
 Operators
• Concatenation and Replication operators
– wire [7:0] Dbus
– wire [11:0] Abus
– assign Dbus = {Dbus[3:0], Dbus[7:4]} //
concatenation: swap nibbles
– Abus ={3{4’b1011}} // 12’b1011_1011_1011

25
Two ways to express hardware in
Verilog:
Structural and Behavioral Models
 Two Main Components of Verilog
• Concurrent, event-triggered processes (behavioral)
– Initial and Always blocks
– Imperative code that can perform standard data
manipulation tasks (assignment, if-then, case)
– Processes run until they delay for a period of time or wait
for a triggering event
• Structure (structural)
– Verilog program built from modules with I/O interfaces
– Modules may contain instances of other modules
– Modules contain local signals, etc.
– Module configuration is static and all run concurrently
• High level modules typically structural
• Low level modules (leaves) typically behavioral
27
 Structural Modeling
• When Verilog was first developed (1984) most
logic simulators operated on netlists
• Netlist: list of gates and how they’re
connected
• A natural representation of a digital logic
circuit
• Not the most convenient way to express test
benches

28
 Behavioral Modeling
• A much easier way to write testbenches
• Also good for more abstract models of circuits
– Easier to write
– Simulates faster
• More flexible
• Provides sequencing
• Verilog succeeded in part because it allowed both
the model and the testbench to be described
together

29
 Multiplexer Built From Primitives
Identifiers not
module mux(f, a, b, sel); explicitly defined
default to wires
output f;
input a, b, sel; Module may contain
Predefined module types structure: instances of
primitives and other
and g1(f1, a, nsel), modules

g2(f2, b, sel);
or g3(f, f1, f2); a f1
nsel g1
not g4(nsel, sel); g4
g3 f
b
endmodule sel
g2
f2

30
 Multiplexer Built With Always
Modules may contain one or
more always blocks
module mux(f, a, b, sel);
output f;
input a, b, sel; Sensitivity list
reg f; contains signals
whose change
triggers the execution
always @(a, b, sel) of the block
if (sel)
f = b;
a
else
f = a; f
b
endmodule sel

31
 Mux with Continuous Assignment
LHS is always set to the value on
the RHS
module mux(f, a, b, sel); Any change on the right causes
reevaluation
output f;
input a, b, sel;

assign f = sel ? b : a;
a
endmodule
f
b
sel

32
Structural Modeling in more
detail
 Modules and Instances
• Basic structure of a Verilog module:

module mymod(port1, port2, … portN);

output port1;
Verilog convention lists
output [3:0] port2; outputs first. This is not
necessary
input [2:0] portN;
…
endmodule

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 Modules and Instances
• Verilog 2001 allows port direction and data type in
the port list of modules as shown in the example
below
module mymod(output port1,
output [3:0] port2,
…
input [2:0] portN);

…
endmodule
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 35
 Instantiating a Module
• Instances of

module mymod(y, a, b);

• look like

mymod mm1(y1, a1, b1); // Connect-by-position

mymod (y2, a1, b1),
(y3, a2, b2); // Instance names omitted
mymod mm2(.a(a2), .b(b2), .y(c2)); // Connect-by-name

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 36

 Gate-level Primitives
• Verilog provides the following keywords for gate
level modeling:

and nand logical AND/NAND

or nor logical OR/NOR
xor xnor logical XOR/XNOR
buf not buffer/inverter
bufif0 notif0 Tristate buf with low enable
bifif1 notif1 Tristate buf with high enable
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 Switch-level Primitives
• Verilog also provides mechanisms for modeling CMOS
transistors that behave like switches
• A more detailed modeling scheme that can catch some
additional electrical problems when transistors are
used in this way
• Rarely used because circuits generally aren’t built this
way
• More seriously, model is not detailed enough to catch
many of the problems
• These circuits are usually simulated using SPICE-like
simulators based on nonlinear differential equation
solvers

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Behavioral Modeling in more
detail
 Types of Assignments in Verilog
• Continuous and Procedural Assignments
• Continuous assignments model combinational
behavior only
– They assign a value to a wire (never to a reg)
– assign LHS_target = RHS_expression
– The continuous statement executes every time an event
happens in the RHS expression
– The expression is evaluated
– If the result is different, the new value is assigned to the
LHS target

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 Continuous Assignment
• Convenient for logical or data path specifications

Define bus widths

wire [8:0] sum;

wire [7:0] a, b; Continuous assignment:
permanently sets the value
wire carryin; of sum to be a+b+carryin
Recomputed when a, b, or
carryin changes

assign sum = a + b + carryin;

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 41
 Types of Assignments in Verilog
• Procedural assignments model combinational
and sequential behavior
• They appear only within an initial statement or
an always statement
• Two different types of procedural assignments
– Blocking
– Non-blocking

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 Initial and Always Blocks
• Basic components for behavioral modeling
initial always
begin begin
… imperative statements … … imperative statements …
end end

Runs when simulation starts Runs when simulation starts

Terminates when control reaches the end Restarts when control reaches the end
Good for providing stimulus in testbenches Good for modeling/specifying hardware

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 Timing Controls
• Two forms of timing control:
– Delay control
– Event control

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 44

 Delay Controls
• Delay control is of the form
# delay <procedural statement>
It specifies the time units from the time the statement is
initially encountered to the time it is executed

e.g.
#2 input = 4’b0101; // wait for 2 units, and then make
the assignment
input = #1 x // assign to input the value that x will have after
1 time unit. Different than #1 input = x

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 45

 Event Controls
• Edge-triggered event control is of the form
@ event <procedural statement>
e.g. @ (posedge clk) curr_state = next_state
@ (X or Y) A <= 0; // when X or Y change

• Level-triggered event control is of the form

wait (condition) <procedural statement>
The statement executes only if the condition is true,
else it waits until the condition becomes true.
e.g. wait(DataReady);
Data = Bus
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 46
 Initial and Always
• Run until they encounter a delay

initial begin
#10 a = 1; b = 0;
#10 a = 0; b = 1;
end

• or a wait for an event

always @(posedge clk) q = d;

always
begin
wait(i); a = 0; wait(~i); a = 1;
end

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 47

 Blocking Procedural Assignment
• Inside an initial or always block:

sum = a + b + cin;

• Just like in C: RHS evaluated and assigned to LHS

before next statement executes

• RHS may contain wires and regs

– Two possible sources for data
• LHS must be a reg
– Primitives or cont. assignment may set wire values

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 48

 Imperative Statements
if (select == 1) y = a;
else y = b;

case (op)
2’b00: y = a + b;
2’b01: y = a – b;
2’b10: y = a ^ b;
default: y = ‘hxxxx;
endcase

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 49

 For Loops
• A increasing sequence of values on an output

reg [3:0] i, output;

for ( i = 0 ; i <= 15 ; i = i + 1 ) begin

output = i;
#10;
end

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 50

 While Loops
• A increasing sequence of values on an output

reg [3:0] i, output;

i = 0;
while (i <= 15) begin
output = i;
#10 i = i + 1;
end

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 51

Blocking vs. Non Blocking Assignments
• Verilog has two types of procedural
assignments

• Fundamental problem:
– In a synchronous system, all flip-flops sample
simultaneously
– In Verilog, always @(posedge clk) blocks run in
some undefined sequence

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 52

 A Flawed Shift Register
• This doesn’t work as you expect:

reg d1, d2, d3, d4;

always @(posedge clk) d2 = d1;

always @(posedge clk) d3 = d2;
always @(posedge clk) d4 = d3;

• These run in some order, but you don’t know

which
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 53
 Non-blocking Assignments
Nonblocking rule:
RHS evaluated when
• This version does work: assignment runs

reg d1, d2, d3, d4;

always @(posedge clk) d2 <= d1;

always @(posedge clk) d3 <= d2;
always @(posedge clk) d4 <= d3;
LHS updated only after all
events for the current instant
have run. It runs after a Delta
time
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 54
 Nonblocking Can Behave Oddly
• A sequence of nonblocking assignments don’t
communicate
a <= 1;
b <= a;
a = 1; c <= b;
b = a;
c = b; Nonblocking assignment after δ
time:
Blocking assignment: a=1
a=b=c=1 b = old value of a
c = old value of b

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 55

 Nonblocking Looks Like Latches
• RHS of nonblocking taken from latches
• RHS of blocking taken from wires
a b c
a = 1; 1
b = a;
c = b;

1 a
a <= 1;
b <= a;
c <= b; b

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Sequential Logic and Finite State
Machines in Verilog
 Why we need sequential logic?
What if you were given the following design specification:

When the button is What makes this circuit

pushed: different from those
1)Turn on the light if it
is off we’ve discussed
button light
2)Turn off the light if it before?
is on
The light should 1.“State” – i.e. the circuit
change state within a has memory
second of the button
2.The output was
press
changed by a input
“event” (pushing a
button) rather than an
input “value”
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 58
 Digital State
One model of what we’d like to build

New
Memory
State
Device Current
State Combinational
LOAD Logic

Input Output

Plan: Build a Sequential Circuit with stored digital STATE –

•Memory stores CURRENT state
•Combinational Logic computes
•NEXT state (from input, current state)
•OUTPUT bit (from input, current state)
•State changes on LOAD control input
If Output depends on Input and current state, circuit is called a Mealy machine.
If Output depends only on the current state, circuit is called a Moore machine.
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 59
 Our building block: the D FF

The edge-triggered D register: on the rising

edge of CLK, the value of D is saved in the
register and then shortly afterwards appears
on Q.

CLK

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 60

 D-Register Timing

t
≤ PD

t
≥ CD

CLK

tPD: maximum propagation delay, CLK  Q ≥ tSETUP ≥ tHOLD

tCD: minimum contamination delay, CLK Q

tSETUP: setup time
How long D must be stable before the rising edge of CLK

tHOLD: hold time

How long D must be stable after the rising edge of CLK

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 61

 The Sequential always Block
module dff (input D, CLK, output reg Q);
always @(posedge clk)
begin
Q<=D;
end
endmodule;

module CL(input a,b, sel, module SL(input a,b, sel,

output reg out); output reg out);
always @(*) always @(posedge clk)
begin begin
if (sel) out = b; if (sel) out <= b;
else out = a; else out <= a;
end end
endmodule; endmodule;

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Finite State Machines and Verilog
 Finite State Machines
•Finite State Machines (FSMs) are a useful abstraction for
sequential circuits with centralized “states” of operation
•At each clock edge, combinational logic computes outputs and
next state as a function of inputs and present state

inputs Combinational outputs

Logic
+ +
present state next state

n n

Q D

Registers
CLK

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 64

 Two types of Finite State Machines
Moore and Mealy FSMs : different output generation
•Moore FSM:

next
state S'D
inputs Q
Comb. Outputs
x0...xn Comb. Registers
Logic Logic yk = fk(S)
CLK
n

present state S

•Mealy FSM:

next
state S'D
inputs Q
Comb. Outputs
x0...xn Comb. Registers
Logic Logic yk = fk(S, x0...xn)
CLK
n

present state S

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 65

 Design Example: Level-to-Pulse

• A level-to-pulse converter produces a

single- cycle pulse each time its input
goes high.
• It’s a synchronous rising-edge detector.
• Sample uses:
–Buttons and switches pressed by
humans for arbitrary periods of time
–Single-cycle enable signals for counters

Level to
L Pulse P
Whenever input L goes Converter ...output P produces a single
from low to high... pulse, one clock period wide.
CLK

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 66

Step 1: State Transition Diagram

Level (L) L Level toP Pulse (P)

Pulse FSM

CLK

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 67

Step 2: Logic Derivation

+
S0 = L

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 68

Moore Level-to-Pulse Converter

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Design of a Mealy Level-to-Pulse

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Design of a Mealy Level-to-Pulse

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Second FSM Example

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Step 1A: Block Diagram

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Step 1B: State transition diagram

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 74

 Step 2. Verilog Implementation of the FSM
module lock(input clk, reset, b0, b1, output out);
wire reset;
parameter S_RESET = 0; parameter S_0= 1; // state assignments
parameter S_01 = 2; parameter S_010 = 3;
parameter S_0101 = 4; parameter S_01011 = 5;
always @(*)
begin // First always computes next state
case (state)
S_RESET: next_state = b0 ? S_0 : (b1 ? S_RESET : state);
S_0: next_state = b0 ? S_0 : (b1 ? S_01 : state);
S_01: next_state = b0 ? S_010 : (b1 ? S_RESET : state);
S_010: next_state = b0 ? S_0 : (b1 ? S_0101 : state);
S_0101: next_state = b0 ? S_010 : (b1 ? S_01011 : state);
S_01011: next_state = b0 ? S_0 : (b1 ? S_RESET : state);
default: next_state = S_RESET;
endcase
end // always

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 75

Step 2. Verilog Implementation of the FSM

always @(posedge clk) // Second always computes next state

if (reset == 1’b1)
state <= S_RESET;
else
state <=next_state;

assign out = (state == S_01011);

endmodule

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 76

 Modeling FSMs Behaviorally
• There are many ways to do it:

1. Define the next-state logic combinationally

and define the state-holding latches explicitly

1. Define the behavior in a single always

@(posedge clk) block

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 77

Testbenches
 Writing Testbenches
Inputs to device under test
module test;
reg a, b, sel; Device under test (DUT)

mux m(y, a, b, sel);

$monitor is a built-in event
initial driven “printf”
begin
$monitor($time, “a = %b, b=%b, sel=%b, y=%b”,
a, b, sel, y);
a = 0; b= 0; sel = 0;
#10 a = 1; Stimulus generated by sequence
#10 sel = 1; of assignments and delays
#10 b = 1;
end
endmodule

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 79

 Writing Testbenches
module first_counter_tb();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [3:0] counter_out;

//Initialize all variables

initial
begin
$display ("time\t clk reset enable counter");
$monitor ("%g\t %b %b %b %b",
$time, clock, reset, enable, counter_out);
clock = 1; // initial value of clock
reset = 0; // initial value of reset
enable = 0; // initial value of enable
#5 reset = 1; // Assert the reset
#10 reset = 0; // De-assert the reset
#10 enable = 1; // Assert enable
#100 enable = 0; // De-assert enable
#5 $finish; // Terminate simulation
end

// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end

// Connect DUT to test bench

first_counter U_counter ( clock, reset, enable, counter_out );

end module Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 80

Simulating Verilog
 Simulation Behavior
• Scheduled using an event queue
• Non-preemptive, no priorities
• A process must explicitly request a context
switch
• Events at a particular time unordered

• Scheduler runs each event at the current time,

possibly scheduling more as a result

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 82

 Two Types of Events
• Evaluation events compute functions of inputs
• Update events change outputs
• Split necessary for delays, nonblocking
assignments, etc.
Update event writes
new value of a and a <= b + c Evaluation event reads
schedules any values of b and c, adds them,
evaluation events that and schedules an update
are sensitive to a event
change on a signal

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 83

 Simulation Behavior
• Concurrent processes (initial, always) run until they
stop at one of the following

• #42
– Schedule process to resume 42 time units from now
• wait(cf & of)
– Resume when expression “cf & of” becomes true
• @(a or b or y)
– Resume when a, b, or y changes
• @(posedge clk)
– Resume when clk changes from 0 to 1

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 84

 Simulation Behavior
• Infinite loops are possible and the simulator does not
check for them
• This runs forever: no context switch allowed, so ready
can never change

while (~ready)
count = count + 1;

• Instead, use

wait(ready);

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 85

 Simulation Behavior
• Race conditions abound in Verilog

• These can execute in either order: final value

of a undefined:

always @(posedge clk) a = 0;

always @(posedge clk) a = 1;

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 86

Verilog and Logic Synthesis
 Logic Synthesis
• Verilog is used in two ways
– Model for discrete-event simulation
– Specification for a logic synthesis system

• Logic synthesis converts a subset of Verilog

language into an efficient netlist
• One of the major breakthroughs in designing
logic chips in the last 20 years
• Most chips are designed using at least some logic
synthesis

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 88

 Logic Synthesis Tools
• Mostly commercial tools
– Very difficult, complicated programs to write well
– Limited market
– Commercial products in $10k - $100k price range

• Major vendors
– Synopsys Design Compiler, FPGA Express
– Cadence BuildGates
– Synplicity (FPGAs)
– Exemplar (FPGAs)

• Academic tools
– SIS (UC Berkeley)

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 89

 Logic Synthesis
• Takes place in two stages:

• Translation of Verilog (or VHDL) source to a

netlist
– Register inference

• Optimization of the resulting netlist to

improve speed and area
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 90
 Logic Optimization
• Netlist optimization the critical enabling technology
• Takes a slow or large netlist and transforms it into one
that implements the same function more cheaply

• Typical operations
– Constant propagation
– Common subexpression elimination
– Function factoring

• Time-consuming operation
– Can take hours for large chips

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 91

 Translating Verilog into Gates
• Parts of the language easy to translate
– Structural descriptions with primitives
• Already a netlist
– Continuous assignment
• Expressions turn into little datapaths

• Behavioral statements the bigger challenge

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 92

 What Can Be Translated
• Structural definitions
– Everything
• Behavioral blocks
– Depends on sensitivity list
– Only when they have reasonable interpretation as
combinational logic, edge, or level-sensitive latches
– Blocks sensitive to both edges of the clock, changes on
unrelated signals, etc. cannot be synthesized
• User-defined primitives
– Primitives defined with truth tables
– Some sequential UDPs can’t be translated (not latches or
flip-flops)

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 93

 What Isn’t Translated
• Initial blocks
– Used to set up initial state or describe finite testbench
stimuli
– Don’t have obvious hardware component
• Delays
– May be in the Verilog source, but are ignored by
synthesizer
• A variety of other obscure language features
– In general, things heavily dependent on discrete-event
simulation semantics
– Certain “disable” statements

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 94

 Register Inference
• The main trick

• reg does not always equal latch

• Rule:
• Combinational if outputs always depend
exclusively on sensitivity list
• Sequential if outputs may also depend on
previous values

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 95

 Register Inference
• Combinational: Sensitive to changes on all of
the variables it reads
reg y;
always @(a or b or sel)
if (sel) y = a; Y is always assigned
else y = b;
• Sequential:
reg q;
q only assigned when clk is 1
always @(d or clk)
if (clk) q = d;

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 96

 Register Inference
• A common mistake is not completely specifying a
case statement
• This implies a latch:

always @(a or b)
case ({a, b})
2’b00 : f = 0;
f is not assigned when {a,b} = 2b’11
2’b01 : f = 1;
2’b10 : f = 1;
endcase
Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 97
 Register Inference
• The solution is to always have a default case

always @(a or b)
case ({a, b}) f is always assigned
2’b00: f = 0;
2’b01: f = 1;
2’b10: f = 1;
default: f = 0;
endcase

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 98

 Inferring Latches with Reset
• Latches and Flip-flops often have reset inputs
• Can be synchronous or asynchronous

• Asynchronous positive reset:

always @(posedge clk or posedge reset)

if (reset)
q <= 0;
else
q <= d;

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 99

 Inferring Latches with Reset

• Synchronous positive reset:

always @(posedge clk)

if (reset)
q <= 0;
else
q <= d;

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 100

 Simulation-synthesis Mismatches
• Many possible sources of conflict

• Synthesis ignores delays (e.g., #10), but

simulation behavior can be affected by them
• Simulator models X explicitly, synthesis doesn’t
• Behaviors resulting from shared-variable-like
behavior of regs is not synthesized
– always @(posedge clk) a = 1;
– New value of a may be seen by other @(posedge clk)
statements in simulation, never in synthesis

Οργάνωση και Σχεδίαση Η/Y (ΗΥ232) 101

FPGA architecture and
design technology

- 1
 FPGA fabric

• A generic island-style
FPGA fabric
• Configurable Logic Blocks
(CLB) and Programmable
Switch Matrices (PSM)
• Bitstream configures
functionality of each CLB
and interconnection
between logic blocks

CE435 - Embedded Systems 2

CLB (Combinational Logic Block)
Xilinx case

- 3
 TheDetailed
Xilinx Slice
Structure
• Xilinx slice features
– LUTs
– MUXF5, MUXF6,
MUXF7, MUXF8
(only the F5 and
F6 MUX are shown
in this diagram)
– Carry Logic
– MULT_ANDs
– Sequential Elements

Basic
- Architecture 4
 Slice Logic
• Look-Up Tables
– An N-input LUT to implement
any combinational boolean
function with N inputs
– Coarser-grained than logic
gates
– Less area efficient than fixed
logic gates (e.g. 4-input AND
gate)
– Very powerful concept for
implementation of bit-level
random digital logic.
– Typical values (N=4,5, or 6)
- 5
 Example 2-input LUT

• Lookup table: a b out

0 0 0 1

a 0001 0 1 0 0
out
LUT
b
1001 1 0 0 0

configuration 1 1 1 1
input

CE435 - Embedded Systems 6

Example 4-input LUT

CE435 - Embedded Systems 7

 Slice Logic
• D Flip Flops
– A D-Flip Flop at the
output of the LUT can be
used to latch the output
data
– It can also be used to
carry state in FSM
designs OR
– as a pipeline stage
– etc.
CE435 - Embedded Systems 8
 Slice Logic
• Carry Logic
– Carry Logic is used to
speed up carry-based
computations.
– Additions (CLA, Ripple
Carry Adders), parity
functions, etc.
– Cin/Cout routing is
separate from general
purpose routing (fewer
logic stages and faster)

CE435 - Embedded Systems 9

 Carry Chains
Dedicated carry chains speeds up arithmetic operations

• Simple, fast, and COUT COUT

To S0 of the
complete arithmetic next CLB
To CIN of S2 of the next
CLB
Logic SLICE
– Dedicated XOR gate First Carry
S3
CIN
for single-level sum Chain COUT
completion
– Uses dedicated SLICE
S2
routing resources
– All synthesis tools can SLICE
infer carry logic CIN
S1
COUT
Second
Carry
S= 𝐴 𝑥𝑜𝑟 𝐵 𝑥𝑜𝑟 𝐶𝑖𝑛 Chain

Cout= 𝐴𝐵 +
SLICE
S0
(𝐶𝑖𝑛(𝐴 𝑥𝑜𝑟 𝐵 )) CIN CIN CLB

CE435 - Embedded Systems Basic Architecture 10

 Multiplexer Logic
Dedicated MUXes provided to connect slices and LUTs

MUXF8 combines the two

CLB

F8
MUXF7 outputs (from the

F5
CLB above or below)
Slice S3
MUXF6 combines slices S2

F6
and S3

F5
Slice S2

MUXF7 combines the two

F7

MUXF6 outputs
Slice S1
F5

MUXF6 combines slices S0 and S1

F6

Slice S0
F5

MUXF5 combines LUTs in each slice

CE435
Basic- Embedded
Architecture
Systems
11
 Programmable wiring
• Organized into channels.
– Many wires per channel.
• Connections between wires made at
programmable interconnection points.
• Must choose:
– Channels from source to destination.
– Wires within the channels.
• Routing area typically much larger than logic
area
CE435 - Embedded Systems 12
 Programmable interconnect

• MOS switch controlled by configuration bit:

D Q

CE435 - Embedded Systems 13

Programmable wiring paths

CE435 - Embedded Systems 14

 Switchbox

channel
channel channel
channel

CE435 - Embedded Systems 15

 Choosing a path

LE

LE

CE435 - Embedded Systems 16

 Interconnection architectures

Segmented interconnects consists of shorter wires that connect

to emulate longer wires
Hierarchical interconnects assume that most connections are local
CE435 - Embedded Systems 17
 Routing problems
• Global routing:
– Which combination of channels?
• Local routing:
– Which wire in each channel?
• Routing metrics:
– Net length.
– Delay.

CE435 - Embedded Systems 18

 I/O
• Fundamental selection: input, output, three-
state?
• Additional features:
– Register.
– Voltage levels.
– Slew rate.

CE435 - Embedded Systems 19

 Configuration
• Must set control bits for:
– LE.
– Interconnect.
– I/O blocks.
• Usually configured off-line.
– Separate burn-in step (antifuse).
– At power-up (SRAM).

CE435 - Embedded Systems 20

 Configuration vs. programming
• FPGA configuration:
– Bits stay at the device • CPU programming:
they program. – Instructions are fetched
from a memory.
– A configuration bit
controls a switch or a – Instructions select
complex operations.
logic bit.

add r1, r2 add IR

r1, r2
memory CPU

CE435 - Embedded Systems 21

 Reconfiguration
• Some FPGAs are designed for fast
configuration.
– A few clock cycles, not thousands of clock cycles.
• Allows hardware to be changed on-the-fly.

CE435 - Embedded Systems 22

FPGA fabric architecture questions
• Given limited area budget:
– How many logic elements?
– How much interconnect?
– How many I/O blocks?

CE435 - Embedded Systems 23

 Logic element questions
• How many inputs?
• How many functions?
– All functions of n inputs or eliminate some
combinations?
– What inputs go to what pieces of the function?
• Any specialized logic?
– Adder, etc.
• What register features?

CE435 - Embedded Systems 24

 Interconnect questions
• How many wires in each channel?
• Uniform distribution of wiring?
• How should wires be segmented?
• How rich is interconnect between channels?
• How long is the average wire?
• How much buffering do we add to wires?

CE435 - Embedded Systems 25

 I/O block questions
• How many pins?
– Maximum number of pins determined by package
type.
• Are pins programmed individually or in
groups?
• Can all pins perform all functions?
• How many logic families do we support?

CE435 - Embedded Systems 26

The Design Cycle for FPGAs (I)

CE435 - Embedded Systems 27

The Design Cycle for FPGAs (II)

CE435 - Embedded Systems 28

Mapping

CE435 - Embedded Systems 29

Placement

CE435 - Embedded Systems 30

Routing

CE435 - Embedded Systems 31

 Modern FPGA architecture
Xilinx Virtex family

Columns of on-chips SRAMs, hard IP cores (PPC 405), and

DSP slices (Multiply-Accumulate) units
CE435 - Embedded Systems 32
 DSP slices

Large number of hard multipliers allow for DSP applications

CE435 - Embedded Systems 33

Example Aplication: FIR filtering

CE435 - Embedded Systems 34

 Architectural Evolution
Reconfigurable FPGAs
Programmable
“System in a
Domain- Package”
Device Complexity and

optimized
System Logic
Performance

System • FPGA Fabric

Logic • Block RAM
• Embedded
Registers and
Platform • FPGA Fabric Multipliers
Logic • Block RAM • Clock Management
• Embedded • Multi-standard
Block • FPGA Fabric Registers and Programmable IO
Logic • Block RAM Multipliers • Embedded
Glue • Embedded Registers• Clock Management Microprocessor
and Multipliers • Multi-standard • Multigigabit
Logic • FPGA Fabric Programmable IO
• Clock Management Transceivers
• Block RAM • Embedded • Embedded DSP-
• Multi-standard
• FPGA Fabric Microprocessor optimized
Programmable IO
• Multigigabit Multiplers
Transceivers • Embedded Ethernet
MACs
1985 1992 2000 2002 2004 2005
CE435 - Embedded Systems 35