Advanced SimVision Debug Rapid Adoption Kit (RAK)

XCELIUM, Xcelium, INCISIVE, incisive, Probe, error, warning, Post Processing Mode(Inspection of HDL Waveforms), Debug Methodology(Post Processing Mode), Waveform
signal comparison(Using simcompare), Driver Tracing, Probing assertions, Probing HVL Objects(Transaction recording), Probing UVM Hierarchy, Sequence Debug, Interactive
Debug (Single stepping and break points), Setting breakpoints, Advantages of SimVision Interactive Debug, UVM Debug Challenges, UVM Sequence Viewer, UVM
Configuration Debug, UVM Register Debug, UVM Factory Debug, SHM, Simvision, UVM, Probe, Database, SHM database, VCD, SST2, EVCD, TCL, incremental, incfile,
incremental database, Delta Cycle ,Event,transaction,recording shm_probe, Assertion, Assertion Browser, simvisdbutil, Convert,UVM toolbar, SystemC,Waveform
SimVision Debug RAK
Agenda

Post Processing Mode(Inspection of HDL Waveforms()

Interactive Debug (Single stepping and break points)

Summary

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SimVision Debug RAK
Agenda

Post Processing Mode(Inspection of HDL/HVL Waveforms)

• Debug Methodology(Post Processing Mode)
• Waveform signal comparison(Using simcompare)
• Driver Tracing
• Probing assertions
• Probing HVL Objects(Transaction recording)
• Probing UVM Hierarchy
• Sequence Debug

Interactive Debug (Single stepping and break points)

• Setting breakpoints
• Advantages of SimVision Interactive Debug
• UVM Debug Challenges
• UVM Sequence Viewer
• UVM Configuration Debug
• UVM Register Debug
• UVM Factory Debug

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 Debug Methodology(Post Processing Mode)

Post Process HDL

waveform
inspection

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Post Processing Mode Post process HDL
waveform
inspection

Code
Post process debug
using only waveform
information + source
code

Debug Simulate

Fail

Done Inspect

Pass

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 Post process HDL
Launching a debug session with the right information waveform inspection

• Launching SimVision in Post process debug mode

– Commonly used switches include –snapshot passing a waves db
– Example (if snapshot and waves in current directory):
– simvision –snapshot <snapshot name> <waves db name>

– Example (if snapshot and waves in completely different directories):

– simvision
–cdslib <path to INCA_libs>/irun.lnx86.<version number>.nc/cds.lib
–snapshot <snapshot name>
<full path to waves db>
– For example: simvision -cdslib ~/simvision/examples/INCA_libs/irun.lnx86.19.20.nc/cds.lib -snapshot
worklib.md_top ~/demos/simvision/waves.shm

• Other common command line switches

– -input: Script that gets executed during initialization, -title: Adds a custom name to each
SimVision window (if running multiple SimVision sessions), -layout: Loads a layout

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 Waveform signal comparison(Using simcompare) Post process HDL
waveform
inspection

• There are multiple ways to compare signals within SimVision

– Simple compare of two signals in the Waveform Window
– Comparison of sets of signals (hierarchical or entire waveform databases) using SimCompare
• Using the Waveform Window:

1 – Select two signals of interest

Right Click->Create-> Comparison

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 Post process HDL
Waveform signal comparison waveform
inspection

SimCompare sidebar
contains hyperlinks to
each mismatch detected.
New group created
highlighting the
differences between
the signals

All mismatches
highlighted in red
throughout the window

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 Post process HDL
Waveform signal comparison waveform
inspection

• Using the SimCompare Manager:

1 - Open
databases for
comparison 3 - After scopes have
been added, click
“Submit Compare”

Waveform
databases
listed in the
sidebar
2 - Drag and
drop scopes
from the
sidebar here

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 Post process HDL
Waveform signal comparison waveform
inspection

New comparison
added to the list 5 - Click “View
Results”

Number of
mismatches
found

All mismatches
listed in waveform
sidebar

Mismatches
highlighted in the
waveform area
Clicking a mismatch in sidebar
adds the comparison to the
waveform area
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 Post process HDL
Mnemonic Mapping waveform
inspection

• SimVision contains highly customizable mnemonic map creation

1) Click the properties
toolbar button

2) Give the new

map a name and
set values here

3) Customize the
look of the
mnemonic with If you have a signal
many options already selected,
click Apply

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 Post process HDL
Mnemonic Mapping waveform
inspection

Can apply to other signals

through the Format-
>Radix/Mnemonic menu

New mnemonic is
applied to the
selected signal

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 Post process HDL
Driver Tracing waveform
inspection

• Driver Tracing vs. Signal Connections

– All signals are connected to drivers/loads in some way

Signal of
interest

A B C

B and C do not
Driver contribute to
driving D

– Users may not be interested in viewing all intermediate connections between a signal and
it’s driver/load
– Viewing all connections provides a full picture of what is going on but
– It can add complexity and clutter to the tracing task

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 Post process HDL
Connectivity Tracing waveform
Using Source Browser ‘Follow Signal’ inspection

• If you would like trace connectivity

– Use right-click -> “Follow Signal” feature of the Source Browser
– Use the Schematic Tracing window

Can follow the connectivity of the

signal upward or downward
through the hierarchy

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 Post process HDL
SimVision Driver Tracing Explained waveform
inspection

• There are several steps that take place under the hood when users perform a
driver trace operation within SimVision:

• Identify all
possible drivers
Launch • Invokes Driver • Snapshot • Heuristics • Contributing • Active Driver
Analyze • Graded drivers
Driver Trace process provides driver Driver • Algorithms Circuit signals identified Results
• Trace current
Static list • Uses recorded • Contributing • Static drivers
Trace Grading Sensitivity Presented
value of signal Drivers • List does not waveform data signals graded • No drivers found
Operation
reflect active
driver

• The driver tracing process utilizes recorded waveform values, connectivity

and static driver information from the snapshot and knowledge of the design
to identify the drivers and contributors of a given signal value
• Results are presented as:
– The active driver of the signal (if correctly identified)
– Graded list of potential drivers (if algorithms could not identify active driver)
– Static list of drivers (driver grading algorithms could not complete)
15
– No drivers found (there were no identifiable drivers of the signal)
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Invoking SimVision Driver Trace Operations - 1 Launch
Driver
• Invokes Driver
Trace process
Trace • Trace current
Operation value of signal

• There are several ways in SimVision to invoke driver tracing

– Source Browser:
– Default double click operation is to trace driver
– Use the driver trace toolbar buttons
– Waveform Window
– Select signal edge to trace Common Toolbar throughout
– Right-click-> Go To Cause SimVision

– Driver Trace Sidebar

– Use the trace driver buttons within the sidebar
– Schematic
– Use the driver trace toolbar buttons

• In all methods, you first need to select a signal to trace before invoking

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Invoking SimVision Driver Trace Operations - 2 Launch
Driver
• Invokes Driver
Trace process
Trace • Trace current
Operation value of signal

• Typically two types of driver tracing users perform

– Trace X
– Trace Value
• Both tracing operations are invoked using the same set of buttons
– Driver tracing buttons are value sensitive
– Button icon reflects current value being traced
If selected signal is
If selected signal
currently X, trace
contains a non-X value
buttons reflect this

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SimVision Driver Tracing Modes Launch
Driver
• Invokes Driver
Trace process
Trace • Trace current
Operation value of signal

• Automatic trace:
– Default trace mode when tracing X values in source and Waveform Go To Cause
– Automatically trace a value back its source, through several drivers if needed
– User interaction only required when driver grading can’t find driver with 100% accuracy
– Invoked through the Auto trace button shown above
– History of traced drivers is saved and accessible

• Trace driver:
– Default trace mode when tracing non-X values in source and Waveform Go To Cause
– Trace back to the next immediate driver
– Invoked through the Trace driver button shown above

• Though the basic user interface is simple, there are several advanced
preferences available
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Driver Tracing Preferences – 2 Launch
Driver
• Invokes Driver
Trace process
Trace • Trace current
Operation value of signal

• Preferences control the operation of the algorithms

Detects out of module
Highlights (green colour) for references (OOMRs)
any signal previously traced
Default modes for
Automatic X/Value trace

Influence X trace
decisions when multiple
X’s are detected

If an X is not detected
on the current cycle of a
Signal Tracing Sidebar signal, how many
Selections transitions to go back in
time looking for a match

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Presentation of Driver Tracing Results • Active Driver
• Graded drivers
Results
Presented • Static drivers
• No drivers
found

• Results are presented to the user based on the method of invocation

• Source Browser or Waveform Go To Cause
– Source browser updated (or opened) and driver of signal is highlighted

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Presentation of Driver Tracing Results • Active Driver
• Graded drivers
Results
Presented • Static drivers
• No drivers
found

• Trace Driver Sidebar

– Sidebar updated to highlight driver and contributing signals
– All contributors are displayed in order of relevance (according to driver grading algorithms)

Indicates that this is the

driver (100% grade)

Indicates that
contributor has a grading

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 Presentation of Driver Tracing Results • Active Driver
• Graded drivers
Results
Presented • Static drivers
• No drivers
found

• Automatic Trace History

– For Auto-trace, the complete trace path is retained and accessible
Full trace history is available
through the “previous historical
step” button

Auto-trace takes users

to the root cause of the
value change

Original Signal
Traced

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Presentation of Driver Tracing Results • Active Driver
• Graded drivers
Results
Presented • Static drivers
• No drivers
found

• Schematic Trace Driver operation

– Schematic updated to show the user the trace path

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Presentation of Driver Tracing Results • Active Driver
• Graded drivers
Results
Presented • Static drivers
• No drivers
found

• Schematic Automatic Trace Operation

– Schematic updated to show the user the complete trace path
– Automatic Trace will hide all irrelevant pins

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 Post process HDL
Example 1: Why Did That Signal Rise? waveform
inspection

• We’ll start with something simple

1.) Strongly recommend placing a

marker on the edge you are interested in
as it can be easy to lose track when
deep into driver tracing
Why did this push pulse happen?

3.)Right-click
3.) Right-clickonon
thethe signal
signal name
name and
2.) Place cursor on edge of
andselect
select “Go
“Go ToTo Cause”
Cause” interest
Recommend isolating the signal of interest in
it’s own target waveform window. You can then
add interesting contributors along the way

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 Post process HDL
Example 1: Why Did That Signal Rise? - 2 waveform
inspection

4.) Enable source

annotation

5.) Click the Signal

Tracing Sidebar for
guidance

Note that the time has changed

slightly from when we first started The cursor has changed time as a result of signal tracing activity!

our trace. (4) has been added to

the simulation time. More in this
in the next slide

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 Post process HDL
Example 1: Why Did That Signal Rise? - 3 waveform
inspection

How can all signals appear to be

rising in the waveform window, yet
my values are different for the
signals

Right Click->Expand Time Sequence will

show you sequence information (enabled
through the –event option to the database command)
Driver Trace time also
includes scheduler
Synchronizing waveforms to sequence times
source annotations requires a
bit of simulator scheduler
understanding
Moving the cursor slightly will change
annotated values in the source browser…
keep this in mind
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 Post process HDL
Example 1: Why Did That Signal Rise? waveform
inspection
- Back to our Tracing Task
Double click the rf_push
signal to trace its driver

You might choose to

You might choose to
Note that rf_push is investigate why this
investigate why this rstate
the highest ranked rstate
was set was set to
to sr_push?
contributor sr_push?

Note that nothing is

transitioning at this
point. Let’s investigate why
srx_pad_i was being
driven. Double click the
signal name.

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 Post process HDL
Example 1: Why Did That Signal Rise? - 5 waveform
inspection

Continue our trace by

double clicking the
srx_pad driver

Refrain from clicking in waveform window while

tracing signals as annotated source value will change,
The cursor has changed time as a result of signal tracing activity!
causing confusion

Cursor time changes and we

see the red flash to warn us

Note that we are now quite

a ways away from our
starting point in the
29 © 2020 Cadence Design Systems, Inc. All rights reserved. waveform window
 Post process HDL
Example 1: Why Did That Signal Rise? - 6 waveform
inspection

Continue our trace by

double clicking the
async_dat_i driver

Continue our trace by

double clicking the
flop_0 driver

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 Post process HDL
Example 1: Why Did That Signal Rise? - 7 waveform
inspection

Double clicking the pins to the

DUT will not show you any more
This driver is an input pin to the drivers. We are at the top level
top level DUT wires now.

Traverse up one
level
To continue your trace all the
Traverse down a
way up the hierarchy, right click-
level
>Follow signal.

• Answer: That signal rose because something was driving a 1’b1 on the txd
lines of the top level test harness.
– Perhaps take a closer look at the rstate variable from prev. slide?
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 Post process HDL
Example 2: Tracing Through a Memory - 1 waveform
inspection

1) Why was this particular value 2.) Place cursor on edge of

interest
driven on the data_out bus?

3.) Right-click
3.) Right-clickononthe
the signal
signal name
name and
and select “Go To Cause”
select “Go To Cause”

We see that the data8_out bus is

the only driver. Double click in
either the side bar or the Source
Browser
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 Post process HDL
Example 2: Tracing Through a Memory - 2 waveform
inspection

Where do we
go from here?

Looks like the only driver, dpo,

is being driven by a value in a
memory

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 Post process HDL
Example 2: Tracing Through a Memory - 3 waveform
inspection

Where do we
go from here?

Driver Tracing will not find the

drivers of a particular memory Next step would be identify
address. This is too when the value of interest was
performance intensive. being written into the memory.

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 Post process HDL
Example 2: Tracing Through a Memory - 4 waveform
inspection

2) Search for ram in the

Search for ram in the source
source
1) Click the search button

3) Identify which signal is driving the

input to the ram (di in this case) and
then send it to the waveform window

4) Highlight the di signal and then search for

the value of interest (from the previous slide)

5) Once you have found the value of

interest, continue your driver tracing from
here on the di signal

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 Post process HDL
Driver Tracing Limitations waveform
inspection

• If grading algorithms cannot determine driver, SimVision reverts to static driver tracing
• All signals in the trace path must be probed
• Read access is required for all signals
• Driver grading is not available at time 0
• Currently, variable delays are not supported, that is delays inside if, for or generated blocks
• Limited support for generate statements
• There is a time limit for the tracing operations, so if the algorithm runs out of time it will return
with an invalid trace path
• New data types added to System Verilog might not be supported.
– E.g. – Newly supported SV let construct

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 Post process HDL
Driver Tracing Tips and Tricks waveform
inspection

1. Use markers in the Waveform window to mark the start location of your Driver
Trace operation
2. Refrain from clicking in Waveform once you have started your Driver tracing
– Changing the cursor affects value annotation in all windows
3. Understand that the scheduler sequence time affects source annotation
– Look for bracketed numbers after the simulation time (e.g 34,567(5) ps)
4. Understand that Driver Tracing has limitations
– It is algorithmic and probabilistic in nature
– There will be times where the algorithm cannot predict the correct driver
– Human analysis will be required to provide further guidance as to next steps

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 Post process HDL
Additional Information waveform
inspection

• Please see these YouTube Videos for more information on Method 1 debug
features:
– YouTube:
– SimVision Debug Video Series Introduction
– SimVision Quick Introduction to the Major SimVision Windows
– SimVision Waveform Window Introduction
– SimVision Design Browser Introduction
– SimVision Source Browser Introduction
– SimVision Driver Tracing Introduction
– SimVision Automatic Driver Trace
– SimVision Signal Comparison using SimCompare

– Cadence Online Support (COS):

– You can refer to https://support.cadence.com – Resources – Video Library (Filter on “Indago Debug” Product)

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 Post process HDL
Probing assertions waveform inspection

• Users can probe assertions in several different ways

– If assertions are present in an already probed module:
– Assertion state as well as checked_count, finish_count, failure_count and disabled_count counters probed
– Contributing signals can be shown (if recorded and if snapshot is loaded)

– probe … –transaction …
– Records assertions as transactions only (will not record any additional assertion information) within the scope
– Will not probe any other signal at all … only transactions
– Can visualize start/end and pass/fail (colourization) of any assertion thread
– Visualize multiple threads of a given assertion (overlapping transactions)

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 Post process HDL
Probing assertions waveform inspection

– probe … –assertions …
– Only records assertion information (will not probe other signals) for the scopes in the probe command
– Assertion state as well as checked_count, finish_count, failure_count and disabled_count counters probed

– probe …-assertions -signals …

– Assertion state as well as checked_count, finish_count, failure_count and disabled_count counters probed
– Contributing signals also probed

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 Post process HDL
Probing assertions waveform inspection

– probe …-assertdebug …
– Records assertions as transactions
– Records also local variables

Local variable
num_cycles
contained within the
req_ack assertion

• There are other options to the probe command for assertions

– See the documentation for all details

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 Post process HDL
Additional Information waveform inspection

• Please see these Videos for more information on Method 1-2 debug features:
– YouTube:
– SimVision Debug Video Series Introduction
– SimVision Quick Introduction to the Major SimVision Windows
– SimVision Waveform Window Introduction
– SimVision Design Browser Introduction
– SimVision Source Browser Introduction
– SimVision Driver Tracing Introduction
– SimVision Automatic Driver Trace
– SimVision Signal Comparison using SimCompare
– SimVision Assertion Debug Introduction

– Cadence Online Support (COS):

– You can refer to https://support.cadence.com – Resources
– Video Library (Filter on “Indago Debug” Product)
– Rapid Adoption Kits (Filter on “Indago Debug” Product)

42 © 2020 Cadence Design Systems, Inc. All rights reserved.

 Lab1: Driver Tracing with the Schematic Tracer (X tracing)

Refer to Lab1-DriverTrace.pdf for more details. It can be downloaded from attachment section.

Note: There might be some issues if labs are decompressed/untar in Windows OS. To mitigate this, request is
to decompress/untar the labs in UNIX/LINUX.
43 © 2020 Cadence Design Systems, Inc. All rights reserved.
 Post Process
A Word on Post Process Class Based Debug HDL/HVL waveform
inspection

• Many users prefer traditional post process debug

• Dynamic data types introduce differences in the way data is displayed to the
user in post process mode
– A single class can be randomized many times during a simulation
– Internal variables can be resized
– New object handles created
– SimVision provides innovative visualization capabilities around debug of dynamic data in post
processing mode
• In post-processing mode you have access to a number of debug tools, including
(but not limited to):
– Waveforms, Source Browser
– Design Browser (hierarchy navigation)
– Transactions and Transaction Stripe Chart
– Class Browser
– Value annotations

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 Post Process
Probing HVL Objects HDL/HVL waveform
inspection

• Probing HVL objects allow for debug at several levels of abstraction

– HDL signal level
– Transaction level
– Testbench level
• In order to debug at transaction/class abstraction levels
– Need a simulator that can record transaction/class activity
– Need a debugger that can visualize signal/transaction/class activity in an intuitive manner
– Easy correlation between all levels of abstraction to get the full big picture
• Dynamic data types introduce visualization differences
– Single class can be randomized many times during a simulation
– Internal variables can be resized (queues, arrays)
– New object handles created
– Modern EDA debuggers provide innovative visualization capabilities for post process debug
of dynamic data

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 Post Process
Transaction recording HDL/HVL waveform
inspection

• Transaction recording is built in for UVM Sequences

– No need to use the Cadence UVM library
– Must be enabled Note: Need to include
the cdns_uvm_pkg
– Easiest way to enable transaction recording for all objects package if not using
Cadence Library
– uvm_set [–config] * recording_detail UVM_FULL

Built-in UVM Use only if calling

UVM component
command for prior to build Field name value
name
configuration phase

• Transactions can be used for more than just UVM Sequences

– Can display function/task calls in the waveform
– Display collected packets/transfers in monitors
– Assertions (as we’ll see later in this section)

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 Post Process
Transaction Recording Visualization HDL/HVL waveform
inspection

• What you’ll get: Sequences and sequence item

visualization in waveform for
correlation to signal/class activity

Exploration/filtering of
sequence information

– Waveform visualization

– Stripe Chart visualization

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 Post Process
Probing UVM Hierarchy HDL/HVL waveform
inspection

• Probing the entire UVM hierarchy

– probe -create -database waves uvm_pkg::uvm_top -all -depth all

• Probing only a single UVC

– probe -create –database <db name> <top_level>.<UVM test
name>'(worklib.uvm_pkg::uvm_top.top_levels[0]).<hierarchical path>
-depth all
– Example from the lab environment:
– probe -create uart_ctrl_top.uart_bad_parity_test'(worklib.uvm_pkg::uvm_top.top_levels[0]).uart_ctrl_tb0.apb0 -depth all

• Users must request UVM base class fields via the –uvm switch
– Example probe -create -database waves –uvm uvm_pkg::uvm_top -all -depth all

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 Post Process
Visualizing the UVM Hierarchy HDL/HVL waveform
inspection

• Before navigating the UVM hierarchy, the debug database must be loaded
– Snapshot/Lightweight debug database must be loaded before sending to the waveform
– Otherwise you may not be able to expand sent items
• Use the Design Browser window to navigate the UVM hierarchy
3 - Can then select
any object and send
to waveform or use
Ctrl+W
This contains the
transaction hierarchy
only (when 2 - UVM hierarchy
debugging offline) will be displayed in
the Data Members
pane

1 - Click on the
uvm_top item to
view the UVM
hierarchy
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Post Process Class Based Debug – Post Process
HDL/HVL waveform
Waveform Representation inspection

Click “+” to
create new
Hover to bring up detailed group for this
Changing Class
info in tool tips transaction
Handles
Dynamic Class

Internal fields
changing

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 Post Process
Visualizing the UVM Hierarchy HDL/HVL waveform
inspection + log file

Fields of the
uart.tx.driver
UVM Component

Fields of each
UART frame
driven

Transaction View
of UART
sequences

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 Post Process
Visualizing the UVM Hierarchy HDL/HVL waveform
inspection + log file
Tips and Limitations
• Tips and tricks:
– Visualizing UVM Based classes in PP requires setting a preference (Edit->Preferences)

– Must have this preference set prior to sending to the waveform

– Items already added to the waveform will not be updated to show/hide UVM base class information
• Limitations
– Debug database must be loaded to see dynamic objects (including queues) in Post Process
– Class is added to the waveform as a indivisible group
– Cannot delete specific signals from waveform window
– Workaround: be selective when sending items from Design Browser
– Design Browser Objects pane is the only window that displays entire UVM hierarchy

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 Post Process
Sequence Debug HDL/HVL waveform
inspection

• By default, req/resp UVM base class fields of driver components are recorded
– As are the m_parent_sequence fields
• Using these fields alone, it is possible to walk up the sequence tree to
understand the sequence structure
– Keep walking up through the sequences until you encounter a sequence whose
m_parent_sequence is null
• Generally, it is much faster to use UVM transaction recording for sequence
analysis however, there are some benefits to using this approach
– Can start from the req field and work upwards
– Using transactions users generally start at the sequencer and work downward
– Parent class handles displayed
– Parent class names displayed
– Associated sequencer type name displayed

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 Post Process
Traversing through parent sequences HDL/HVL waveform
inspection

3 – Information about the

1 – Locate the 2 - Hover over the parent sequence displayed
m_parent_sequence value for the req of in the pop up (Name, class
field of the driver.req interest to open pop up handle, fields)

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 Post Process
UVM Sequence Debug HDL/HVL waveform
inspection

7 – Information about the

4 – Expand the parent sequence displayed
m_parent_sequence in the pop up (Name, class
field of the driver.req handle, fields)

5 – Locate it’s
m_parent_sequence

6 - Hover over the

value for the req of
55 © 2020 Cadence Design Systems, Inc. All rights reserved.
interest to open pop up
 Post Process
UVM Sequence Debug HDL/HVL waveform
inspection
The easy way … with transactions Parent sequence names
are in the transaction
stream name

u2a_bad_parity_vseq
sends the rd_rx_fifo
Select the sequence, which sends
sequencer of interest req

Select the
transaction stream of
interest and send to
Waveform

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 Post Process
Important Debug Needs HDL/HVL waveform
inspection
Probing simulator scheduling … also valuable for dynamic UVM objects

UVM Build
phase occurs
UVM at time 0
Hierarchy
displayed in
the
waveform
window

Can see Can see objects

objects being being assigned
declared class handles

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 Post Process
Important Debug Needs HDL/HVL waveform
inspection
Queue Visualization

Can see queue

elements
pushed/popped
over time

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 Lab2: Post Process Debug

Refer to Lab2-PostProcessDebug.pdf for more details. It can be downloaded from attachment section.

Note: There might be some issues if labs are decompressed/untar in Windows OS. To mitigate this, request is
to decompress/untar the labs in UNIX/LINUX.
59 © 2020 Cadence Design Systems, Inc. All rights reserved.
 Post Process
Additional Information HDL/HVL waveform
inspection

• Please see these Videos for more information on Method 1-3 debug features:
• YouTube: • Cadence Online Support (COS):
− SimVision Quick Introduction to the Major SimVision Windows • You can refer to
− SimVision Waveform Window Introduction https://support.cadence.com – Resources
− SimVision Design Browser Introduction – Video Library, Application Notes and
− SimVision Source Browser Introduction Rapid Production Kits (Filter on “Indago
− SimVision Driver Tracing Introduction Debug” Product)
− SimVision Automatic Driver Trace
− SimVision Signal Comparison using SimCompare
− SimVision Assertion Debug Introduction
− SimVision Class Browser Introduction
− SimVision Class and Transaction Based Debug
− SimVision Transaction Stripe Chart Introduction
− SimVision UVM Debug Commands

60 © 2020 Cadence Design Systems, Inc. All rights reserved.

SimVision Debug RAK

Post Processing Mode(Inspection of HDL Waveforms()

Interactive Debug (Single stepping and break points)

Summary

61 © 2020 Cadence Design Systems, Inc. All rights reserved.

The Debug Methodology Scale Interactive Debug

Code

Online
Simulate
Debug

Re-run
(set break
Automated Pass
point) Fail Status

Done
Inspect

62 © 2020 Cadence Design Systems, Inc. All rights reserved.

Setting breakpoints Interactive Debug

• Can set breakpoints to target focus areas

– Set a breakpoint shortly before an error scenario, then step forward to the failure
– Can set conditional breakpoints (time, line, signal changes, instance, etc.)
– Allows users to stop execution at a precise point of interest
– Productivity boost in that you can start debug very close to failure point

Right click on line

number or within
margin to set
breakpoint

63 © 2020 Cadence Design Systems, Inc. All rights reserved.

Important Debug Needs Interactive Debug

Conditional breakpoints

• General line breakpoints are often not enough to hone in a problem

– Single line of code may execute 100’s of times in a simulation
– There could be many instances of a given object
– RTL blocks
– Classes in the TB (several instances of a given UVC)
– Single line may execute 100’s of time at a specific point in time
– For/while/repeat loops

• Setting the right breakpoint requires a thoughtful approach

– Examine the log file to extract any contextual information
– Open source files to examine context surrounding the situation you would like to debug
– If you are not able to isolate the problem enough, several breakpoints might be needed
– Enhanced printf() debug

64 © 2020 Cadence Design Systems, Inc. All rights reserved.

Most Common Types of Breakpoints Interactive Debug

• Time based
– Stop the simulation on a specific line of code if we have reached a certain time
• Value based
– Stop the simulation on a specific line if ever a specific set of signals take on a desired value
• There are various ways to access the source files for setting breakpoint
– Design File Sidebar:
– If you know the source file name or only need to set a time based breakpoint
– Design Browser:
– If you know the specific instance in the hierarchy or you would like to set a Value based breakpoint

• Though not as common, you can set a breakpoint from several other locations
within SimVision
– Watch window, UVM Sequence Viewer, UVM Register Viewer, etc.

65 © 2020 Cadence Design Systems, Inc. All rights reserved.

SimVision Conditional Breakpoint Setting Interactive Debug

Most common breakpoint type

• Time Based
– Break on a particular line of code after a
certain time has been reached
– RMB in Source Browser Margin

Click to enable Enter a time after which Choose

time based the breakpoint will be time units
breakpoints enabled

TCL stop command is

output in the SimVision
console.

66 © 2020 Cadence Design Systems, Inc. All rights reserved.

Advantages of SimVision Interactive Debug Interactive Debug

Single Stepping
Step control toolbar
• Single stepping allows users to
run code in a controlled manner
– Access to all simulator data is a huge
productivity boost for debug
Source annotations
– Can explore on the fly
available without
– Can examine the context of every probing
line executing
– Can examine all variable values at
the current simulation time
– Can selectively probe items of
interest on the fly
– Step within the current thread, within
all threads, into methods

67 © 2020 Cadence Design Systems, Inc. All rights reserved.

Call Stack Debug Interactive Debug

• Very important for debug of procedural code

– Understand exactly why a method was called
– Can walk back through all frames, including TLM port connections
– Very important for many to one connections

Call stack shows how the

current executing method
came to be called

Can click on any level of

the stack to be shown
source code line of the
calling method
68 © 2020 Cadence Design Systems, Inc. All rights reserved.
Translating the call stack uart_ctrl_rx_scbd.
write_abp()

UVM analysis port

connection

uart_ctrl_monitor.
write_abp()

UVM analysis port

connection

apb_monitor.
write()

UVM analysis port

connection

apb_collector.
collect_transactions()

apb_collector.
run_phase()
These numbers
identify “frames”
within the stack UVM phase control stuff

69 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” analysis Interactive Debug

• Allows users to modify variables values on the fly

– Force: Apply a value to a signal and hold it until further notice
– Deposit: Apply a value at the current time, hold until another driver applies a value
• If used with save/restore:
– Save state -> modify value -> simulate->restore previous state -> repeat
• Can inject error scenarios
– Driver protocol incorrectly to ensure checkers are working
– Corrupt a payload bit of a packet to verify that scoreboard detects it
– Writing to an invalid address
• Can manually test out potential fixes
– Can ‘correct’ the code while it is executing, then make the source change later
– Examples:
– What if this function returned 8’hAA instead of 8’hBB?
– What if reset was held low for a few more cycles?

70 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Interactive Debug

Creating forces
• Forces can be applied to HDL objects
– Typically done through the right click option of the Waveform or Source Browser windows

Forcing a value
causes the
variable to retain
this value until
the force is
released

71 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Example Interactive Debug

Targeting an invalid register address using a deposit

• Good simulation = all registers programmed correctly at startup Addresses in valid

range

• Lets see what would happen if we attempted to write a register at address

32’h12345678 instead of 32‘h00000003 …

72 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Example Interactive Debug

Targeting an invalid register address using a deposit

1. Run the simulation interactively with SimVision
2. Set a breakpoint at the point where the address is driven onto the DUT Interface
3. Run to encounter the breakpoint

73 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Example Interactive Debug

Targeting an invalid register address using a deposit

4. Find a reference to the input trans and send to a watch window

Notice that the fields are

italicized. You cannot
deposit at this level. If
you try, you will get an
error in the deposit
dialog

74 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Example Interactive Debug

Targeting an invalid register address using a deposit

5. Walk up the call stack to find the class that instantiates the input trans field
6. Send that object to the watch window

Notice that the fields are

not italicized. You can
deposit at this level.

75 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Example Interactive Debug

Targeting an invalid register address using a deposit

7. Right Click on the addr field in the Watch window and select “Deposit Value”

76 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Example Interactive Debug

Targeting an invalid register address using a deposit

8. Enter the new desired value in the Deposit dialogue box and click OK
9. New value appears in the watch window

77 © 2020 Cadence Design Systems, Inc. All rights reserved.

Interactive “What if” Analysis Example Interactive Debug

Targeting an invalid register address using a deposit

10. Run the simulation and you will see your new value being driven
– You may want to delete your breakpoint

OLD SIGNALS

NEW SIGNALS
78 © 2020 Cadence Design Systems, Inc. All rights reserved.
Advantages of SimVision Interactive Debug Interactive Debug

Constraint Debug

• Constraint Debug
Run randomizer
– Advanced “what if” analysis
allows users to add/remove Add a
constraint
constraints interactively through TCL
– Can see all variables and
constraints involved in
randomization issues
– Cross selection with source Class Enable/Disa Applicable
code members ble constraints
and values constraints

79 © 2020 Cadence Design Systems, Inc. All rights reserved.

Advantages of SimVision Interactive Debug Interactive Debug

Simulation Cycle Debug

• Simulation Cycle Debug

– Delta cycle debug
– Helpful for debug of 0-delay
errors
– Debug event ordering issues
– Debug of race conditions
– Helpful for glitch debug

80 © 2020 Cadence Design Systems, Inc. All rights reserved.

Advantages of SimVision Interactive Debug Interactive Debug

Command Line Debug

• Command Line
Debug
– Simulation control
– Available in batch or GUI
mode
– Query object/signal
contents and values
– Quick printing to the
screen/Console
– Print drivers of signals
– Set breakpoints

81 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Debug Challenges - 1 Interactive Debug

• Hardware Verification Languages (HVL’s) are more complex than HDL

– Polymorphism
– Object partitioning (header files)
– Randomization
– Coverage
– Assertions
– Automated Self Checking

• UVM brings even more complexity to the picture

– Base class library not written by the user
– 360+ macros utilized for various reasons
– New methodology to learn

82 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Debug Challenges - 2 Interactive Debug

•Sequence Debug
•Configuration Debug
•UVM register modeling
•Heavy macro usage
•UVM base class inheritance
•Phased execution
•Factory overrides
•Objections

UVM Debug
Challenges

• Let’s take a look at each of these topics a little more closely

83 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Debug Challenges Interactive Debug

Sequence based stimulus generation

• Sequences can be very complex chains of procedural code

– Can involve conditional execution, segmentation/reassembly, constraint solving, arbitration, ,
interrupt handling, loops, etc.
• Many sequence in flight on several sequencers at any given time
• Problems typically surface due to a low level sequence item triggering a failure
– To debug, we often must start from the sequence item and work our way backward through
parent sequences
item1

sequenceB item2
sequenceC
item3
sequenceA
item4 Error traced to
sequenceD sequenceE this sequence
item5 item being sent
sequenceF item6
Problem
Problem can be be
can probably
Problem can be isolated to
isolated
isolatedto
to one ofthese
one of these
one of these locations item6
locations?
sequences
84 © 2020 Cadence Design Systems, Inc. All rights reserved.
SimVision UVM Sequence Debug Interactive Debug

Sequence based stimulus generation

• For effective debug:

– Need to able to easily navigate the sequence tree
– Need to be able to get a full picture of the state of each sequence
– Need to understand what each sequencer is sending in the environment
– Need to be able to set breakpoints and step through the execution of sequence body() code
• New Sequence Viewer window supports multiple debug use models
– Exploration of sequences running on a given sequencer
– Understanding the sequence hierarchy for any given sequence item
• Window has several key panes Can launch the UVM
Sequence Viewer through
– Sequencer hierarchy the UVM Toolbar drop
– Sequence hierarchy down or the UVM menu in
– Sequence data any SimVision window

– Sequence Type List

85 © 2020 Cadence Design Systems, Inc. All rights reserved.

 UVM Sequence Viewer - 2 Interactive Debug

Rapid debug of sequence based stimulus

Sequence Hierarchy Pane displays
info on sequences and sequence
items. Nesting to show parent/child
relationship

Sequencer hierarchy
within the UVM
environment

Sequence Data Pane

displays user defined
data fields for selected
items
86 © 2020 Cadence Design Systems, Inc. All rights reserved.
 UVM Sequence Viewer - 3 Interactive Debug

Rapid debug of sequence based stimulus Can jump to the parent or Indicates whether item
Indicates the
sequencer that the
the root sequence is in flight or finished item belongs to

Double click of
any item opens
When items source in-scope
selected,
sequencer is
bolded

Find box to easily search

within the hierarchy

87 © 2020 Cadence Design Systems, Inc. All rights reserved.

 UVM Sequence Viewer – 4 Interactive Debug

Easy navigation to parent/root sequence

3) Click
“Jump to
Root”
Sequence

2) Notice we
are at the
apb0 master
sequencer

1) Select
sequence or
sequence
item

88 © 2020 Cadence Design Systems, Inc. All rights reserved.

 UVM Sequence Viewer – 5 Interactive Debug

Easy navigation to parent/root sequence

4) Shows that rd_rx_fifo

3)
sequence
sequence
is being
is actually
sent by
the
being
u2a_bad_parity
sent by the virtual
virtual
sequencer
sequence

4) Hierarchy
jumps to
virtual
sequencer

89 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Sequence Viewer - 6 Interactive Debug

Extensive RMB menu operations

Extensive
RMB Menu

Copy path to selected

item Expand/collapsing items

Navigation

Filtering

Can send items to other

SimVision windows

Sequence-specific
breakpointing

90 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Sequence Viewer - 7 Interactive Debug

Sequence Types Pane

• New Sequence Types pane allows users to quickly analyze all sequence types
Click the Sequence
– Shows how many of Types Tab to view
List of types currently in
each sequence and existence
sequence item exist at
current simulation time
– Can filter UVM base
sequences away
– Can filter sequences
and sequence items
that do not have
instances
Can see all members

Can filter on name, UVM

base classes and zero-
count sequences
91 © 2020 Cadence Design Systems, Inc. All rights reserved.
UVM Sequence Viewer – Use Model Example Interactive Debug

Moving from Source to Sequence Viewer

• Users can now send any sequence based stimulus to the Sequence Viewer
– RMB -> Send To UVM Sequence Viewer

Can see the

entire chain that
Sequencer led to up to the
Req
Highlighted item of interest
(apb_transfer)
is part of a
sequence

RMB
Selection

Sequence
Hierarchy
expanded with
item selected

92 © 2020 Cadence Design Systems, Inc. All rights reserved.

Important Debug Needs Interactive Debug

UVM Configuration Debug

• Configuration debug can be quite challenging

– Need to understand why calls to set(..) did not take place
– Need to identify risks such as set(..) with no matching get(…) calls
– Need to understand precedence to identify which set(..) calls override others
– Need to quickly navigate through the set()/get() calls within the source code

• A set(…) call has several inputs:

– uvm_config_db#(virtual apb_if)::set(null, “uvm_test_top.apb0*”, “vif”, apb_if0);
instance
type of property context (used field/resou value
name
you are to help set rce* name
configuring precedence)

• A get(..) call has similar inputs

* = name used in Config Viewer
93 © 2020 Cadence Design Systems, Inc. All rights reserved.
UVM Configuration Debug Interactive Debug

• Fields within the environment can be overridden within the configuration

database from several locations
• Can lead to confusion as to why a field was set to a particular value
• For effective debug:
– Need to be able to query the configuration database
– Need to be able to identify why a field received a particular value
– Need to identify locations in the code that configure particular fields
• New UVM Configuration Viewer helps users debug configuration issues
– Component and Resource Name views
– Identifies set() with no get() situations
– Identifies get() with no set() situations
– Identifies resource name mismatches (typically typos where a component cannot be found)

94 © 2020 Cadence Design Systems, Inc. All rights reserved.

Important Debug Needs Interactive Debug

UVM Configuration Debug

UVM
component
hierarchy Individual set()/get() calls
Resources affecting
for the resource
selected component

Clicking on
Clicking on a
a
resource
resource access
access
takes users directly
takes users directly
to
to the
the source
source code
code

95 © 2020 Cadence Design Systems, Inc. All rights reserved.

Important Debug Needs Interactive Debug

UVM Configuration Debug

Clicking a
Resource resource shows
Names tab all entries in the
resource DB

No matching
components
Number of
set()
entries in the
with no
config DB RMB Menu show
get()
all components
affected by this
resource call

96 © 2020 Cadence Design Systems, Inc. All rights reserved.

Important Debug Needs Interactive Debug

UVM Configuration Debug

• Straightforward and easy to use

–Interactive use model:
– Start the simulation in GUI mode
– Open the UVM Configuration Viewer
– Click the record button in the Toolbar
– Click the UVM build button in the Toolbar
– Once the build occurs, you can now begin analysis/debug
–Scripting use model:
– In a .tcl file, include the following two lines before you build the UVM environment
– TCL script to source: <path to install>/tools/simvision/files/util/simvis_uvm_config_record.tcl
– TCL command name to launch: simvis_uvm_config_record

97 © 2020 Cadence Design Systems, Inc. All rights reserved.

SimVision UVM Configuration Debug Interactive Debug

UVM Toolbar configuration database printing

• In addition to the UVM

Configuration Viewer, there are
several options in the drop down
– Dump
– Dumps configuration database
– Trace ON/OFF
– Print read/write information
– Audit ON/OFF
– Prints get/set information

• All information printed to screen

98 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Register Debug Interactive Debug

• UVM_REG allows SystemVerilog users to model DUT registers

• vr_ad allows e users to model DUT registers

• For effective debug:

– Need a way to visualize the entire register space together in one window
– Both SystemVerilog and e models should be accessible for debug
– Register block hierarchy needs to be displayed
– Need to visualize register/field names, register sizes, values, access policy
– Ability to set breakpoints on changes in any register
– Value change or call to read(), write(), update(), mirror()
– Access source code for any register easily

99 © 2020 Cadence Design Systems, Inc. All rights reserved.

SimVision UVM Register Viewer Interactive Debug

Register Hierarchy
(maps/blocks) – e or SV Registers Register Values
and Fields

Access Type

Values
currently
changing

Find Filtering

100 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Debug Challenges Interactive Debug

Heavy macro utilization

• Macro usage is very common in today’s SystemVerilog Testbench methodologies

– In all, there are approximately 360 macros that exist within UVM
– Approximately 100 are utilized often by users

UVM field
automation
macros

• Macros are becoming increasingly more common within RTL code as well

101 © 2020 Cadence Design Systems, Inc. All rights reserved.

Effective UVM Macro Debug Solution Interactive Debug

• For effective Debug of Macros:

– Macros need to be expandable inline
– Expanded macros should retain original formatting
– Must be able to identify/expand/collapse nested macro code
– Must be able to view annotated values for all macro variables
– Need to provide users with quick access to macro source code file

102 © 2020 Cadence Design Systems, Inc. All rights reserved.

SimVision Macro Debug Solution Interactive Debug

Macro is expanded
inline with background
to indicate expanded
macro code
Source
Hover to see + annotations
sign for
expansion

Tool tip shows a sample of

the macro and the original
Source File
103 © 2020 Cadence Design Systems, Inc. All rights reserved.
UVM Debug Challenges Interactive Debug

UVM base class inheritance

• Most of the base class functionality provides much needed automation to the
SystemVerilog Language
– e has most of the automation built-in hence, smaller base class
• Most information contained within base classes is not needed by users
– Some fields are useful for debug though:
– m_parent_sequence: The parent sequence of the current sequence item
– m_sequencer: The sequencer that this sequence is being sent on
– m_name: Hierarchical location of this class within the environment
– m_parent: The parent of the current class

104 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Debug Challenges – Interactive Debug

UVM base class inheritance

• For effective debug:

– Should not be distracted by inherited UVM fields
– Should be able to easily access desired UVM fields on demand

– Should be able to identify inheritance relationships easily

105 © 2020 Cadence Design Systems, Inc. All rights reserved.

 Phased Execution Interactive Debug

• UVM provides built in phasing

• Users can extend each phase to add custom functionality
• Perhaps the most important phase is the build phase
– All objects in the verification environment are constructed
• For effective debug:
– Need to be able to understand what is happening during each phase
– Must be able to stop at the beginning/end of any phase
– Must be able to stop on any user extension of any phase
– Need to be able to query the phase at any given point in the simulation

106 © 2020 Cadence Design Systems, Inc. All rights reserved.

 SimVision UVM Phase Debug Interactive Debug

Run to end
of connect

• SimVision UVM Phase

phase

debug
– Can set breakpoints to
stop at any UVM Run to Break
– Can explore the next on UVM
environment after a phase phase
phase executes
– Example, after build phase to
ensure environment is
constructed
– Can set breakpoints and
step through any custom
user code
– No wasted simulation Query UVM Phase
cycles from command line

107 © 2020 Cadence Design Systems, Inc. All rights reserved.

UVM Factory Overrides Interactive Debug

• Classes can be overridden by derived class

• Can lead to confusion when debugging
– User expects one class/behaviour, but got another
• For effective debug:
– Need to understand what overrides occurred for any given test
– Need to understand where, in the codebase, the overrides are

108 © 2020 Cadence Design Systems, Inc. All rights reserved.

SimVision UVM Factory Debug Interactive Debug

UVM toolbar factory printing

• Print UVM Factory information to

the ncsim console
– Instance/type overrides
– Registered classes

Info on instance
and type
overrides

Registered
types

109 © 2020 Cadence Design Systems, Inc. All rights reserved.

Controlling End of Test (Objections) Interactive Debug

• Objections are the democratic way to control end of test

• Users must control the raising/dropping of objections
– Leads to situations where an objection was raised, but not dropped
– Also leads to situations where no objections were raised at all

• For effective debug:

– Need to easily access the objectors to any given phase
– Need to understand hierarchical location of objectors in the env
– Need to be able to trace objections being raised and dropped

110 © 2020 Cadence Design Systems, Inc. All rights reserved.

SimVision UVM Objection Debug Interactive Debug

UVM Toolbar Objection printing

• Prints objections to the simulator

console
– Current: Currently executing phase
– All: Objections for all phases printed

111 © 2020 Cadence Design Systems, Inc. All rights reserved.

 SimVision Interactive Class Based Debug – Interactive Debug

Knowing what tools are available to you

• UVM Verbosity Levels
SimVision has so • ‘Enhanced’ Log File Analysis
many debug
features, where do Yes
I begin? • Inherited Properties
Messaging?
• Design Browser UVM awareness (icons,
hierarchy)
• UVM Toolbar
• UVM Debug Commands
Trans.
Yes
recording?

Yes • Waveform Transactions

UVM?
• Transaction Stripe Charts
No
UVM Register Viewer
The “Basics”
• Class Browser
UVM_REG?
• Design Browser
Yes
• Watch Window
• Design File Search
• Source Browser (stepping,bp’s) Yes
• Call Stack Sidebar Yes Sequences?
• Waveform Window set()/get()?
• SV Data Browser
• Command Line • UVM Configuration • UVM Sequence Viewer
112 © 2020 Cadence Design Systems, Inc. All rights reserved. Viewer • Transaction Stripe chart
Additional Information Interactive Debug

• Please see these Videos for more information on Method 1-4 debug features:
• YouTube:
• Cadence Online Support (COS):
− SimVision Quick Introduction to the Major SimVision Windows
• You can refer to
− SimVision Waveform Window Introduction
https://support.cadence.com – Resources
− SimVision Design Browser Introduction
– Video Library, Application Notes and
− SimVision Source Browser Introduction
Rapid Production Kits (Filter on “Indago
− SimVision Driver Tracing Introduction
Debug” Product)
− SimVision Automatic Driver Trace
− SimVision Signal Comparison using SimCompare
− SimVision Assertion Debug Introduction
− SimVision Class Browser Introduction
− SimVision Class and Transaction Based Debug
− SimVision Transaction Stripe Chart Introduction
− SimVision UVM Debug Commands
− SimVision UVM Toolbar and Messaging Hyperlinks
− SimVision UVM Register Viewer
− SimVision SystemC/C/C++ Debug with HDL
113 © 2020 Cadence Design Systems, Inc. All rights reserved.
 Lab3: UVM Sequence Debug (NULL Pointer Issue)
Lab4: UVM Scoreboard Failure (Packet parity mismatch)

Refer to Lab3-UVM_Seq_Debug.pdf and Lab4-UVM_Scoreboard_Failure.pdf or more details. It can be

downloaded from attachment section.

Note: There might be some issues if labs are decompressed/untar in Windows OS. To mitigate this, request is
to decompress/untar the labs in UNIX/LINUX.
114 © 2020 Cadence Design Systems, Inc. All rights reserved.
Access and Download RAKs from Cadence Support Portal
https://support.cadence.com

• RAK database and references can be found at ‘Attachments’ and ‘Related

Solutions’ sections below the PDF.

• This RAK pdf can be searched with the document title on

https://support.cadence.com

115 © 2020 Cadence Design Systems, Inc. All rights reserved.