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DLCD Lab Practical File

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DLCD Lab Practical File

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ad599066
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© © All Rights Reserved
Available Formats
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BHARATI VIDY APEETH'S COLLEGE OF ENGINEERING A-4, PASCHIM VIHAR, NEW DELHI - 410063 CERTIFICATE This is to Certify that Mr./Miss.... FARA... KAT. eeceeiseereres palt No, 2lsitia leis lola TREE) ranch. CSET A oeeeeee Digttal Logic. owl. Computer, Bmiqn. = AB. subject Professor Head of the Department Date Incharge Ld EXPERIMENT -4 ____ Date 1904 | 2022 Ps Implementation 4 Adder ctreuit ty Logisinn REQUIREMENTS & THEORY Addin : 4 ductyonics an addin ty digited. cieawlk thot _pujorms addition of mumbens . dr Modern computers adden yesides th the Avithmetic Logic Unik CALLS Addevs ant importank not oly ty tha computor bak ramet data au _procened also _jx_many ‘per digital atone uid the Adden 4) | Adsen 2 Tht half “adden accepts two bir digits Len it’s Mputs and produce two binary digits outputs. a_sum bk ad a bur Th half adden an example _q a simple tional, digitad civeutt built from tuo logic gates . The half adden _adde to ons -bit bi output fo tw sum _q the tus __cansut ce. numbouw (AB). Ta two bits sum (5) and (CLASSTIME) eo + Tha Inputs to Imputs +o te AND gste . geke_j tun, wher _vottage of tas _XOR. gee ana Ain ved te sant voltage . Trt _expeenionn obtains ae: Tht same two Mputs divected to two | dif ere OR, gpte ant aloo tne Tha input “ wives” to we KOR gee ane. tid to the input wives of 148 AND & apple to me A input pur to te AND _gete mane! CIRCUIT DIAGRAM 3 1) HALF ADDER t A HALF ABDER ° | coany (©) - fos) ——7 TRUTH - TABLE 3 B [Sw _ |Comy out Ofo] Oo] CO! oft} 2 | Oo Jt Jo}; 4 Oo J a{4}]o 4 2) Ful AMER t aeoai . - By A e— For. Lg gm ee peR cme Cowy * Cony U . uk Teta . TABLE: A] 6 feng tn [sum leony out o fof o ° ° oO i BRO FO. or RP BO ole BRO RIO Beep ae ko wy Title - Date __ Page _ 2) | Full Adder: The WU adden accepts two inputs bits ard an input canny and qgnuraker a sum _oukput | and an output . - The fuse adden _addo three ann - bik beinony numb ow CA,B Cin) and outputs two om bit bow nunbuw a@ Sum (S) and a comy Ccouk) - Tra pull adden _& una lly ia a compo th a cancade gf ddens uidt addin _ c 3, 16,32 eke _binorwy nambuv - Dj Te__full adden is simply two half adden fered by an OR. _ D | We on implement a adden__civeusif with hulp of two holf adden etre ~Tr__first rat adden wil be woe tp_add A and RB to produce a portiol sum - Tha _ econ hos adchen logic can be uth to ath Cnr to the sum produced by the fist olf adden to get : te fra $ output. 4 awy of tre adden togic Je produces a cau Hur wil oe ar output SAN Tus Cout wil be an oR dunction of Hee holt _ adden Corut Outputs - Ths __ eprom _aotainud aw +: a S= A® B® Cu Cok = AB + BCin + CinA RESULT $ Te chy 9 add and Full adder have been studied ard Vo truth tables wena verified. : a OUTPUT : HALF ADDER OUTPUT : HALF ADDER * Title Date 16/16 | 2022, _ Pape. Erie 2 AIM 2% dele ord tnplemert _biary parcthel adden ciruit th Logfsim REQUIREMENTS = Logtsirn. _Saftsoant THeorRyY 3 Pavalleh Adder _ mp) Hb a dualt enisting of yAfull adders rat will adh no vte bivany number - ae >| Tat output consists of n sum bits and a covry bit. D | Compal of one pu adder & conneckeA 0 Cinput Ps nok full aden Structure gi favallel Adder ; - ) | A paratheh adler» wonning out _a__ card & 4 sour Jott accor D| Te wmbu_g ful adders wd will dapurd on fe _vunioer_ of ofts in tt binary digits union vequive to be added = - SoH dagrrn gf vente bingaay/ porate adder win a “ncbit bing rumbet & added to anotwin , each column quicnates a sum Sok a Oo 4 comy to tht not higher - ersten column. PROCEDURE = a +) | Tae bits au added with full _adclen oe » Starting frown tre heat sifarficont position (Ls8) to form me cum ord cous > | The _inpuk & Cin tm 8 fesat_ significant position rmusst M3470 > | Tax value of Cing_‘b_a_givern significant portion ths _oukpul Cou of tre fu adler, a CUSSTINEY) Tain value to Darejnred into tee typ uk conn Con of Ws fal Bain BN bh AL So po odie db th Four Fou FULL Fu Cog Ga, ton) ADDER (ine, ADDER gr Ge ADDER | Cin aq eet Ig } | | i l ' ’ t Sn Sa Se Se BLOCK wf OF Ne bit BINARY PARALLEL ADDER Dernonatvation ms A®= 1010 , B= teat até 1010 guecret [3 [2 | 2 O Trpus ony }° L ° ° ce [Auge (AY | L o {1 (0 At Addurd (8) 1 ° 1 i 4 | Br | on ° t fo |2 Js | Output | “I | pad 4 | oO 1 | S av Title “Date. - Page adden thal odd> tu tts ae _ighr _siquipicamt position to the hoff - oe » | The son bits an tho stenting from to. cst position ord ot ayatlable aa toon on tet _cowmpordlig prevtows _comy bit _& guwoled, RESULT 2 | Tae chreuik of a _Y- bite oinany Addin hao bean studied ¢ Ray and it’s outess haa ben venijied OUTPUT: 4-bit Binary Adder ce Date) 19/ 22 Pape — —_EXPERIMENT ~ 3 nim 2 aia se inploment _g_sutetvactor veut in Loy REQUIREMENTS 5 Logisim _sytoene THEORY 3 ceeeeeneeee I Subtractey ; tm dudironts a subtvacoy to digital circu tok pelorme _ subtvaction of _numbuw + sublyactoyS ont oh == vod in eectronke a oo welt ao digital devicer (ype g Sustractor_t 4) | Hast Subtactey 3 4 & wed for sulstrocting _ one ingle Bit single bie binary numour | ena number from _@noten & ralees wo inputs oO nee (AY and suotvahond le) and two culpurs Le Diffrmnce (> and Borrow (Bout > + Thos subtvackor te destgned. with uu _retp gfe ‘ i 2- ipput And. gett nig, input | fotrowing fogic gokee Wi) mot gate Exousive - OR “spi ov Yor gate _ and Taya diferwrer bit (DD ig ted with tu help _ tre KOR gate anh hs _ Bowvow bit (Bour) gprnakek _ wilt L_hdp_f a NOT aad ANID _goKe —_ rom Tak twat table and Ko rep, can be derived a0 3 ee Booka _ A [wr oviguwnee() A> \, SUBTRACTOR . ' | FoR > 2 vpere L ° ®) ° rad | 8 | © Boned (Goat) | — (oe | ee) eset TARE fF | | quuce | emo on fo (et) one | vey (Bout) ©.0| 0 ° Hentai 40 L Ce Loo | 11) 0 ° 2) Fur TRACTOR € lame |LOUe Bo SueTenctor Yeo | joy —$—$— ow. ifownce ae ress © A | 8 |) ow | a oo 0 ° o ejoj1 4 A eH o|t|t A 1}Oj}o 4 a to. io 7 ji Sto ° ° tlalal a Title ———_| torow (Bin) Tne fuk subtrackey t derigntd with tas hep of He following | Logic goku zt) two _2-inpal ANID gate wd) *wo 2 -impuk Exctwive -OR gate cy OR gare Ww) two NOT gp se tv) 2-imput OR gate. Full subtvactey qaunates two outputs a Diy eure tt 0b) ard a Rovrow ett (Bout). Boolian txprertonr_¢ from tk fuk table anc Ko map, thet boclan — enpromim con be derive a> ¢ biljewnce (B) = ABCA Awe + ABC + ABC wre C= Bin 2 Oe OC 2 AGBO© Bw Borrow (Boat) BC+ ABE + ABC + ABC Acce+B) + ABCC+T) 4 BOWAIAD = Acs Aa + BC wut C= Bin = ABn + AB + BBin = BC + (BOCA RESULT 3 Tae trad ¢ Half subtractcy aw Full Sutra ctor hone been studied and they truth tables wert verified. (CLASSTIME OUTPUT: HALF SUBTRACTOR Title Date 24110 J22. XPERIMENT =U ° Be-Maltiplorer Logisin. i pest and dmplemertation of Mullipiecet anc REQUIREMENTS 3 isin Soptwans Multiplex (MUX) 3 A Mux B® a dightal suttthh thal has multiple mputs (sunt) and a single outpye~ (destinatton ) —_ » +) | MUA Types THEORY 3 The select tus to we output. detent which, input comma j 2 40 4 Ca w 4 tt C2 select hint) seheck {ines wy 8 to 4 C3 select ben) ww 16 to 4d (4 setae Lined) dr @ quuralivd NxS MUR wane Nb 2 as ‘im! sthect Lins Typtca Application gf a MUX 2 Mustip sounco sebrctoy sh con 3 a = / dockig stabiorT be : to j heh ———1._2 5 Surround eae amd sound ar" 5 > “a ai sytem, en DB: Z _ oO SSouT Ce _ BAD a —— - os - _ oO 4 Laptop = CLASSTIME) 4 0 safer oe a TT eb Ww ———___— DE-MULTIPLEXER (1X 4) oe MULTIPLEXER (8X1) = DE-MULTIPLEXER (1X8) Title : Date 78 22 Page = x PERIMENT -5 THEORY _$ _ Wg LAME each of the 2 4n Binary Codec Decimal (BCD) encodt =a. decimak rumbus (0-1) b vepreserked by t's eqivatent bina} patlew (which ty _genenatiiy of 4 wits ) - - ) | whereas Sevor _segrnunk displog we an dectronfe device hich | consists of sever Ligni eositing Bfodes CLED'S) amanged bs 2 _ same. deyinite pattnn “nih i uid 10 display numbers 0 © 4. > BCD to swt segruk decoden haa four Prat nw (A, 6 C wt BD and 7 output kines (a,b, © ae, od g), thr output & geet 4O senor seqroank Les dispiny ent displays de dicimal ninbur depending wpor inputs - | swe seqenarS. display an urd 10 disploy ke digits ih cabcesakors docks, yaniow> ensan unig wins digttas wakhnn end digital counrtevs - | > | From mK Truth Table the Baoan eapreniona of gach outpal Junctions can be _unftlon a2 2 - = & CA BOP) = Sm (0,2,3,5,7, 3,9) _ as - wy | b= BAB, CD) = Sm C,4,2,3,4,7,8,9) 7 | a — — | c= CABO DB) = Em (04,34,5)6,1,8,9) a fr,_€92)3,5,6 2) Vem (0,26 8) em _ €O,4,5,6,8,4) Em (2,349,596, 8,9) = Fy CABO) DD e | = Fo ABCD) =F A,B,CD) “Gas | = 8..PD miu ea | —- o 0 | Bce to | | 5 | | 7 seqeapnt od — —i_ aa Decoden ay | e | c 9 | - - A Tsuen Ub Aisplan “ TaotH TABLE 3_ + Dectenak | dapat Mines — bight aA BCID O° oo O10 4 olo oft 2 oo1 0 3 oot 14 4 leo t 00 ~S a“ ° aS mn ° b ROO} eo a a Bp Pp | Title = Date. — Page 5 From tnt akeove __simpltiffeatfon , we gat the output vale a= A+C+ 60+ BO b= B+tb + co = @+ tid = BR4 cB + BD +Bcr+A RESULT 2 Te Hyak gf BCD 107 sqqrrant dacocun ho ben studied and as outpak noo beer vent fiek OUTPUT: BCD To 7 SEGMENT DECODER “-0+-8C+C-0+B-con “B-D+c-0 C-D+B-C+B-Den OC+8-Co0-Den uo Topic Date “sn 20 _ EXPERIMENT — 6 ; [Aird = Pug 4 bit apple Corian. in Lue! «Up Guntur a | * Mod = 12 Wuntor ~ REQUIREMENTS + Logtsim Sojtunnt * Down tountye nl my | THEORY S 4 Ripple Countn + s +) Negative iy Ttggeud. Fitp Flop % r Tauty Tree - ; ie Sy KW | Orn —3 4}-— eee) 2 oe om | pr fo ft le —— KK ay a | jt | oO | t I i p. i, i | ® a | 4- BIT RIPPLE u-ein Rioee UP - COUNTER DOWN - COUNTER TRUTH TABLE 8 oo a v - | TRUTH TABLES _ | [OK Toe | ae iat | | |g, & |& | o Date Mj\\|202% Page No.___ mule, vabut, L a v) | Bown Counttor : [typo nua nent pom tha _aiauen— Yale SS | ceo vote vi) | MoD Cowtan, 2 [op —cowstina aoa dfivacl bose on tt nsanthxt of stata — OQ t A iv * 0 ( 0000 4o 11 (rolt) would pagupe four {up - {tops . : MOD -\2 UP COUNTER TRUTH «TABLE - [eux | & GQ | % mrad | © | 0 |O lo oa) 7m” O) ay a Guy |to™ Cu) un") 22) OUTPUT: 4-BIT UP COUNTER © ©0600 4-BIT DOWN COUNTER Topic Date '2/12122 __- Page No. EXPERIMENT - 7 ek AIM 8 mpl wentation of Bo hie wipple Cound _ : —f CS nesta us) on Go ggestan SorTWARE USED 3 Logesim a | | Daisgyn “abut Synchnonoun up Courstirts - Centos olla} Tih ep {inp = » WRITO-LINE Teacher's Sign. { Topic Date Page No, 2) | Stat diagram ond Coroiuch Erietodion tobe jy 990) _ 5 18h, —}— | Cid Gio) 7 Z C Cou Y — a) G0) 4 fo q - Poenenk Stoke | Nek Stake QQ Wr ar & [Tu Ke [T Kr | Je Ke oo o|s o 4 \0 x_lo X |L x © ° Lilo 4 o jo x [h KX A ° o tf 4 io x |y oj, Xx ° tooo |r x |% Lox L L tO 4 ix do |o Xx [tL x L t bt © Jk ae X |x L 4 4 ob 4 IY ® Ix ot x i L o oO © + wk ms L Teacher's Sign. % tu y? wo COUNTER 38iT sy a Date Page No. _ i fu a follows, Jo zt Tr = Wo Moe Kr = &) Qo lied Tes Os Ki = Qo OUTPUT: BIT ASYNCHRONOUS COUNTER 3- BIT SYNCHRONOUS COUNTER 3 Topic Date ____ Page No. ) EXPERIMENT - 8 AIM § Witiiag and crceutiing programs tn _gaudirn 1025 SOFTWARE USED 2 GNU Sin 2085 THEORY 3 2 | GNusiny 2085 %& a softwant tral simuldten tt 2005) wnicroprocemoy . dt con _amenble dibyy anh vucrte 3025 anunbly code Tune ant 6 quenat purpose _yagister to store_ date von B.C, DEH Lark an Accumulator to store ft xooult, We can convert _pecimal_t6 Wee _anct_vice vero Wwe car alo menuatiy update port values _anck monory Some common commands MUL => Move dSormediates MOV => Skort doko at a pantiatan addr LoA =? Load Accumulator ADD md 40 re Youle ty Accumulator STA Copy Accumulator contents at adders HUT =7 Halt PROGRAMS = > | to Add two valine? yi myzr 8, ost 2 | MVE cf , Od 3) ADD _ 6 4) | Aeo C 3)] aT = a WRITO-LINE Ga Teacher's Sign, Topic _ Page No _) To Swotract two values MYL A, OSH MYT B&B, oan LBB WUT Vel and stort AADANO 4G anon addr — | Loa - ins e008 a Mov BLA a —— LOA 90014 a res a ——— sTA oood | HUT _ —sz | read vatuc ond store subtraction te anotrr _ adolyo _ LeA adda mov BA LBA __OOO1 a _ sve @ STA__00O2 a [rt 1) ADDING TWO VALUES OUTPUT MVI B, 05H oe MVI C, 03H mk 0002 2 ADD B a} oe ADD C 0605 5 bad HLT moe UBTRACTING TWO VALUES ieee MVI A, 05H ene MVI B, 03H was SUB B Pre ae neheg 0 | D VALUES AND STORE ADDITION TO ANOTHER ADDRESS 3) LOA soe LDA 0000 ee eee) MOV B,A too 0S a LDA 0001 eg mee ADD B om 3 6 eae sTA 0002 oot ‘ 0 an ae os 8 4) LOAD VALUES & STORE SUBTRACTION TO ANOTHER ADDRES! ae LDA 0000 cam MOV B,A Address (Hex) Address Data ces LDA 0001 aon eee: maw SUB B om 2 > ae STA 0002 “ — + vee HLT reas

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