Explain the concept of pipelining.

: In pipelined processor, fetch, decode and execute opera on are Define the following terms –
performed simultaneously or in parallel. When first instruc on is being decoded, same me code
(i) Physical Address : The address given by BIU is 20 bit called as physical address. It is the actual
of the next instruc on is fetched.• When first instruc on is ge ng executed, second one’s is
address of the memory loca on accessed by the microprocessor. It is calculated
decoded and third instruc on code is fetched from memory. This process is known as pipelining. It
improves speed of opera on to great extent. (ii) Effec ve Address: Effec ve address or the offset address is the offset for a memory operand. It
is an unassigned 16 bit number that gives the operand's distance in bytes from the beginning of
State importance of pipelining in 8086 microprocessor  In pipelining, while the current instruc on
the segment.
is execu ng, next instruc on is fetched using a queue.  Pipelining enables many instruc ons to be
executed at the same me.  It allows execu on to be done in fewer cycles.  Speed up the ALP ARAAY OF 10 BYTE IN ASCENDING step: MOV AL,[SI]
execu on speed of the processor.  More efficient use of processor. Program: CMP AL,[SI+1]
DATA SEGMENT JC Down
DAA : DAA instruc on is used to convert the sum of two packed BCD numbers in the register AL ARRAY DB 15h,05h,08h,78h,56h, 60h, 54h, XCHG AL,[SI+1]
into a correct BCD number. Example : MOV AL, 23H MOV BL, 47H ADD AL, BL DAA A er the 35h, 24h, 67h XCHG AL,[SI]
execu on of the above instruc ons, the result in AL = 70H. DATA ENDS Down : ADD SI,1
CODE SEGMENT LOOP step
MUL source: Unsigned mul plica on of the source byte with AL or source word with AX. The result ASSUME CS: CODE, DS:DATA DEC BL
is stored either in AX or in DX: AX. (For byte opera on the result is min 8 bits and maximum 16 bits START:MOV DX, DATA JNZ step1
whereas for word opera on the result is minimum 16 or maximum 32 bits).Ex: MUL CL: Mul ply MOV DS, DX MOV AH,4CH
contents of CL with AL and result stored in AX.MUL WORD PTR [BX]: mul ply word from BX offset MOV BL,0AH INT 21H
with AX and result stored in DX:AX. step1: MOV SI,OFFSET ARRAY CODE ENDS
MOV CL,09H END START
DIV source: Divide the contents of the source with AX or with DX: AX and result is stored either in
AX {AH= remainder and AL= quo ent} or in DX:AX { DX= remainder, and AX= quo ent}.Ex: DIV BL:
divide the contents of the BL with AX and result stored in AX. DIV WORD PTR [BX+SI]: divide the
word from offset of BX+SI with DX: AX and result stored in DX: AX. SMALLEST NUMBER FROM ARRAY OF 10 NUM MOV AL, [SI]
DATA SEGMENT CMP AL, BL
X-OR des na on, Source:- Contents of source are exclusively ORed with contents destn Result ARRAY DB JGE NXT
stored in destn 15H,05H,08H,78H,56H,60H,54H,35H,24H,67H MOV BL, AL
RES DB ? NXT:
EG- XOR [BX + DI], 1234H
DATA ENDS INC SI
XOR [BX + 2000H], AX CODE SEGMENT DEC CX
ASSUME CS:CODE, DS:DATA JNZ UP
XOR [1234H], BX START: MOV AX, DATA MOV RES,BL
MOV DS, AX INT 3
Features of 8086 microprpcessor 1)It requires +5v power supply. 2)It has 20 bit address bus,can
MOV CX, 04H CODE ENDS
acceess 220 =1MB memory loca on. 3)16 bit data bus. 4)It is a 16 bit processor having 16 bit MOV BL, 79H END START
ALU,16 bit registers. LEA SI, ARRAY
PARAMETERS COMBINATIONAL SEQUENTIAL UP:
DEFINITION The output of any instance of The output of any instance of
me depends upon the input me depends upon the Q Memory segment :Segmenta on is the process in which the main memory of the computer is
present at that instance of present input as well as past logically divided into different segments and each segment has its own base address. It is basically
me input and output used to enhance the speed of execu on of the computer system, so that the processor is able to
NEED OF MEMORY no memory element required Memory element required to fetch and execute the data from the memory easily and fast. Need for Segmenta on –The Bus
in the ckt store bit Interface Unit (BIU) contains four 16 bit special purpose registers (men oned below) called as
NEED OF CLOCKS clock input not necessary clock input necessary Segment Registers. (1)Code segment register (CS): is used for addressing memory loca on in the
EXAMPLE example adders,subtractor example flip flop ,shi code segment of the memory, where the executable program is stored.(2) Data segment register
code, converter, comparator register, counters etc (DS): points to the data segment of the memory where the data is stored. (3)Extra Segment
APPLICATION etc used to simplify Boolean used in counters and registers Register (ES): also refers to a segment in the memory which is another data segment in the
expression kmap truthmap memory. (4)Stack Segment Register (SS): is used for addressing stack segment of the memory. The
stack segment is that segment of memory which is used to store stack data

Q Draw architectural block diagram of 8086 microprocessor anddescribe the func on of each
block.

Internal architecture of Intel 8086:Intel 8086 is a 16 bit integer processor. It has 16-bit data bus and
20-bit address bus. The internal architecture of Intel 8086 is divided intotwo units,1. Bus Interface
Unit (BIU)2. Execu on Unit (EU).Bus Interface Unit (BIU )

Memory Interface:The Bus Interface Unit (BIU) generates the 20-bit physical memory address and
provides the interface with external memory(ROM/RAM). 8086 has a single memory interface.

Instruc on Byte queue: To speed up the execu on, 6-bytes of instruc on are fetched in advance
and kept in a 6- byte Instruc on Queue while other instruc ons are being executed in the
Execu on Unit (EU).

Segment registers: There are four 16-bit segment registers, viz., the code segment (CS),the stack
segment (SS), the extra segment (ES), and the data segment(DS). The processor uses CS segment
for all accesses to instruc onsr eferenced by instruc on pointer (IP) register.

Adder:8086's BIU produces the 20-bit physical memory address by combining a 16-bit segment
address with a 16-bit offset address using the adder circuit.

2. Execu on Unit:

Control unit: The instruc ons fetched by BIU in the instruc on byte queue are decoded under the
control of ming and control signals. Arithme c and Logic Unit (ALU) : Execu on unit has a 16 bit
ALU, which performs arithme c & logic opera ons. General purpose register unit: All general
registers of the 8086 microprocessor can be used for arithme c and logic opera ons. The general
registers are: Accumulator register AL (8 bit), AX (AL & AHfor 16 bit), Base register, Count register,
Data register , Stack Pointer(SP), Base Pointer (BP), Source Index (SI), Des na on Index (DI).

Flags: is a 16-bit register containing 9 1-bit flags: Overflow Flag (OF), Direc on Flag (DF), Interrupt-
enable Flag (IF), Single-step Flag (TF), Sign Flag (SF), Zero Flag (ZF), Auxiliary carry Flag (AF),Parity
Flag (PF), Carry Flag (CF)

Q Use of Flag Register: Microprocessor 8086 has 16 bit flag register among which 9 bits are ac ve.
The purpose of flag register is to indicate the status of the processor Depending upon the value of
result a er any arithme c and logical opera on the flag bits become set (1) or reset (0). 1. Carry
Flag (CF): Set 1 if there is carry out of MSB posi on. 2. Auxiliary Flag (AF): Set 1 if carry from lower
nibble to upper nibble. 3. Parity Flag (PF): Set 1 if opera on contains even number. 4. Zero Flag
(ZF): Set 1 if result of arithme c or logical opera on is zero. 5. Sign Flag (SF): Set 1 if result of
opera on is nega ve. 6. Overflow Flag (OF): Set 1 if result is too large to fit in the numbers bits
available to accommodate it. 7. Control Flags: (i) Trap Flag (TF): Set 1 if program can be run in single
step. (ii) Interrupt Flag (IF): Set 1 if INTR of 8086 is enabled. (iii) Direc on Flag (DF): Set 1 if string
bytes are write or read from higher memory address to lower memory address.  Use of Segment
Register: The 8086 has four segment register of 16 bit each. i.e. CS,DS,SS and ES. The code segment
CS register used to address a memory loca on in the code segment of memory. The data segment
point to data segment of memory where the data is stored the extra segment ES used to address
the segment is addi onal data segment. The Stack segment SS register is used to point loca on in
stack segment of the memory, used to store data temporarily on the stack.