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PDF 3 - Floorplan Lab Manual

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0% found this document useful (0 votes)
154 views8 pages

PDF 3 - Floorplan Lab Manual

Uploaded by

ketchrajath24
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chipizage Physical Design Course FLOORPLAN Learning Objectives : 1. Perform Sanity Checks 2. Create Floorplan 3. Place 10 Ports 4. Manually Place the Macros Tasks : 1. Invoke the tool 2. Open the library and block created in the previous class 3. Perform sanity checks 4. Create a floorplan, given a. Core Utilization b. Aspect Ratio c. Shape (Rectangular / Rectilinear) d. Space between core and die area 4. Placing the I/O ports 5. Placing Macros into the core area 6. Set Keepout margin and fix the macros Invoke the Tool : Open the directory which was created in the previous lab Linux > cd dtmf_project/design_import Invoke the tool Linux > icc2_s Open the Library ice2_shell > open lib lib/dtmf_1ib To see all the blocks present in the library shell > list_blocks Now, open the import_done block to which netlist and SDC files were read in the previous lab shell > open block import Chipedge Technologies Pvt Ltd., Bangalore Physical Design Course Sanity Checks : Check the design for netlist connectivity errors if mismatches are present between the current design and reference libraries Create Floorplan : To open the Graphical User Interface (GUD) Block Window (layout window) will open as shown in Fig 1 Fig The large rectangular shapes as shown in Fig 1 are the macros, this design has 6 such macros. In the toolbar, Click on Task > Design planning, a window will pop out. Select Floorplan Initialization as shown in Fig 2. Chipedge Technologies Pvt Ltd., Bangalore ChiplEdge Physical Design Course Fig 3: Floorplan initialization In Floorplan initialization window, Select : Core Area Shape : Template ‘Type : Rectangle Side Size Control : Ratio Core Utilization = 0.6 Aspect Ratio = 1 Sides a=1 b=0.65 Select : Die Boundary follows core shape Uniform : 5 Click on Apply Fig 4 : After floorplan initialization Chipedge Technologies Pvt Ltd., Bangalore ChipiEdge Physical Design Course Activity 1: 1. What is Core Utilization ? 2. What is Aspect ratio? 3. Try Different values for Core Utilization (0.6,0.7,0.8) with fixed Aspect Ratio (0.85). Note : What is the height , width, and AREA of core. 4. Try different values for aspect ratio (0.7,0.8,0.85) with core utilization (0.6) fixed Note : What is the height , width and AREA of core. Activity 2: Explore the options present in View settings on the right hand side. - Site rows - Tracks - Layers Placement of I/O ports Note : place_io_ports.tel is available in /PD/labs/iec2/design_import/scripts/ Set the constraints for pin placement 2_shell> set_block_pin_constraints -self - M3 Ma} Perform pin placement ice2_shell> place_pins -self Check whether the ports are fixed or not ice2_shell> get_attribute [get_ports *] is_fix Set all the ports to the fixed state if they are not ice2_shell> set_attribute [get_ports *] physical_status fixed Chipedge Technologies Pvt Ltd., Bangalore Chiplzdga Physical Design Course Input/Output Ports Placement Look into all input / output ports of this project 2_she jet_port Compare with the ports present in the top module of the netlist. Get the count of ports Placement of Macros : Move the macros (select macro and press m to move) into core area, based on interconnections b/w the macros to macros and I/O ports (by enabling fiylines), signal pins of macros facing towards the core. Use align and distribute options of the tool while placing macros. Refer to Fig 6 to enable flylines (Net Connections) te x8 mvaiu@P) eBags Chipedge Technologies Pvt Ltd., Bangalore Chiplzdga Physical Design Course i i Fig 6: To check Flylines Refer Fig 7 to enable Align / Distribute tool T# timo he ces real iv Poe canes a Distribute Tool Fig 7 : Align Place all Macros in the core area (as shown in Fig 8) Chipedge Technologies Pvt Ltd., Bangalore Physical Design Course Fig 8 : After placement of Macros Activity 4: List the Guidelines followed for placement of macros. 1 Set Keepout Margin : We need to set the keepout margin across the macros so that standard cells are not placed close to the edge of Macros. Following command creates keepout margins for all macros with type hard. Activity 5 What is keep out margin ? Differentiate between Hard and Soft margins. To fix the Macros: Chipedge Technologies Pvt Ltd., Bangalore ChipiEdge Physical Design Course Check whether Macros are fixed or not. 2_shell> get_attribute [get_cells -physi. design_type=-macro] is_fixed 1_context - Lets fix the macros if they are unfixed. ice2_shell> set_attribute [get_cells -physical_context -filter design_type==macro] physical_status fixed Activity 6: Run the following command to unfix the fixed macros ice2_shell> set_fixed_objects [get_cells -physical_context -filter design_type: Run the following command to check whether macros are placed or not. icc?_shell> get_attribute [get_cells -physical_context -filter design_type==macro] physical_status Saving the Block : 2_shell> set_app options -list (design.morph_on_save_as true} Save the changes done to the block as floorplan_done ice2_shell> save_block -as floorplan_done Close the block and Library before exiting from the iec2_shell. ice2_shell> close_blocks ice2_shell> close_lib Chipedge Technologies Pvt Ltd., Bangalore

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