Unit 5-Memory Organization
Unit 5-Memory Organization
Memory Organization
Introduction
Memory is used for storing programs and data that are required to
perform a specific task.
For CPU to operate at its maximum speed, it required an uninterrupted
and high speed access to these memories that contain programs and data.
Some of the criteria need to be taken into consideration while deciding
which memory is to be used:
• Cost
• Speed
• Memory access time
• Data transfer rate
• Reliability
Block Diagram
A computer system contains various types of memories like auxiliary memory,
cache memory, and main memory.
• Auxiliary Memory
The auxiliary memory is at the bottom and is not connected with the CPU directly.
However, being slow, it is present in large volume in the system due to its low
pricing. This memory is basically used for storing the programs that are not needed
in the main memory. This helps in freeing the main memory which can be utilized
by other programs that needs main memory. The main function of this memory is
to provide parallel searching that can be used for performing a search on an entire
word.
• Main Memory
The main memory is at the second level of the hierarchy. Due to its direct
connection with the CPU, it is also known as central memory. The main memory
holds the data and the programs that are needed by the CPU. The main memory
mainly consists of RAM, which is available in static and dynamic mode.
• Cache Memory
Cache memory is at the top level of the memory hierarchy. This is a high speed
memory used to increase the speed of processing by making current programs
and data available to the CPU at a rapid rate. Cache memory is usually placed
between the CPU and the main memory.
Main Memory
Types of RAM:-
• If the active portions of the program and data are placed in a fast small
memory, the average memory access time can be reduced
• Thus reducing the total execution time of the program
• Such a fast small memory is referred to as cache memory
• The cache is the fastest component in the memory hierarchy and
approaches the speed of CPU component
Locality of Reference
• When CPU needs to access memory, the cache is examined
• If the word is found in the cache, it is read from the fast memory
• If the word addressed by the CPU is not found in the cache, the main
memory is accessed to read the word
• When the CPU refers to memory and finds the word in cache, it is said to produce a
hit
• Otherwise, it is a miss
• Therefore, very little or no time must be wasted when searching the words
in the cache
Spatial Locality – Spatial locality means instruction or data near to the
current memory location that is being fetched, may be needed soon in the
near future. This is slightly different from the temporal locality. Here we
are talking about nearly located memory locations while in temporal
locality we were talking about the actual memory location that was being
fetched.
• This permits any location in cache to store any word from main memory
• The address value of 15 bits is shown as a five- digit octal number and its
corresponding 12- bit word is shown as a four-digit octal number
• A CPU address of 15 bits is places in the argument register and the
associative memory as searched for a matching address
• If the address is found, the corresponding 12- bits data is read and sent
to the CPU
• If not, the main memory is accessed for the word
• If the cache is full, an address-data pair must be displaced to make
room for a pair that is needed and not presently in the cache
Direct Mapping
• In general case, there are 2^k words in cache memory and 2^n words in
main memory (in our case, k=9, n=15)
• The n bit memory address is divided into two fields: k-bits for the index
and n-k bits for the tag field
Addressing relationships between main and cache memories
Set-Associative Mapping
• The disadvantage of direct mapping is that two words with the same
index in their address but with different tag values cannot reside in
cache memory at the same time
• A RAM chip is better suited for communication with the CPU if it has one
or more control inputs that select the chip when needed
• The Block diagram of a RAM chip is shown next slide, the capacity of
the memory is 128 words of 8 bits (one byte) per word
RAM
ROM
Memory Address Map
• Memory Address Map is a pictorial representation of assigned address
space for each chip in the system
• The RAM have 128 byte and need seven address lines, so for above
requirement we would need 4 RAM each of 128bytes (128*4= 512)
whereas the ROM have 512 bytes and need 9 address lines hence
only one ROM
• The hexadecimal address assigns a range of hexadecimal equivalent
address for each chip
• When line 10 is 0, CPU selects a RAM. And when it’s 1, it selects the
ROM
Memory connection to the CPU
• To help understand the mapping procedure, we have the following
example: