MAINTENANCE

HANDB

~~ 4 08 ~~
ultifunction alibrator
 MAINTENANCE HAN OOK
for

THE DATR N
MULTIFUNCTION CALIBRATOR

i'il

erv1c1ng
[l

art 1 alibration and

lnfor ation
and

art 2 Technical escriptions

For any assistance contact your neares! Dalron Sales and Service center.
Addresses can be found at the back of this handbook.

850271 Issue 1 (MAR 1992)

Due to our policy of continuously updating our products, this handbook may contain minor differences in specification, components and circuit design
to the instrument actually supplied. Amendment sheets precisely matched to your serial number are available on request.

Tllis produci woih "!he risquirisments ol lh@ lollowing Europearn Communiljl Direclives:
Ml::llS@;/!1111,,C {!.:ll!l@tf@ri111!!19!1ffli@ Comp!lll!lill!iity) and 73/23/EEC «L@t~ \l'oltage)
as amem:led by 93/~/!:l!:C {CE Marking).
However, noisy or intense "'"""'""'"'''""'"''i"
lields in !he vicinily ol lhe eq1,1ipmeni can distl.lrl:J lhe measuremeni
circuit Users should exercise and use appropriate connection and cabling conliguralions 10 avoid
misleading results when making precisiori meas11remenls in lhe presence al eleclromagneiic inlenerence.
I ~ DANGER
HIGH VOLTAGE
r

THIS INSTRUMENT IS CAPABLE

OF DELIVERING
A LETHAL ELECTRIC SHOCK !

I+, I- Hi and Lo terminals

Carry the Full Output Voltage
THIS CAN KILL!

Guard terminal is sensitive to

over-voltage
It can damage your
instrument !
J r,------------------."'

1
Unless you are sure that it is sare to do so,
DO NOT TOUCH
the I+ I- Hi or Lo leads and terminals

DANGER
 CONTENTS

Se111icing Diagrnims amll Componenl Usls .................................................................................................................. Refer to Volume 2

osi,eri1,;tiG1ro lm,i:alla!km , Conlmls, C©nneciions and Operation,

s,,,,,,,,i,,,,,1·,cin :::;ri,3c111ca·11011 Verifk::alion amd Routine Calibralkm .......................................................... Releno Usefs Handbook

PART1 AND SERVICING INFORMATION

Section Page

1 CALIBRATION
1.1 ...... Guida lo Calibratiorn ...... .... .... ....... .... ....... .... ........ ... ................... ........ ... ........ .... ... .... .......................... ........ ............... ... 1-1
1.2 ...... Remote Calibration Guidelines ................................................................................................................................... 1-7
1.3 ...... Pre-Calibraticm:
1.3. i ... lntrodwciion ...... .... ........... ............... .... ................... ....... ........... ........ ....... ........ ................... ....... .... .................. 1-9
1.3.2 ... Pmcedwre ...................................................................................................................................................... 1-10
1.4 ...... lnlemalOhms .......................................................................................................................................... 1-13
1.5 ...... Remote Gwidlines .............................................................................................................................. u-14

1 ......... Noles on the U!le of the Null Delec!or ........................................................................................................................ 1-A 1

2 ......... Calibraiion Source Zem Olfse!s .. .... .... ............... .... ... .... .... ....... .... ........ ... ........ ....... .... .... ........... .... .... ... ........ .... ... ....... 1-A2

2.1 ...... lrn!irodl.ldion ..................................................................................................................................'............................... 2-1

2.2 ...... "'""me."''"" Guides....................................................................................................................................................... 2-2
2.2.1 ... FAIL 1 (l:::):ce1,1m1e intemal Tempera!me) ..................................................................................................... 2-2
2.2.2 ... FAIL2 '"""-'"''""'11 ................................................................................................................................... 2-2
2.2.3 ... FAIL 3 Data Corrnpted) ................................................................................................................... 2-3
2.2.4 ... FAIL 4 IP,,::ici!~ion Divider Fault) .................................................................................................................... 2-3
2.2.5 ... FAIL 5 Circui!s 'Watchdog' Tripped)................................................................................................. 2-4
2.2.6 ... FAIL 6 1r:,,1,n,·1>1ot,n MemorJ,1 Faull)................................................................................................................ 2-5
2.2. 7 ... FAIL 7 A. 400V Power Failure) ....................................................... :........................................................ 2-5
2.2.8 ... FAIL 8 A 38V Power Failure).................................................................................................................. 2-6
2.2.9 ... FAIL 9 A. 15V Power Failure) .................................................................................................................. 2-6
2.2.10 . Error FrequeRCy selected !:ll.ll nol detecled) ............................................................................. 2-7
2.2. u1 . Error OL Limils el'iceeded) .. .... ............... ........ ........... ....... .... ........ ....... .... .... ... .... .... .... ....... .... ....... .... 2-8
2.3 ...... Sell-Test Sequence ........................ .'........................................................................................................................... 2-9
2.4 ...... Fuse Protection........................................................................................................................................................... 2. ui

AND RIEASSEMBl Y

3.1 ...... General Precau!kms ............................................ :...................................................................................................... 3-1

3.2 ...... General Mechanical Layout .. .... .... .... ... .... ........... .... .... .... ... ............ ... ........ .... ....... .... .... ....... ........... .... .... .... ....... .... .... .. 3-1
3.3 ...... Location and Access .. .... .... .... ... .. .. .... .... ... .. ...... .... ... .... .... ............... .... ... .... .... .... ... .... .... .... ... .... .... .... ....... .... ....... .... .... . 3-2
3.4 ...... General Access .. .... .. .. .... ... .... .... .... ... .... .... ....... .... .... .... ........... ....... ............ ..... .. .... .... ... ........ ....... .... ........ ... ........ .... ..... 3-3
3.5. ..... Removal and Filling .................... .'............................................................................................................................... 3-5

SEIRVICiNG AND INTERNAL ADJUSTMENTS

4. u ...... Introduction .. .... .... .... ... .... .... .... ... .... .... .... ... .... .... ........... .... .... ... .... .... .... ........... ....... ........ ....... .... ........ ... ........ ................ 4-1
4.2 ...... Cleaning !he Air Intake Filler ...................................................................................................................................... 4-3
4.3 ...... l.ilhium Bal!ery - Replacement .. .... .... ........... .... ........... .... .... ... .... .... ..... ... ........ ............... ........... ........... ........ .... ............ 4-4
4.4 ...... Ohms Fum:lion - St!:!ndard Resistor Adjus!ment .................................................... .'................................................... 4-6
4.5 ...... Biss Curren! Adju!l!ment- 100V PA ........................................................................................................................... 4-6
4.6 ...... 1,,,11111111o;;1H1v1::1 load Tesl .................................................................................................................................................. 4-7
4. 7 ...... yu,,~is,.~n Currant Adjustmenl - Cum,ni/Ohms Assembly ...........................................................................:............. 4-S
4.S ...... L.01nrn11,;nm:;a - Currenl/Ohms Assembly ........ ,.......................................................................................... 4-9
4.9 ...... Common Adjuslmenls ............................................................................................................................... 4-10
4.10 .... SenseAmplifierZeros ................................................................................................................................................ 4-1,

0-2
PART2 TECHNICAL DESCRIPTIONS
Section Title

5 PRINCIPLES OF OPERATION

5.1 ...... Block Diagrams........................................................................................................................................................... 5-1

5.2 ...... Inputs .......................................................................................................................................................................... 5-1
5.3 ...... Digital Outputs ............................................................................................................................................................ 5-1
5.4 ...... Precision Reference ...... .... .... .. . .... ..... ... ... .... ........ ... .... .... .... ....... .... .... ... ... . .... .... ... .... .... .... ... .... .... .... ... .... .... .... ... ..... ... .. 5-2
5.5 ...... Analog Control ............................................................................................................................................................ 5-3
5.6 ...... DC Voltage Outputs.................................................................................................................................................... 5-3
5. 7 ...... AC Voltage Outputs .. .... .... .... ... .... .... .... ... ........ .... ... .... .... .... ... .... .... .... ... .... .... .... ... .... .... .... ... .... .... .... ... .... .... .... ... .... .... ... 5-3
5.8 ...... 1000V Ranges ............................................................................................................................................................ 5-5
5.9 ...... DC/AC Current Outputs.............................................................................................................................................. 5-5
5.10 .... Resistance Outputs ............................. ....................................................................................................................... 5-6
5.10 .... Datron'Autocal' .......................................................................................................................................................... 5-6

DIGITAL CIRCUITS; REFERENCE CIRCUITS; POWER SUPPLIES

6.1 ...... Digital .. .... .... .... ... ........ .... ... .... .... .. .. ... .... ... . .... ... .... .... .... ... .... .... .... ... .... .... .... ... ........ .... ... ........ .... ..... .. ........ .. ..... ........ ... ... 6-1
6.2 ...... Keyboard .................................................................................................................................................................... 6-11
6.3 ...... Digital Displays ................. ........ ............................................................................................................. ..................... 6-15
6.4 ...... Analog Control Interface . .. ... .... .... ....... .... .... ... .... .... .... ... .... .... .... ....... ........ ... .... .... ........... ........ ... .... .... ..... .. ........ .... ... .... 6-22
6.5 ...... Precision Divider......................................................................................................................................................... 6-30
6.6 ...... AC Reference - !he Qua.si-Sinewave .......................................................................................................................... 6-43
6. 7 ...... Power Supplies .. .... .... .... ... .... .... .... ... .... ........ ... . ........... ... ........ .... ... ........ .... ... ........ .... ... ........ .... ... .. .. ........ ... .... ........ ...... 6-4 7

1 VOLTAGE SVSTIEM
7.1 ...... Introduction................................................................................................................................................................. 7-1
7.2 ...... Low Voltage Loops ..................................................................................................................................................... 7-2
7.3 ...... DC 1V Loop ................................................................................................................................................................ 7-3
7.4 ...... 1OOmV Range............................................................................................................................................................. 7-6
7.5 ...... 100µV- 10mV Ranges ............................................................................................................................................... 7-7
7.6 ...... DC 10V Loop .............................................................................................................................................................. 7-7
7.7 ...... DC High Voltage Loops .............................................................................................................................................. 7-9
7.8 ...... 100V Range ................................................................................................................................................................ 7-10
7.9 ...... 1000V Range .............................................................................................................................................................. 7-15
7.10 .... Logic Control of DC Ou,puts ....................................................................................................................................... 7-20
7.11 .... DC Assembly Relay Drives and Logic........................................................................................................................ 7-21
7.12 .... PAAssemblyLogicandRelayDrives ........................................................................................................................ 7-23

AC VOLTAGE OUTPUTS~ FREQUENCY CONTROL SYSTEM

8. 1 ...... Digital Frequency Synthesizer .. .... .... .... ....... .... ....... .... .... .... ... ........ .... ... ........ .... ... .... .... .... ... ............ ... ........ .... ... .... .... .. 8-1
8. 2 ...... Quadrature Sinewave Oscillator ............................................................................. .,.. .... .... ... .... .... .... ... .... .... .... ....... ... 8-9
8.3 ...... External Frequency Lock ............................................................................................................................................ 8-17

9 AC VOLTAGE OUTPUTS· AMPLITUDE CONTROL SYSTEM

9. 1 ...... Introduction .. .... .... .... ... .... ........ ... .... .... ....... .... .... .... ... ........ ...................... .... ........... .... .... .... ....... .... ....... .... .... .... ... ......... 9-1
9.2 ...... AC Voltage Amplitude Control System - Block Diagram ............................................................................................ 9-2
9.3 ...... Voltage Controlled Amplifiers ................................................................; .................................................................... 9-3
9.4 ...... AC Low Voltage Loop ................................................................................................................................................. 9-7
9.5 ...... AC High Voltage Loops .............................................................................................................................................. 9-12
9.6 ...... AC 100V Range ........................................................,..................................................... : ........................................... 9-13
9.7 ...... AC 1000V Range ........................................................................................................................................................ 9-14
9.8 ...... AC High Voltage Sensing ........................................................................................................................................... 9-18
9.9 ...... Sine/Quasi-Sine RMS Comparator ............................................................................................................................. 9-19
9.10 ... ,l.ogic Control ol AC Outputs....................................................................................................................................... 9-30

0-3
10 CURRENT OUTPUTS AND RESISTANCE

10.1 .... DC and AC Current..................................................................................................................................................... 10-1

10.2 .... Resistance ...... .... .... ... .... .... .. .. ... .... .... .... ....... .... .... ... .... .... .... ....... .... .. .. ....... .... .. .. ... .... .... ....... .... .... .... ... .... .... ... . ... .... ...... 10-5
10.3 .... Function Switching ........................................................................................................ .......................... ................... 10-6
10.4 .... Current and/or Ohms Assembly Analog Conlml .. .... .. .. .... ... .... .... .... ... .... .... .... ....... ........ ... .... .... .... ... .... .... .... ... ........ .... 10-7

0-4
 ILLUSTRATIONS

PART1 CALIBRATION AND SERVICING INFORMATiON

1 CALIBRATION
Preparing/Retumlng t@ Us®:
IEEE 488 and Security Key switch Settings........................................................................................................................... 1-3

Autocal Facillties:
Autocal Keys .. .... .... .... ... .... ..... ...... .... ........ ... .... ........ ... .... .... .... ... .... .... .... ... .... .... .. .. ... ........ .... .. . ... . .... .... ... ..... ... ... . ... .... .... .... ... .. 1-5

Remote Calibration Guidelines:

Transfer of Calibration Facilities ........................................................................................................................................... 1-7

Pre-Calibration:
Identification of Access Holes .. .... .... .... ... .... .... .... ... .... .... .... ... .... .... .... ....... .... ....... .... .... .... ... .... .... ....... ........ .... ... ........ .... ....... .. 1-9
Procedure:
DCV Pre-cal Connections............................................................................................................................................... 1-10
ACV LF Pre-cal Connections.......................................................................................................................................... 1-11
ACV HF Pre-cal Connections......................................................................................................................................... 1-12
Pre-Cal Disable.............................................................................................................................................................. 1-12

Remote Pre-Calibration Guidline:s:

Transfer of DC Pre-Calibration Facilities ........................................................................................................... ................... 1-14
Transfer of AC Pre-Calibration Facilities............................................................................................................................... 1-14

Self Tesfi Sequene®:

Stage 1 ............................................................................................................................................................................ ....... 2-9
Stage 2.................................................................................................................................................................................. 2-10

3 DISMANTLING AND REASSEMBl Y

HF Trnnsformer AHembill':
HF Transformer..................................................................................................................................................................... 3-10
lf Transformer Assembly,:
LF Transformer..................................................................................................................................................................... 3-11

4 SERVICING AND INTERNAL ADJUSTMENTS

Battery Replacement .. .... .... .... ... .... .... .... ... .... ........ ... ............ ... .... .... .... ... .... .... ... ........ .... .... ....... .... .... ... .. .. .... .... ... .... .... ... . ... .... 4-5

0-5
PART2 TECHNICAL DESCRIPTIONS

5 5.1 ........... 4808 Simplified Block Diagram ...................................................................................................................... 5-0

5.2 ........... 4808 Block Diagram - Digital, Control and Flelerences ................................................................................. 5-7
5.3 ........... 4808 Block Diagram - DC Operation .. .. .. .... .... ... .... .... .... ... . ... .... .... ... .... .... .... ... .... .... ..... .. ........ .... ... .... ...... .. ... .. 5-9
5.4 ........... 4808 Block Diagram - AC Operation .............. ... .. .......... ... . ... .... .... ... . ... .... . ... ... .... .... .... .. .... ..... .... ... ...... .. .... ... ... 5-11
6. 1 ........... Digital Function Block Diagram ...... .... .... .. ..... ........ ... .... .... .... ... .... .... .... .... ... .. .. .... ... .... . .. ..... ............ ...... .... .... ... 6-2
6.2 ........... Software Overview ......................................................................................................................................... 6-4
6.3 ........... Master Clock Waveforms .. .... .... .. .. ... .... ........ ... .... .... .... ... .... .... .... ... .. .. .... .... ... .... ... ..... ... .... .... .... ... .... .... .... ... ..... 6-8
6.4 ........... Clock Shaping Circuit..................................................................................................................................... 6-9
6.5 ........... Clock Shaping Waveforms............................................................................................................................. 6-9
6.6 ........... U201 Interface (P8279) - Simplified Schematic............................................................................................. 6-11
6. 7 ........... Buzzer Control Latch Action .. .... .... .... ... .... .... ....... .... ... ..... ... ... ..... .... ... .... .. .. .... ... .... .... .... ... . ... .... .... ... .... .... .... ... 6-13
6.8 ........... Mode and Output Displays - Functional Block Diagram .. ... ..... .... ....... .... .... .... ........... ....... ........... .. .. .... .... .. .... 6-14
6.9 ........... RAM Access - Write Mode Logic ................................................................................................................... 6-16
6.10 ......... Read Mode Logic - RAM Access and Segment Switching .......... .............................. .......................... .......... 6-17
6.11 ......... Display Sc.an Sequences .. .... .... .... ... .... ........... .... .... .... ....... .... .... ... .... ........... .... .... .... ... ........ ....... .... ... ........ .... . 6-17
6.12 ......... Display Timing Waveforms .. .... .... .... ... .... .... ... . ... . ... .... ....... .... .... .... ... .... .... .... ... ..... ... .... ... .... .... ....... .... .... .... .. ... 6-19
6.13 ......... Comma Logic - Timing Waveforms................................................................................................................ 6-20
6.14 ......... Serial Data Link - Simplified Functional Block Diagram .. .... .. ...... ....... ........ ... ........ ....... ........ .... ... ......... ...... .... 6-22
6.15 ......... Serial Data Transfer Organization ............................................................................................ ........ ............. 6-23
6.16 ......... SSDA Clock Generator Waveforms............................................................................................................... 6-25
6.17 ......... WATCHDOG Circuitry - Simplified Block Diagram ........................................ .... ............................................ 6-29
6.18 ......... Precision Divider Ou I-Guard Circuitry - Simplified Block Diagram................................................................. 6-30
6.19 ......... Precision Divider In-Guard Circuitry - Simplified Block Diagram ............................................ ....................... 6-30
6.20 ......... 13-Bit Counter Waveforms............................................................................................................................. 6-32
6.21 ......... BUSY Waveforms.......................................................................................................................................... 6-33
6.22 ......... MSB Sync Logic Wavelorms ............................................ ............... .......................... ............... ..................... 6-34
6.23 ......... MSB Set!Reset Pulse Generation.................................................................................................................. 6-35
6.24 ......... LSB Set/Reset Pulse Generation ................................................................................. ................................. 6-36
6.26 ......... Action of LSD Switch ...... .... .... ... .... ........ ... .... .. .. ... . ... .... .... .. .. ... .... .... .... ... .... .... .... ... ........ ... .... .... .... .... .. . .. .. .... ... 6-38
6.27 ......... Action of Main and Guard Switches (MSD) ................................................................................................... 6-40
6.28 ......... Quasi-Sinewave Generation .. ... . .... .... ... ........ .... ... .... ........ ... .... .. .. .... .... ... .... .... ... .. .. .... .... ... .... .... .. .. ... .... .... .... ... 6-45
6.29 ......... Power Distribution Simplified Block Diagram ...... ................................................. ............... ........................... 6-47
71 7.1 ........... Low Voltage DC Operation - Simplified Functional Diagram ......................................................................... 7-2
7.2 ........... DC High Voltage Loop - Simplified Block Diagram and Routing.................................................................... 7-9
7.3 ........... Action of Constant-Curren! Source .. .... .... .... ... .... .... .... ... .... .... .... ... .... .... .... ... .... ... ..... ... ... ..... .... ... .... ... ..... ... .... . 7-18
7.4 ........... UPD(iG) Signal Distribution........................................................................................................................ 7-21
7.5 ........... Typical Clamped Buffer.................................................................................................................................. 7-22
7.6 ........... Limit Status Signal Origins........................................................................ .................................................... 7-25
8. 1 ........... Frequency Synthesizer Block Diagram .......... ....... .... ... ..... . .. .... .. ......... .... .... .... .. ..... ..... .. .... .... .... .. .. .......... ....... 8-1
8.2 ........... VCO Block Diagram ....................................................................................................................................... 8-2
8.3 ........... Frequency Dividers Block Diagram .. .... ........ ... .... .... ....... .... .... .... .. ......... .... ........... .... .... ....... .... . .. .... ... .. ...... ..... 8-4
8.4 ........... The Quadrature Sinewave Oscillator and its System Environment .............. .................. ............................... 8-9
8.5 ........... Basic Quadrature Sinewave Oscillator .......................................................................................................... 8-10
8.6 ........... Gain and Phase Response ol Practical Circuit.............................................................................................. 8-1 o
8. 7 ........... Corrected Quadrature Oscillator .. .... ........ ....... .... ....... ........ ....... .... .... ........... ........ ......... .. .. .. ....... .... . .. .... ......... 8-11
8.8 ........... Fine Frequency Control .. .... .... .... ... ........ .... ... .... ........... .... .... .... ... .... .... .... ... .. .. .... .... .. ... .. .... .. .. ... .... .... .... ... .... ... 8-12
8.9 ........... Summing A2 sin 2wl with A2cos2wt ................................................................................................................... 8-14
8-1 O ......... External Frequency Lock - Block Diagram .. .... ........... .... .... .... ... ...... .. .... ... .... . ... .... ... .... ........ ... .... .. .. ................ 8-17
8-11 ......... 1MHz/10MHz Detector Waveforms .. ..... .......... .... .... .... ...... ..... ........... .... .... ... .... .... ........... .... ....... .. .. .... . .. . ... .... 8-18
9.1 ........... Output Amplitude Control System.................................................................................................................. 9-1
9.2 ........... VCA - Block Diagram ..................................................................................................................................... 9-3
9.3 ........... 1VBuffer-OutputStage ................................................................................................................................ 9-4
9.4 ........... Simplified Diagram of Tracking Analog-to-Digital Converter.......................................................................... 9-5
9.5 ........... A-D Tracking - R/2R Network ........................................................................................................................ 9-5
9.6 ........... Window Comparator Action ......................................................................................... ............... ................... 9-6
9.7 ........... Low Voltage Loop - Simplified Block Diagram and Routing ........................................................................... 9-7
9.8 ........... Millivolt Attenuators .. .... ........ ... .... .... .... ... ........ ....... .... .... .... ... .... .... .... ....... .... ........... ........ ... .... .... .... ... .... .... .... .. 9-1 o
9.9 ........... The Sine/Quasi-Sine RMS Comparator and its System Environment........................................................... 9-19
9.10 ......... Sine/Quasi-Sine RMS Comparator - Block Diagram ..................................................................................... 9-20
9.11 ......... Sine/Quasi-Sine RMS Comparator - Sequence Cycle................................................................................... 9-20
9.12 ......... Sine/Quasi-Sine RMS Comparator - Sequence Timing................................................................................. 9-22
9.13 ......... Comparator Timing 9-25
9.14 ......... Three Stages of Output Build-up from Zero................................................................................................... 9-29
0-6
Section

10 10.1 ......... Basic Voltage-to-Current Converter .. .... .... .... ... .... ........ ... .... ........ ... .... .... .... .. ..... ........ ....... .... .... ... .... .... .... ... .... 10-1
10.2 ......... AC Current Generation .................................................................................................................................. 10-1
i 0.3 ......... Current Range Configurations .. ........ .... ... .... .... .... ... .... .... ....... .... .... .... ... ... ..... ....... .... .... .... ... .... .... .... ....... .... .... 10-3
10.4 ......... Routing ol Functions on Curren! and/or Ohms Assemblies........................................................................... 10-6
10.5 ......... Typical Clamped Buffer.................................................................................................................................. 10-8

0-7
 PART1

CALIBRATI IN
INF

SECTiON 1 Calibration

SECTION 2 Fault Diagnosis

SECTION 3 Dismantling and Reassembly

SECTION 4 Servicing and internal Adjustments

SECTION 1 CALIBRATION
1. Routine Calibration procedures are given in the User's Handbook, Section 8.
2. Users are recommended to have first completed the Verification Procedures in Section 7 of the User's Handbook.

1"1 GUIDE TO CALIBRATION

Circumstances Calling For Subsequent Recalibration

SCHEDULED RECALIBRATION CRITICAL PART CHANGES

Routine calibration is carried out from the front panel, avoiding Recalibration (or Verification) is necessary after replacement of
thermal disturbance and allowing immediate return to use. The a critical PCB assembly or a critical component. These are listed
4808 is fully calibrated before leaving the factory. The. in Table 1.1 (seepage 1-2 ), indicating theextentoftherecalibration
specifications for the 4808 are based on standard intervals of up necessary.
to 24 hours, 90 days or 1 year from calibration. Some users will
wish to maintain the highest accuracy by recalibrating at short Ohms Internal Adjustments
intervals (e.g. every 24 hours). In these cases, recalibration
If the Pow0r Supply/Current Heatsink has been changed it
becomes a routine task. For this reason, Routine Autocalibration
may be necessary to adjust the quiescent bias current (IQ) by
procedures are given in Section 8 of the User's Handbook.
internal adjustment. Refer to Section 4.7 for further
Users may wish to choose alternative schemes, accounting for: information.
The accuracy required when in use, If a standard resistor value has been changed by subjecting it
The instrument specifications (User's Handbook Section 6) to undue stress, it may be possible to recalibrate by internal
The scheduled calibration intervals normally adopted by the adjustment. Refer to Section 4.4 for further information.
user's organization
The Routine Calibration procedures are sufficient for all normal
recalibration purposes, except whenPre-cal is called for (Refer to Recalibration Procedures In Section 1
Table 1.1).
REMOTE CAUBRATiON VIA THE IEEE 488 BUS
RESTANDARDIZATION
The device-dependent commands necessary for routine calibration
Occasions may arise when it is necessary 1:0 trim the instrument's of the instrument over the IEEE 488 bus are described in Section
internal Master Reference. For example, when the 4808 is to be 5 of the User's Handbook. A guide-line example is given in
made traceable to a different National Standard, after Sectioril .2 ofthis manual, but this needs to be adapted for the bus
transportation from one country to another (Refer to AUTOCAL controller in use.
FACILfI'IES page 1-5).
PRE-CALIBRATION PROCEDURES (Section 1.3)
CALIBRATION MEMORY CORRUPTION
In an initial internal calibration process at manufacture, certain
Battery Change 'Pre-cal' parameters are established in a special calibration
Calibration constants are stored in an internal memory which memory.
remains energized by a battery. The Lithium battery which Under certain conditions (detailed in Table 1.1) these parameters
powers the non-volatile calibration memory should be replaced need to be re-established by completing the 'Pre-Cal' procedure
after5 years (RefertoSection4.3 ). Afterreplacement, afullPre- before a Full Routine Autocalibration.
calibration is required followed by a complete Routine
Autocalibration.
REMOTE PRE-CALIBRATION
Memory Check failure A guide line example is given in Section 1.5, but this needs to be
adapted for the bus controller in use.
Whenever the CAL key is pressed, new calibration constants are
checked to be within prescribed limits before being stored.
Values outside prescribed limits flag a Fail 6. The same check
is also performed:
When the instrument is powered-up
Each time the output is switched ON
During each self-test routine

1-1
 Assembly Components Replaced Calibration Required

Digital Complete Assembly Pre- & Routine Calibration

(1'1.2) lithium Battery (Sect. 4.3) Pre- & Routine Calibration
Non-volatile RAM (M1 O/M23) Pre- & Routine Calibration
Non-volatile RAM Supply
commutation components Pre- & Routine Calibration

Refiarene@ D!v!der Complete Assembly Pre- & Routine Calibration

Reference Assembly (11.4-1) Pre- & Routine Calibration
Any set of main, guard or
LSD switch FET's Pre- & Routine Calibration
Reference Buffer Pre- & Routine Calibration
Switch Driver Flip Flops or
their preselected resistors Pre- & Routine Calibration
R79 Pre- & Routine Calibration

DC Assembly Complete Assembly DC (All Ranges) only.

(11.5) 1V attenuator R73/R74 DC (1 V, 1OOmV, 1OmV, 1mV,
100µV Ranges) only.
1OOmV attenuator
R69/70/7i /72/75/7672/75/76 DC (100µV - 100mV Ranges) only.
1OOV/1 OOOV attenuator
R8/9/25/26/46/4 7/64/65/88/95/98 DC (1 OOV, 4OOOV Ranges) only.

Sine S01.1rc® Complete Assembly Specification Verification at

(H.6) User's Discretion

AC Complete Assembly Routine Calibration

{11 Sense Amplifier Routine Calibration
Reference Inverter Routine Calibratioi:,
AC/DC Transfer & Integrators Routine Calibration

Current/Ohms Complete Assembly DC/AC Current and Ohms

Current Assl!!mbl:lf' (N.B. Internal Adjustment required, DC/AC Current
(11.8) refer to Section 4.4)

+ 10 attenuator (R43/44) DC Current

(DC! function)

Current shunts R8/9/i 0/79/80 DC Current

(DCI function)

M8 and associated components AC Current

Current shunts AC Current
Feedback resistor R45 AC Current

Current/Ohms Standard Resistors, associated Internal adjustment (Section 1.4)

Ohms Assembly pre-selected/variable trimmer Ohms calibration (replaced values only)
(11.8) resistors (Ohms function)

All Other Assemblies Not Listed Above Specification Verification

at User's Discretion

Table 1.1

---------------~~- - - - -
1-2
PREPARING THE 4808
IEEE 488 ADDRESS
(LOCATED ON THE REAR PANEL)

Before any calibration is carried out, prepare the 4808 as follows:

SET TO: ADD 11111 (ADDRESS 31)
1. Tum on and allow a minimum of 2 hours to warm up in the
5 4 3 2 1 'O' '1'
specified environment

Z. Cancel any MODE selection keys, ensure OUTPUT set to

OFF.

3. IEEE 488 Address switch:

Set to ADD 11111 (Address 31) unless the 4808 is to be ADD
calibrated via the IEEE 488 interface.

4. CALIBRATION ENABLE key switch:

Insert Calibration Key and turn to ENABLE. SECURITY KEYSWITCH
(LOCATED ON THE REAR PANEL)

These actions activate the four calibration modes (labelled in red

SET TO: CAL ENABLE
on the front panel), and present the cai legend on the MODE
display.

Caution
Inadvertent use of the cal key can overwrite the calibration
memory!
CALIBRATION
ENABLE )t CALIBRATION
ENABLE

'~

CAUTION: WARNJ[NG:
Re-configuration of measurement circuitry should only be
attempted when all voltage sources are OUTPUT OFF.
Te:rmmal.s marked with t h e ~ symbol carry the
m.1.tput of the 4808. These teirminals and any otheir
Before setting OUTPUT ON ensure !he correct polarities have iconnectfons to th.e load under test icmdd icanry lethal
been selected and that any measurement device has been set t:o voltages, Under no dricuimstanices should users touch
low sensitivity. liB!TI!Y of the frm1.t (or :rear) panei terminals unless they
are first satisfied that no dlangernl!lls woitage fa present
NOTE
The message Error 3 appears on the left-hand MODE display for
any attempt to select an inappropriate mode.

SET TO: RUN

RETURNING THE 4808 TO USE

CALIBRATION CALIBRATION
ENABLE ENABLE

~~
When any calibration is completed, return !he 4808 to use as
follows:

1. Ensure that Output off LED is lit

)f
2. CALIBRATION ENABLE key switch:
Turn to RUN and withdraw calibration key. SET TO: CORRECT ADDRESS
(for your system)

3. IEEE 488 Address switch: 5 4 3 2 1 'O' '1'

Restore to correct address if the 4808 is to be used in an
IEEE 488 system.

The cal legend and calibration modes are deactivated.

ADD

1-3
EQUIPMENT REQUIREMENTS
Before removing the 4808 from service check that the necessary 2°wire HF compelllsation (1 V to lOV)
calibration equipment is available. The equipment summary, An AC DVM of suitable accuracy
listed by function, relates to the procedures recommended in this Example: Datron 1281
handbook:
Caution MHl.ivoltill at LF(lmV to l OOmV)
A commercially-available Inductive Voltage Divider of suitable
When choosing a set of current shunts ensure that their power
accuracy and frequency response; with ratios of 10: l, 100:1 and
dissipation ratings are sufficient to avoid permanent degradation
1000:1.
from the self-heating effects of the current being checked. This
Example: Tinsley 5560J
applies particularly to the lAmp shunt.
An AC DVM of suitable accuracy and frequency response.
Example: Datron 1281 or similar.

DC FUNCTION Millivolts at HF (lmV to 100mV)

An AC DVM of suitable accuracy and frequency response.
Low Voltage (lOOmV to lOV) Example: Datron 1281 or similar.
An adjustable DC Voltage source of suitable accuracy
Example: Datron 4000A Autocal Standard Current (lmA to lA)
A DC Current Source of suitable accuracy.
A battery-operated null detector with variable sensitivity, able to
Example: Datron 4000 or 4000A Autocal Standard
withstand 1200V across its input terminals:
Example: Keithley Instruments Model 155 AC/DC Thermal Transfer and a set of Calibrated Thermal-
Transfer Current Shunts of suitable accuracy.
High voltage (lOOV and 1000V) Example: Holt 6B and HCS-1 AC/DC Shunts.
A Precision Divider An AC/DC transfer switching unit
Example: Datron 4902/S High Voltage Divider. Example: Holt HCS-1
A battery-operated null detector wit_h variable sensitivity, able to
withstand 1200V across its input terminals: C111nrre1Tut (Aitemate) (lµA to lA)
Example: Keithley Instruments Model 155 A set of calibrated AC Shunts of suitable value S!.lld accuracy.
Example: Tinsley 5685 AC/DC Standard resistors.
Cmrrient (lOOµA to lA) An AC DVM of suitable accuracy and frequency response.
A DC Voltmeter, of suitable accuracy standardized at 1V and Example: Datron 1281 or similar.
lOOmV.
Example: Datron 1281. A Buffer capable of operating with negligible errors from DC to
5kHz at a 1Volt level
A set of calibrated. current shunts of suitable accuracy o

Example: Tinsley 5685 "Wilkins" Standard Resistors.

RESIST ANICE
AC FUNCTION 2°Wi.re & 4°Wire (10n to lOOMn)
A set of standard resistors covering 1on to 1OOMn. The 1on to
Voltage (lV to 1000V) lOkn should be 4-wire type.
An Adjustable DC Voltage Source of suitable accuracy. Example: For 10n - lOkn Tinsley 5685
Example: Datron 4000 or 4000A Autocal Standard. For lOOkn - lOMn Guildline 9330

An AC/DC Thermal Transfer Standard capable of operating over An accurate resistance bridge, or other ratiometric device for
the range lV to 1100V RMSo measuring resistance to the required accuracy.
Example: Characterized Holt 6B A Datron 1281 used as a transfer-measurement device.

1-4
AUTOCAl FACILITIES
These keys are activated by two rear panel switches (refer to page 1-3 'Preparing the 4808'). When lhese modes are active, the legend
'ea!' is presented on the left-hand MODE display.
The following is a general description of the facilities available. For specific information see the introduction proceeding each of the
function's calibration routines.

CAl ±0 I SPOT
The 4808 assumes that the selected range is to be calibrated at the On the DCV function, the ±0 key is used to align the ON+ and
exact Full Range value or at Zero. The instrument decides on ON- zeros of all DC voltage and current ranges, by a two part
'Zero Offset' or 'Full Range Gain' from the right-hand OUTPUT calibration on the lOV range. Itis only necessary when the ON+
display value (defined by the same limits as for 'SET'), and and ON- zeros of the 1OV range do not coincide at the same null.
executes the calibration. If the value initially set on the OUTPUT
On the ACY and ACI function, the function of the key changes
display is below 2% of Full Range value, the inslrurnent assumes
to SPOT Frequency calibration. When SPOT is pressed, the4808
that anoffsetcalibrationisrequested, and if at2% or above, again
assumes that the spot frequency is to be changed, and so defaults
calibation is assumed.
the frequency to lkHz. When used with SET, SPOT calibration
can be carried out within 10% of the full range value, but when
CAl (wittn SPOT is used without SET, the4808 assumes that the calibration
If the CAL key is pressed after first pressing §TD, §lE'f or±O, the is to be at Full Range. After SPOT calibration, selecting Spot
CAJL key executes, then cancels, the preselected AUTOCAL Frequency at the calibrated value achieves the highest possible
mode. accuracy (see User's Manual, Section4). It is only necessary to
perform Spot Frequency calibration if the accuracy achievable is
Cautiollll required in use. For recall procedures see the User's Manual page
The following keys preselect an AUTOCAL mode, modifying 4-10.
the action of the CAIL key.
STD
SET
Cal.lltirnm
The SET key allows gain or offset calibration to a Calibration Using the STD key changes the gain of all voltage and current
Standard value which cannot be adjusted to a nominal Full Range ranges.
value or to absolute zero.
The STD key allows a user to re-standardize by trimming the
Before selecting SET, the keys are operated to place the value of the internal Master Reference voltage effectively changing
Calibration Standard value on the OUTPUT display and set the the gain of all DC voltage and current ranges in the same ratio.
4808 output level. The facility can be used to avoid a full recalibration of the 4808
Pressing SET then informs the 4808 that calibration is to be when Laboratory References have been re-standardized (for
carried out at this value. The instrument acknowledges by instance when the instrnment has been moved from one country
duplicating the value on the MODE display. to another).
First check ±0 Alignment. The STD calibration is carried out on
Next, the C keys are manipulated to null the 4808 output against
either the 1V or lOV range, using the DC Low Voltage procedure.
the Calibration Standard (the OUTPUT display changes during
Select STD after placing the Calibration standard value on the
this adjustment).
OUTPUT display. Continue the routine fromstep(l). Procedurally
Pressing the CAL key executes the calibration. The 4808 STD differs from SET only in the use of the STD key instead of
memorizes the difference between the two display values, and the SE'f key.
exits from SET mode. This is shown by transfer of the Standard
value from the left-hand MODE display to the right-hand
OUTPUT display. The instrument uses the difference to modify
stored constants, which in 'RUN' mode correct both positive and
negative outputs on the calibrated range only.

1-5
GENERAL NOTES

INTERCONNECTIONS GENERAL PROCEDURE

lt is recognised that interconnection instructions may need to be Prepare Lhe instrument for calibration (refer to rr·ev,rin.nll' the
adapted to meet ar1 individual user's requirements. It is assumed 4808' procedure onpagel-3). Note that your instrument will not
that users will possess some knowledge of the operation and use necessarily have all options fitted
of standards equipment.
The available options for the 4808 are as follows:
SENSE AVAilAIBiUTV AS
Option 10: DC Voltage function to ±200V.
1V lOV 100V 1OOOV - Local/Remote Sense
lmV lOmV lOOmV Local Sense only Option 20: AC Voltage function to 200V.
i'.1,11 current ranges not applicable Option 30: Integral 1OOOV amplifier for AC Voltage and/or
(Local: 2-wire sense, Remote: 4-wire sense) DC Voltage functions. (Requires either Optior.
Output must be OFF to change sense connection (except that 10, Option 20 or both.)
Rernoic changes automatically to Local when switching to Option 40: Current converter to provide DC Current and AC
Millivolt Ranges). Current functions. (DC Current capability
requires Option 10, AC Current capability
OUTPUT OFIF !IJJEIFAUl T WHEINI UPRANGiNG requires Option 20.)
The 4808 cannot enter High-Voltage state with OUTPUT ON. Option 50: Resistance function. (Requires Option 10 or
Consequently, when ranging-up, the operating system allows the Option 20.)
upranging to occur, but defaults to OUTPUT OFF for two
Option 60: DC Current and/o:r AC Current range extension
specific cases:
to 1 lA. This option includes the Datron 4600
:J.. When upranging to the· 1000V Range. Transconductance Amplifier and all necessary
cabling. (Requires Option 40.)
2.. When upranging to the lOOV Range:
To a voltage of 90V or more on DC
The message 'Ermr 3' appears on the kft-hand MODE display
To a voltage of 75V or more on AC
for any attempt to select an inappropriate mode. Select the
Otherwise, OUTPUT remains ON when changin.g OUTPUT equipment and procedures to be used. Set all sources to zero and
RAl\JGE. all measurrnentdevices to low sensitivity and configure using the
Refer to User's Handbook, Section 4. interconnection diagram provided. If calibrating DC function,
start wit_h ±0 Alignment check routine. When all calibration has
been completed use the 'Return to Use' routine on page 1-3.

Set the 4808 to OUTPUT ON and Full Range value. Adjust the
4808 output to equal the calibration standard and press CAJL. The
right-hand OUTPUT display changes to nominal.

The OUTPUT display is setto the Calibration Standard value, the

4808 output is switched ON, and one of the calibration mode
preselector keys (STD, SE'Jf or ±0) is pressed. The 4808 output
is adjusted to equal the Calibration Standard value, and the CAL
key is pressed to execute the calibration.

1-6
1,2 REMOTE CAUBRATION GUIDEUNES
The operation of the instrument in systems applications via the IEEE 488 interface, is described in Section 5 of the User's Handbook.
fa addition to its capability as a programmable calibrator, the 4808 can itself be calibrated under remote control. Full autocalibration of
the instrument over the bus implies availability of a suitably programmed controller, programmable standards, programmable Null
Detector, and a programmable Thermal Transfer.

Transfer of Calibration Facilities

cam:nauon Commands
The table below lists the device-dcpenda_nt commands used for When the4808 isunderremotecontrolover the bus, thecommand-
P,outine Calibration. The relevant calibration codes are also code W0 overrides the settings of the CALIBRATION ENABLE
listed. andintemalPRE-CALIBRATIONENABLEswitches,disabling
t_he 'C' codes.
These commands can only be activated when two conditions
have been fulfilled:
Geneiral Pmcedl!lr@
ll. theCAUJRRA 'fllON ENABJLJEkeyswitchon the instrument The Main Register is set to the Calibration Standard value
Rear Panel must be set to ENABLE, and (M*':'* ... ), the 4808 Output is switched ON (01), and one or a
2. the IEEE Interface command-code Wl must have been specified sequence of the calibration mode comma.nd codes (C 1,
received and activated. C2, C3, I) may be transmitted.
Additional commands can be activated when 'PRE-CAL The 'M' Code is adjusted to obtain a null at the Calibration
ENABLE' switch is enabled. Refer to 1 5 Remote Pre-Calibration Standard value, and C0 is transmitted to execute the calibration.
Guidlines.

A vai.fabHiity of Commallull Codes

CommaB1d I
Codes I
'(Key caps! DC Voltage DC Current AC Voltage AC Current 2-Wire Q 4-Wire Q

I C!Ql I Range Zero 100mV-1000V

I (CAL) Ranges

Gain calibration 100mV-1000V

to Nominal Full Range Ranges
I
*Ci Zero offset for All
(SET) range at User's Ranges
selected value

Gain for range at All

User's selected value Ranges

·c2 Internal Reference 1V &10V

(STD) gain at user's Ranges
Standard value

*C3 Alignment of 10V

(±0) internal ON+ and Range
ON- zeros

User's Message Refer lo User's Handbook Section 5 'Programming ol Bus Transmissions'

*Preselector - must be activated later by command code C0 (CAL)

1-7
COMMAND CODE FACILITIES (Routine Calibration)
For a General description see 'Autocal Facilities' page 1-5.

CaiibraUoirn Codes
C1 (SET) T'ne following AC command strings are given for the sole
Cl gives calibration at any point in the selected range by purpose of illustrating the methodology designed into the 4808
allowing the user to input the value of the calibration standard for remote calibration modes. Some reference to external
used (initial M code used). Before executi.i,g the calibration operations is inferred. The nulling operation is seperated into its
C0 uses the final 'M' Code value to distinguish between Zero own string, as it is likely to be iterative.
(offset calibration) and Full Range (gain calibration). The It is assumed that the 4808 has previously been programmed L11
limits of Offset or Full Range depend on function selected function and range (not autorange R0) and that the external
(Refer to User's Handbook, Section 8). circuit is set up correctly. The 4808 is already programmed into
its calibration mode by Wl, with the calibration keys witch set to
C2 (STD) ENABLE, and output OFF.
C2 allows a user to compensate for changes of the internal
a. Nominal Full Range LF Gain Calibration:
Master Reference voltage. For best accuracy it is
H(LF)AlOl=M (for null)=C0=00=
recommended this procedure is carried out in DC function.
Note that the gains of all voltage and current ranges change b. Nominal Full Range HF Gain Calibration:
in the same ratio. Execute with C0. H(HF)Al Ol=M(for null)=C0=00=
I[;. Combined Nominal LF and HF Gain Cal:
C0 (execute pre-selection) H(LF)AlOl=M(for null)=CO=
C0 executes one of the above preselected AUTO-CAL H(HF)=M(for null)=C0=00=
modes.
«JL Non-nominal LF Gain Calibration:
H(LF) M(20%-200%FR)Cl=
C0 only)
Ol=M(for null)=C0=00=
If CommandC0 is sentwithoutpre-selectioncodeCl/C2 the
instrument assumes that the selected range is to be calibrated e. Non-nominal HF Gain Calibration:
at either Zero or Full Range. It uses the value input by the 'M' H(HF) M(20%-200%FR)Cl=
Code to distinguish between Zero (offset calibration) and Ol=M(for null)=C0=00=
FullRange(gaincalibration) according to the function selected t Combined Non-nominal LF and HF Gain Cal:
(Refer to User's Handbook, Section 8). H(LF)M(20%-200%FR)Cl=
Ol=M(for null)=C0=
H(HF)M(20%-200%FR)Cl=
The following sequence suggests a method of calibrating Lhe M(for null)=C0=00=
instrument 1V Range Gain against a buffered standard cell value g. Standardization at Nominal Full Range
of + 1.018057V. It is assumed that the instrument is correctly 1V or IOV Range only):
addressed with its Calibration Keys witch setto ENABLE and the H(LF)Al C20l=M(for null)=C0=00=
instrument Output is OFF. Connect the Null Detector, set to low
sensitivity, between the Standard Cell buffer and the 4808. The 11:i!. Standardization at a Non-nominal value
nulling operation is seperated into its own string, as it is likely to (l V or lOV range only):
be iterative. H(LF)M(20%-200%FR)C2=
Ol=M(for null)=C0=00=
SET Calibration of 1V DC Gain
F0R5G0S0W1M+ l .018057Cl01=M(for null)C0
The example suggests only the broad outline of one of many
sequences which could be used to perform instrument calibrations.

1-8
1.3 PREmCAUBRATION
1.3.1 Introduction,

GENERAL PREPARING THE 4808

In an initial calibration process at manufactme, certain 'PRE- Before clearing the pre-calibration store, prepare the 4808 as
CAL' parameters are established in a special calibration memory described on page 1-3. The adjustments detailed in the follov,ing
to define the overall linearity of the instrument, and to allow sequences include intentionally clearing the instrument's pm-
maximum routine calibration memory span for adjustments. For calibration memory, which loses ALL previous calibration
normal purposes, these factory defined pre-calibration parameters information. Therefore before proceeding make certain that the
are valid for the life of the instrument, and subsequent Routine reasons for carrying out a complete recalibration are valid. (If in
Calibration procedures are sufficient to maintain calibration. a..11.y doubt, consult your Datron Service Centre)
Preparation for the pre-calibration operation includes removal of
the Top Cover, to facilitate selection of pre-calibration mode and
operation of the calibration memory clear push-button. DC and
AC pre-calibration must then be completed followed by a Full
Routine Recalibration. Thereafter, all routine calibrations may
be performed from the front panel or over the IEEE Interface
without removing the covers.

The stored parameters are invalidated by replacement of certain

critical parts of the instrument.
The Lithium battery which powers the whole calibration
memory when the instrmnent supply is switched off. This
should be replaced at five-year intervals (Refer to Section
4.3).
The Digital Assembly
The Reference Divider Assembly
Critical components in the Digital or Reference Divider, AC
and Sine Source assemblies
A full list appears on of page 1-2. After replacement of any
of these parts, new parameters must be stored in the pre-calibration
memory, by procedures (in manual orremote control) detailed in These holes provide access to the 'PRE-CAL ENABLE' switch
this section. and the 'CLEAR CALIBRATION MEMORY' switch.
!!I, Release 6 screws retaining the top cover.
!EQUIPMENT IEMENTS i:Ji, Lift the top cover at the front of the instrument and locate the
two holes which give access to the two-position 'PRE-CAL
DC ENABLE' switch and the press-button 'CLEAR
A precision divider capable of dividing 20.000,000V to CALIBRATION MEMORY' switch.
10.000,000V to a ratio error of better than O.lppm between
tappings. For example a Datron 4902/S precision divider or c, Locate the hole which gives access to the PRE-CAL ENABLE
alternatively a Datron 4903 DC Calibration Unit. switch. Insert an insulated tool in the hole and move the pre-
cal switch to the right (Enable). The legend 'cru', as presented
A DC 1OV reference with an accuracy of better than 2ppm. on the left-hand MODE display, also appears on the right-
Example: Datron Instruments 4000A or a bank of standard hand OUTPUT display.
cells.
Caution
The following operation (d.) clears all the calibration memory
AC
stores as part of pre-calibration. Proceed only if this is required.
A precision voltmeter capable of 1V AC measurement with
a stability between readings of better than ±5ppm. d. Locate the hole which gives access to the Calibration Memory
Example: Datron Instruments 1281 CLEAR push-button. Insert an insulated tool in the hole and
press the button to clear the calibration memory.
An inductive voltage divider with ratios of xl.O and x0.1
capable of dividing 10.000,00V to 1.000,000V to an accuracy c, Refit the top cover but do not secure.
better than 2ppm. Complete the following pre-calibration procedure
An AC/DC Thermal Transfer Standard. (Paras 1.3.2 overleaf).
Example: Holt Model 6B

1-9
1,3.2 Procedure
DCV Prncal
± Zero CaiibraUoi11
First complete the ±0 Alignment Calibration Procedure in Section 8 of the User's Handbook, but with pre-calibration mode selected.

PRECISION DIVIDER
(a.g DATRON 4902/S)

Remote Guard
Remote Sense

10k

Local Guard
Local Sense

DCV Precal
Ensure the 4808 OutplLlt off LED is lit, cancel any MODE select Remote Sense and deselect Remote Guard. Select DCV
FUNCTION and lOV RANGE. Connect the Precision Divider to the instrument tem1inals as shown. Use short leads.

Coaiwse G£lliWI Urue©1rhly

21. 4808 If. PireciisfoJJlli ll.JJrrv!dler/Nlll!Ilil Dettedoir
Ensure OUTPUT OFF and select the lOV RANGE. Reduce Null Detector sensitivity. Reconfigure Null Detector
Hi to divider 20V tapping.
b. lP'iredsfollli Diivndeir/NUJtilil Detedl[)Jr
Set the Null Dectector to Low sensitivity and connect to the g. DC §ttamfall'WN11Jlllll Deiedo.
Precision Divider at lOV tapping. Jfthe DC Stand,ud is a buffered bank of standard cells, switch
the Buffer output to zero. However if an electronic reference
IC, 4808
is used, connect the Null Detector -ve lead to the DC
Connect to the precision divider as shown. Select ON+ with
Standard's Low terminal.
zero OUTPUT.
Set Null Detector to high sensitivity. Zero Null Detector.
di. DC Stam:fa1n:ll/Ni!1Illl Detertm· Increase Null Detector sensitivity.
If the DC Standard is a buffered bank of standard cells, switch
a.,
the Buffer output to zero. However if electronic reference Switch on oneconnectthe 1OV reference Hi to Null detector.
is used connect Null Detector -ve lead to Reference Low. lln, 48ijtJ
Set Null Detector to high sensitivity. Zero Null Detector. Select STD, its LED lights. Press ON+ and Full Range
Reduce Null Detector sensitivity. OUTPUT (10.000000V).
Switch on or reconnect the lOV DC Standard Hi to Null j, NMlill Detector
detector. Increase Null Detector sensitivity and use4808 OUTPUT()
ie. 4!808 keys to adjust the reading to zero.
Select SET, its LED lights. Adjust the OUTPUT keys for lk. 4808
Full Scale OUTPUT (+19.999999V). Press the CAJL key: the STD LED goes OFF. Pre-cal is now
completed. Select OUTPUT OFF and disconnect.
Use instrument OUTPUT keys to adjust the Null Detector
reading to zero.
Press CAL: the SET LED goes out.

1-10
ACV LF Precal

AC DVM (mV RANGES) CALIBRATOR

Local Guard (AC mV RANGES)

(shorting
link)

ACV lF Priecal U1r1earity Setup

Ensure the 4808 0!.lltput ({]Jn LED is lit, cancel any MODE keys, select Remote Sense and deselect Remote Guard. Select ACY
FUNCTION and connect the IVD to the instrument terminals as shown. Use short leads. Select the lkHz Frequency Range.

10'%, Range fu!i Rar1ge

a, XVD t, IVD
Select xl.O ratio. Select the xO.l ratio to divide the 4808 output by 10.
!bi, 4808 dL 4808
Select 10V range, at lkHz on the lkHz Frequency range. Select Full Range. Use instrument OUTPUT keys to
Select 1.000,00V. Press the ±Ol key, its LED lights. Use adjust !he DVM reading to l V. Press the CAIL key: the ±0
instrument OUTPUT keys to adjust the DVM reading to LED goes OFF. Recheck, without pre-selection, at l V and
l V. Press CAlL: the ±0 LED remains lit and 1.000,00V 10V. Ifrequiredrepeatiheprocedure. SelectOUTPUTOFF
(nominall0%FullRange)appearsontheright-handOUTPUT and disconnect. Pre-cal is now completed. Disable pre-cal
display. and complete a Full Routine Calibration.

1-11
ACV HF Precai
DC Standard Therma.i Transfer 4808
Remote Sense and Remote Guard Remote Sense and Remote Guard

ACV HF Pirecal Unea1r!ty Setup

With OUTPUT OFF, connect the 4808 and DC Voltage Stondard to the Thermal Transfer AC and DC inputs, respectively.

10'%, Ranige full

a, 4808 e, DC Volltage Stm11dmrd!
On AC function, select the lOV range, select the 1MHz Set to lOV Output, select OUTPUT ON.
frequency rangeand use the FREQUENCY() keys to display IL Tbermall 'frnm,fieir Srarrul.21irdi
1MHz. L se the OUTPUT () keys to output 1V and set Configure for DCV measurement at the 1OV level and adjust
OUTPUT ON. Press the SPOT key. for Null. Configure for ACY measurement at the lOV level.
!bi, DC VoUage Stmmdmrdl g, 4808
Set to l V output and set OUTPUT ON.
Press Full range key to display 10V and use the OUTPUT
c, TlhieirmrnaR Trmru§fer Srallllda1rd keys to obtain a null on the Thermal Transfer. Press the CAL
Configure for DCV measurement at the 1V level and adjust
for Null. Configure for ACV measurement at the 1V level.
oL '1!808
Use the OUTPUT () keys to adjust the OUTPUT display
reading to obtain a null on the Thermal Transfer Standard.
Press the CAL key.

When pre-calibration is complete the pre-cal enable switch must

be set to RUN.
CAUTION: DO NOT ][.ffil!S§ tllile mttem21l puslrn-l:mUoIT11 wlrnklrn
clears the cailibll'llltfoJrn mem.ory, If this is dmi.e, any parameters
stored !Im the caUbr2tkm memory are cleared; so pre-
c21HiraUm1t is ca111.cellled, :md mlllst be repeaitedl.,
a, Lift the top cover at the front.
b. Locatetheho!ewhichgivesaccesstothePRE-CALENABLE
switch.
c, Insert an insulated tool in the hole Pre-cal and move the
·-
1'1 ...- -
l,Ja~I"~' ti
'f'yhh

switch to the left (RUN). The legend 'call' remains on the

MODE display, but disappears from ilie OUTPUT display.
d, Refit and secure the top cover.
A Full Routine Calibration is necessary before completion of the
Return to Use procedure on page 1-3.
1,4 INTERNAL OHMS ADJUSTMENT

The Autocal procedure for routine calibration of the 4808's

Resistance function is described in Section 8 of the User's
Handbook.
The method of calibration is to measure the value of each
standard resistor, and store the measured value in non-volatile
calibration memory. Subsequently, each time aresistance RANGE
is selected, the previously calibrated value is displayed.
If a standard resistor has been subjected to undue stress, its value
may have moved outside its tolerance (signalled by an Error 6
message during Routine Autocalibration). If the value is less
than approx. 50ppmoutside tolerance, it can be adjusted internally
using a variable trimmer. For values out of tolerance in excess of
50ppm it is likely that the resistor has been over-stressed, in
which case consult your Datron Service Centre.

Manual Trimming Procedure

The following procedure is a supplement to Routine
Autocalibration. It is necessary only when the 4-wire calibration
detailed in Section 8 of the User's Handbook has resulted in an
'Error 6' message.
It can also be used when, for operational reasons, it is necessary
to adjust a resistor to its nominal value. For this purpose a
continuously-reading method of measurement is convenient.

21. Release eight screws retaining the top cover.

ill. Lift the top cover at the front of the instrument and locate the
8 holes giving access for 'Q OPTION ADJUSTMENT'.
c. Insert an insulated screw driver tool in the hole for the range
selected, and adjust the preset resistor (rotating clockwise
increases the resistance value).
d. Re-measure the 4-wire value and repeat operation (c) until
the desired value is obtained.
e. Re-calibrate the range for 4-wire and 2-wire connections as
detailed in Section 8 of the User's Handbook.
f. Repeat the manual trimming procedure above for all ranges
as required.
g. Finally refit and secure the top cover using the eight screws
removed in (a), above.

1-13
1,5 REMOTE PRE~CAUBRATION GUIDEUNES

Transfer of DC pre-calibration facilities Transfer of AC pre=calibration facilities

General Prncedme

The tra..'1sfer of Pre-calibration facilities to remote control is Tne string sequence for DC pre-calibration is as follows:
illustrated above. The general procedure follows that for remote
Routine Calibration; the external circuit is connected as for L ±Zern
marmal pre-calibration.
F0R6M+001C3= (Set-up and ±0 preselection)
These commands C6J1 only be activated when Lhe following M''**= (Iterative nulling operation)
conditions have been fulfilled: C0=M-0= ('CAL' and -ON)
The CALrnRA TION JE;l[AJB:JLE key switch on the Iv!**''= (Iterative nulling operation)
instrument. Rear PaIJ.el must be set to ENABLE. C0=00= ('CAL' then OUTPUT OFF)
Ensme that the IEEE address switch is set correctly.
The IEEE Interface comma.nd-code Wl must have been
received and activated. F0R6C4M+ 19.99999901= (Set-up and linearity
The internal PRE-CAL ENABLE switch is set to JEN AJBLE. preselection)
\Vhen t.1-te 4808 is underremote control over the bus, the com.rnand lVI***= (Iterative nulling operation)
code W0 overrides the setting of the CALIBRATION C0=00= ('CAL' then OUTPUT OFF)
ENABLE and internal PRE-CAL ENABLE switches, C5=M+ 10.00000001= (Set-up and linearity
disabling the 'C' codes. preselection)
M,;,:,,,= (Iterative nulling operation)
C0=00= ('CAL' then OUTPUT OFF)

The following command strings are given for the sole purpose of T'ne string sequence for AC pre-calibration is as follows;
illustrating the methodology for the remote pre-calibration mode.
Full Range and 1/10th Ra.i,ge Linearity;
Some reference to external operations is infeITed. The nulling
first for LF, and then for HF
operation is separated into its own string, as it is likely to be
iterative. (Program to frequency and
It is assumed that the external circuit is set up correctly. voltage)
M'"·'··'_ (Iterative nulling operation)
The 4808 has already been programmed into its calibration mode C0=M•:,,:,*= (First 'CAL' of two-part
by Wl, with the CALillRATJION ENABLE keys witch and the process)
internal PRE-CAL !ENABLE switch set to ENAJBJLE. (Iterative nulling operation)
The calibration memory stores have been cleared, and the 4808 C0=00 (Second 'CAL' cancels
Output is OFF. preselected mode)

1-14
 Appendix 1 to
4808 Reference Handbook
Section 1

Notes on the Use of the Nu!!

The Null Detector is normally connected in series with the 4808 Hi lead. A high-impedance-input device should be chosen to reduce off-
null currents due to differences in the outputs of the DC voltage source and the 4808. A battery-operated instrument is preferred to ensure
adequate isolation.
Some Null Detectors possess high input impedance only when lheir readings 11re on-scale, so cme should be taken to ensure that drain
currents from the DC Voltage source do not become excessive. This applies particularly if the DC source is a standard cell or a bank of
cells.

Six points are important:

1. The null detector should be connected to the 4808 (or 4808 5. WARNING
load resistor) only when the4808 Output off LED is lit. (with During performance checks and calibration a common mode
output OFF, the I+, I-, Hi and Lo terminals are at high voltage equal to the full range voltage is present at the Null
impedance). Detector input terminals. On 1000V checks this voltage is
potentially lethal, so EXTREME CAUTION must be observed
2. Always set lhe null detector to its lowest sensitivity before when making adjustments to t_he null detector sensitivity.
connecting up, andincreasesensitivityonly when the voltages
output by the DC Voltage source and the 4808 are close in
value.
ifi. CAU'lflION
3. Do not change polarity of the 4808 or DC Voltage source The Null Detectorused must be able to withstand voltages up
without first switching the 4808 OUTPUT OFF. Care must to 1200V between its inpm terminals. Such voltages will be
be taken to eru;ure that the correct polarity on key is pressed, present during the time that the 4808 is ramping from zero to
to avoid excessive voltages being connected across the null lOGDV Full range after setting OUTPUT ON. Inadvertent
detector, particularly when checking the 4808 directly against disoormection of the Precision Divider terminals can transfer
a standard cell. full output across I.he Null detector.

4. Most Null Detectors are equipped with a 'Self-zero' or'Zero-

check' facility. For maximum accuracy, the Null Detector
range zero should be checked before each calibration nulling
operation is performed. However, when gain-calibrating the
4808 Voltage and Current Ranges, the zero offset of the
calibration voltage source is nullified by adjustment of the
Null Detector ±ero control. This setting should not be altered
until the corresponding Range gain has been calibrated.

1-Al
 Appendix 2 to
4808 Reference Handbook
Section 1

Calibration Source Zero Offsets

It is common practice to accept a small offset in the output of a The 4808 analog circuitry is fully floating, so its output may be
voltage calibration standard, providing that the same offset is referred to any common mode voltage within the range specified
present at all output values, including zero, inSection63 of the User's Handbook, In particular, each Range
zero may be aligned to absolute zero in Local Sense by calibration
A more difficult situation arises if there is a 'DC turnover offset' to a null across its Hi and Lo (Sense) terminals, But if it is then
between the source's positive and negative output values, In this gain-calibrated against an offset source without re-zeroing to that
case, a difference in DC value will be observed when switching source's offset zero, normal mode gain errors will result It is
the source between its positive and negative outputs with zero therefore essential that any offset in the source's output be
volts selected, 1bis type of error is normally adjusted out on the nullified before gain calibration is carried ouL 1bis can be done
4808 by a preliminary '±0' calibration on the lOV Range, to a null at Range zero, simply by trimming the Null Detector nulL
detected across its output terminals, 1bis sets both ON+ and ON-
zeros to the same DC level; and as the same linear analog
circuitry is used to generate both output polarities, range calibration
of zero and gain in positive polarity is then all that is required,

The notional sequence of calibration for the 4808 should be as follows:

l!io ±@
Check that the lOV Range 'ON+' and 'ON-' zeros coincide at 1bis sequence ensures that the 4808 'ON+' and 'ON-' zeros are
absolute zero (Adjust if necessary), both set to absolute zero, and that both positive and negative
polarities are accurately gain-calibrated to a unipolar source,
11:Jo lRallllge Zerns
Carry out 'ON+' zero calibration on all Ranges against the ][fit is required to check the 4808 'ON-' gain calibrations against
same absolute zero, a bipolar source, the source's 'ON-' zern offset must first be
nullified, as described in(«:, iL) opposite.
<Co Range G2h1t
Each Range Gain in turn, (Null Detector connections as
shown for Voltage or Current)
Ilo At 'ON+' zero output from both source and 4808, trim the
Null Detector for null,
!t At the required positive DC level, calibrate the 4808
Range gain,

1-A2
SECTION 2 FAULT DIAGNOSIS
WARNING CAUTION
HAZARDOUS ELECTRICAL POTENTIALS ARE The inslrument warranty can be invalidated if damage is
EXPOSED WHEN THE INSTRUMENT COVERS caused by unauthorised repairs or modifications. Check
ARE REMOVED. i:he warranty detailed in the "Terms and Conditions of
ELECTRIC SHOCK CAN KILL Sale". H appears 011 the invoice for your inslrument.

2.1 INTRODUCTION

2.1.1 Use of Diagnostic Guides

The diagnostic guides given in Section 2.2 are intended to aid the In normal use, an operator will probably notice only FAIL 5, and
user in locating a failed printed circuit board or other assembly. miss the original failure message. In FAIL 5 state, front panel
The self-diagnostic capabilities of the instrument provide the control is inhibited until Reset is pressed. This returns the
first step in fault analysis by displaying a FAIL message on the instrument to the state for which the original fault conditions and
left-hand MODE display. Initial actions to be taken after the failure message were produced, but with Output OFF.
occurence of a FAIL message are given, where applicable, in the
diagnostic guides ofSection2.2. TheFAILmessagelocalizes the 2.1.23 To Obsene the Original Failure Message
failure into a distinct functional area and the "Fault Condition"
Two procedures 11::1.m be used:
summary in each guide relates the function failure to a probable
hardware boundary. a. Carry out the self-test routine of Section 2.3.
The failure message may recur during !his test.
The identities of the assemblies involved in the failure are given
beneath the fault condition summary, but it is unlikley that all l:i. Reset the instrument to reproduce the fault, carefully watching
assemblies listed will°prove to be faulty. For successful failure the MODE display.
analysis, it is advisable to be familiar with the electronic The original failure message could reappear momentarily,
functioning of the instrument and with the physical location of prior to defaulting into FAIL 5.
the assemblies. 'fo assist in these aspects, the diagnostic guides Then select the appropriate diagnostic guide in Section 2.2.
include references to relevant parts of this publication.
'.U.3 JFAIL6
2.1.2 Effects of PrntedHve Measures Oi'i1 Dfagnos!§
FAIL 6 reports two types of NV RAM failure.
2.1.2.1 l?rntecUve Suppressi.mll of Fa1.dt Cm1ditkm,!l
a. Overall sumcheck failure.
The 4808 incorporates built-in protection in hardware and S:umcheck values are calculated at Power on, S:elf-'fest and
software. To minimize damage, protective circuitry acts recovery from FAIL. If the instruments stored calibration
immediately, backed up by a pre-programed CPU response ID constants are outside maximum or minimum permissible
detected failure symptoms. If possible the CPU informs the user values a Fail 6 message is displayed.
by presenting a failure message on the MODE display.
b. Limits check of the calibration constants.
When investigating a failure, it should therefore be anticipated Values are checked when read from the NV RAM at every
that protective measures will have suppressed the original fault OUTPUT change. When a Fail 6 occurs the output remains
conditions. A useful starting-point is to identify the origin of the on and the stored gain or zero correction value is defaulted to
failure message to localize the area of search. xl or xO respectively.

2.1.2.2 FAIL S as Default State

Faults which result in display messages FAll., 2, 3 or 4 can pose
a safety hazard to the operator, and apply excessive voltage to
external circuitry. To protect against this, the instrument is
programmed to default to FAIL 5 state as rapidly as possible after
its initial response to the failure symptoms. The CPU switches
Output OFF and trips the safety monitor (Watchdog). If the
conditions of the original failure message have been removed the
display changes to FAIL 5.

2-1
2"2 DiAGNOSTIC GUIDES

FAUL 1 (Excessive Internal Temperature) IFA!IL 2 (Over-Voltage)

!NITiAl INITIAL ACTION

1. Wait approximately l minute until lhe CPU has defaulted lhe 1. Ensure that OUTPUT is OFlF
instrument to OUTPUT OFF. The CPU clea..n, the lFAfl.. 1 (4808 should have tripped to FAfl.. 5).
message and enables the keyboard.
2. Power OFF any external voltage source.
Z. Switch OUTPUT ON.
N.B. This failure can be caused by injection of an external
3. No failure display - no further action. FAIL 1 recurs - fault voltage across the terminals OR the output of high voltage
persists. when not requested by the user.
DC - voltages in excess of 130V.
FAULT CONDITION
AC - voltages between the limits of 75V to l lOV RMS.
High temperature sensed in:
Positive Heatsink Assembly, or 2. Disconnect external leads from the terminals.
Negative Heatsink Assembly. 3. Press Reset.
Fault indication signal OVJERTEMP active. 4. Carry out self-test sequence.
5. FAIL 2 recurs - fault persists.
FAUlT
ifii. No failure display - Reproduce original conditions in Local
Positive Heatsink Assembly (page 11.13-1). Sense with no external connections.
Negative Heatsink Assembly (page 11.13-2). 7. No failure display - check external circuit and proceed with
careful use.
Power Amplifier Assembly
g_ FAfl.. 2 recurs - fault persists.

Technical Descriptions: Section 7.12.9.

fAUlT
ll. Over voltage circuit on the DC Assembly has detected the
excess voltage between PHi 1md lPl..o lii,es and has activated
HY ST to the CJPU, and
2. The CPU has recognized that the instrument is not in High
Voltage State, so has generated FA__Il.. 2 display, then
]. The CJPU has switched Output OFF, tripped the watchdog
and generated FAfl.. 5 display.

fAUlT
Injection of external voltage.
D.C Assembly (page
Power Amplifier Assembly 11.9-1 ).

Self-t,est procedwre: Section 2 .3.

Technical descriptioru;: Section 7.3 .7.

2-2
2.2.3 FAIL 3 (Control Data Corrupted) 2.2.4 FAIL 4 (Precision Divider Fault)

INITIAL ACTION INITIAL ACTION

No immediate action required. No immediate action required.

!FAULT FAULT CONDITION

1. Control data corrupted. ll.. Precision divider fault.
2. CPU has detected errors in serial transfer of data between 2. CPU has detected errors in the most-significant data bits set
out-guard and in-guard circuits, andgeneratedF AIL3 display, in the precision divider input data latches, and generated
then FAIL 4 display, then
3. The CPU has switched Output OFF, tripped the watchdog 3. The CPU has switched Output OFF, tripped the watchdog
and generated FAIL 5 display. and generated FAIL 5 display.

POSSIBLE FAULT LOCATIONS POSSIBLE FAULT LOCATION

Reference Divider Assembly (page 11.4-1 ). Analog Interface Assembly (page 11.3-1 ).
Analog Interface Assembly (page 11.3-1).
!FURTHER INFORMATION !N THIS HANDBOOK
FURTHER INFORMATION IN THIS IHANIDBOOK Technical descriptioi;: Section 65 .2 .3.
Technical descriptions: Section 6.4.

2-3
2.2.5 FAil 5 (Safety Circuits 'Watchdog'

Use the checking sequence below, watching the MODE display Digital Assembly (No gated WRT STRB pulses at J2/J3-29)
carefully at each stage to detect any FAIL number appearing (page 112-2).
immediately before FAIL 5. If no failure message occurs, carry
Analog Interface Assembly (No SSDA strobe pulses; or
on to the next stage.
Watchdog disabled) (page 11.3-3 ).
Stage 1: Press Reset
Reference Divider Assembly (Incorrect functioning of
Stage 2: Carry out self-test sequence (Section 2.3). Watchdog setup circuitry) (page 11.4-5 ).
Stage 3: Set Output ON. N .R The Watchdog is designed prinlarily to ensure that CPU
malfunctions do not set up dangerous conditions in the
Stage 4: Proceed with careful use.
analog circuitry.
If FAIL 2 occurs at stage 3, ensure that it is not due to injection
of an exessive external voltage by disconnecting the instrument
terminals and repeating the checks. J[f FAIL 5 alone occurs,
proceed to "Fault Condition" below. For any FAIL other d1an Technical description: Section 6.4.
FAIL 5, transfer to the diagnostic guide for that message.

18mS monostable (MlO in reference divider) has been rlP1~'"''"''

of at least two trigger pulses and has timed out,
"BARK" and "RL\RK DELAYED" (BARK
fro:m Ml3 in the reference divider

Summary of "Bit1~I(" effects:

1

JL Removes the drive from 't(8:ilSfor.;:ner"

2. Disables the 400V Powr:T

CPU starts controlled shut-dovvn.

of "BAH.K DETLAYED effects: 1

'

Disconrtects the
instruJ.nent output terminals.
2.
data conveite:rs.
3. fron1 control latches in th~0 refe.reTC1~e
disabled ii1to "Tdstatei., Eac:h
pull-up or
1-i.to a_ safe condition.

2-4
2.2.6 FAffl 6 (Calibration Memory Fault) 2.2.7 FAIL 7(P.A. 400V Power Failure)

INITiAl ACTION INmAL ACTION

l. Select Output OFF, Spee OFF, Error OFF. ll. Switch power OFF.
2. Perform self-test sequence (Section 2.3) or select Output ON 2. Check line supply is correct for input voltage setting.
at the requested value.
3. Switch power ON - no failure display - no further action.
3. No failure display - no further action.
4. FAIL 7 recurs - fault persists.
4. FAIL 6 recurs - recalibration required.
5. Select Cal (refer to Section 1 ). FAULT CONDITION
6. Recalibrate (refer to Section 1 ). Positive or Negative 400V power supply failure

7. Calibration failure - fault persists. Fault indication signal 400V(2) FAIL active
Check line input voltage
FAULT CONDITION
Calibration memory fault on Digital pcb assembly. POSSIBLE FAULT LOCATIONS
Power Amplifier Assembly (page 11.9-1 ).
POSSIBLE FAUlT LOCATION
Reference Divider Assembly (page 11.4-1).
Digital Assembly (page 11.2-3)
Positive Heatsink Assembly (page 11.13-1 ).

FURTHER INFORMATION ilNl THIS HANDBOOK Negative Heatsink Assembly (page 11.13-2).

Self-test procedures: -Section 2 3. Power Supply/Current Heatsink Assembly (page 11.13-3 ).

Calibration procedures: Section 1. Mother Board (page 11 .16-1).

Technical descriptions: Section 6.1. fURTIHIIEIR INFORMATION iN nus HANDBOOK

Technical descriptions: Sections 6.7.

2-5
 /FAUL 8 (P.A. 38V Power Failure) 2,:;ui; FAHIL 9 15V Power Failure)

m1mAL ACTION
1. Switch power OFF. JL Switch power OFF.
2. Check line supply is correct for input voltage setting. 2. Check line supply is correct for input voltage setting.
3. Switch power on - no failure display - no further action. 3. Switch power on - no failure display - no further action.
4. FAIL 8 recurs - fault persists. t:\. FAIL 9 recurs - fault persists.

IFAUlT CONDITION IFAllllT CONDITION

Positive or Negative 38V power supply failure. Positive or Negative 15V power supply failure. This is
indicated by a transitory Fail 9 followed by Fail 8.
Fault indication signal 38V(2) FAIL active.
Fault indication signal 15V(2) FAIL active.
Check line Lnput voltage.
Also 400V power supply is disabled.
It is possible for a misleading FAIL 8 message to occur,
caused by a logic supply failure, in particular-15 Volts. The Check line Lnput vohage.
FAIL 9 message will have been displayed momentarily.
Refer for fault location and fmther information to FAIL 9.

Power Amplifier Assembly (pageJl.9-1).

Reference Divider Assembly
Povver (page 11.11-1).

Mother Board Section 6.7.

Techniccl de,,cr:tpt,ons: Section 6.7,

2.2.10 ErrorE!F Frequency seiected but not

INITIAL ACTION
li External Frequency Lock ii; not required:
Ensure external frequency selection switch (S53) is set to
OFF.

ff External Frequency Lock reference is required:

1. Ensure reference frequency is available at Rear Panel
connector 153.
2. Ensure Rear Panel switch S53 is set to ON.

FAULT
The external reference signal detector has set 'EXT REF ST'
to Logic 0.

POSSIBLE IFAlJJlT
External circuit.
Interconnection Assembly (page
Mother Assembly (page 11.16-4).
Analog Interface Assembly 11.3-4 ).

Teclmical descriptions:
External Frequency Lock: Section 8.3.

2-7
2.2.11 Error OL (Voltage: Output current limit exceeded: or Current: Output compliance limit exceeded)

INITIAL ACTION FAULT CONDITION (IN AC RANGES)

If Voltage range selected: If ImV, IOmV, lOOmV or IV Range:
1. Set Output OFF (Automatic if 100 or 1oo0V range Sine Source Assembly overcurrent sense circuit (M49a/
selected). M49b)has detected a current in theAC 1V line of approximatly
25mA RMS or more, and has activated LIM ST signal to the
2. Disconnect external circuit.
CPU.
3. Set Output ON:
If no Error OL or FAIL message, check external If IOV range:
circuit for low resistance, drawing output current in 10V overload detector in the Power Amplifier Assembly has
excess ofspecification. Ensure Maximum Capacitive detected a current in the 1+ line of approximately 60mA RMS
Load constraints are not exceeded (refer to User's or more. In this condition a hardware limit comes into effect.
I-Iandbook, Section 63).
If Error OL recurs, internal fault persists. If High Voltage ranges (IOOV or IkV): Either
a. 1OOV Overloaddetector in the Power Amplifier Assembly
If Current range selected: has detected a load in excess of 120mA RMS on the 400V
1. Set Output OFF. power supply,

2. Short Output terminals 1+ to 1-. b. 1kV Current Overload detector (M8) in the Output
Control assembly has detected anexcessive output current,
3. Set Output ON: or
If no Error OL or FAIL message, check external c. lkOvervoltageDetectorintheOutputControlAssembly
circuit for high resistance, developing output voltage has detected a voltage on the PHI(V) line in excess of
in excess of compliance limit. 1440V RMS.
If Error OL recurs, internal fault persists. In these ranges the output is switched off automatically by the
CPU.

FAULT CONDITION (IN DC RANGES) If Current range selected:

If Low DC Voltage range (IOO~V -lOY): Overvoltage detector circuit has detected a terminal voltage
of 3V RMS or more and has activated LIM ST signal to the
DC Overcurrent Detector circuit (page 11.5-2) has detected
CPU. If 100mA or lA range selected, the CPU switched
a current in the PLO(DCV) line of approx 28mA or more, and
Output OFF.
has activated LIM ST signal to the CPU.

POSSIBLE FAULT LOCATIONS

If High Vqi~tage range (100V or 1000V): Either
External circuit.
a. DC Overcurrent Detector circuit (page 115-2) has
Sine Source Assembly (page 11.6-1).
detectttcl excessive current in the PLO(DCV) line and has
activatdd LIM DET signal to the CPU, or AC Assembly (page 11.7-1).
b. DC 1oo0V Over-Voltage detector (page 11.14-2) has DC Assembly (page 11.5-1).
detected an output voltage in excess of 1440V and has Power Amplifier Assembly (page 11.9-1).
activated LIM DET signal to the CPU.
Current/Ohms Assembly (page 11.8-1).
In either condition a. or b., MID in the power amplifier removes
the 16kHz drive from the input to the PA, and generates HI I ST
FURTHER INFORMATION IN THIS HANDBOOK
signal to the CPU; which responds by setting Output OFF, and
DC Reference voltage to zero. Technical descriptions:
Low DC Voltage ranges: Section 7.3 and 7.6.
If Current range selected:
Low AC Voltage ranges: Section 9.4.
Overvoltage detector circuit (M15 in Current/ohms Assembly)
has detected a terminal voltage of 4.4V or more and has 100 or 1000V ranges: Section 9.5.
a~tiv ated LIM ST signal to the CPU. If 100mA or 1A range Current ranges: Section 10.1.
selected, the CPU switched Output OFF and reduces DC
Reference voltage to zero.

2-8
2.3 SELF-TEST SEQUENCE

2.3.1 General INHIBIT TEST

The self-test sequence is perfonned in two stages:

Stage 1 is a fully automated test of safety monitoring and
high-voltage safety interlocks;
Stage 2 is a semi-automatic test of keyboard and display TEST SAFETY MONITOR
FAL
DISPlAY UNCHANGED

functions, which also responds to operator's key selections.

2.3.2 Stage 1 (Fig. 2.1)

Entry into Stage 1 is selected automatically whenever the TEST
key is pressed for the first time (the test is not allowed ifOUTPUT
ON, ERROR or SPEC are selected or when in remote control). I
}:/
Indication oftest mode is given by the LED in the TEST key being
RESET SAFETY MONITOR DISPlAY UNCHANGED
lit. The full sequence of Stage 1 must be completed before exit
from the test mode can be made. The tests perfonned in Stage 1
are as follows:
1. Safety Monitor Watchdog Test. In this, the safety monitor is
tripped causing the word 'SAFEtY' to appear in the Mode
display, the Reset LED flashes and the buzzer sounds
TEST CALIBRATtON MEMORY
continuously. It is necessary for the operator to reset the
safety monitor by pressing the Reset key, after which the
'SAFEtY' display is replaced by the 'running' message, and
the test sequence continues.
2. Calibration Memory Test. The contents of the non-volatile
calibration RAM are checked for validity. Failure results in DeTEST
the message 'FAIL 6' appearing on the Mode display. POWER TO 110V
IS DETECTOR SET?

3. High-voltage Protection. This test ensures that a voltage NO

f+------~
demand made to the power amplifier does not trip the
DeTEST
software voltage detector when immediately below the POWER TO 140V
IS DETECTOR SET?
detector threshold level, but when raised to a level above the
YES
detector threshold the detector is tripped.

Incorrect detect action is shown by the message 'FAIL 2' on the AC TEST
POWERT07SV
MODE display. No voltages appear at the output terminals IS DETECTOR SET?

NO
during this test.

Fail messages are updated as the test sequence progresses through "CTEST
the calibration memory and high-voltage tests. After completion POWER TO 120V
IS DETECTOR SET?
of the high-voltage test, the test mode ends and the Test LED is
cancelled. If faults were encountered the last FAIL message will
remain on the display replacing the running message. Fault
diagnosis can now be performed. If no faults are encountered
during Stage I, the message 'PASS' is displayed. The calibrator
can now be returned to normal operation, or Stage 2 of the self- DISPLAY LAST
~YFAULTS?
MESSAGE FAIL?
test sequence can be selected. YES

FIG. 2.1 SELF TEST SEQUENCE STAGE 1

2-9
:t3.3 2 (Fig. 2.2)
Stage 2 of the self-test sequence is entered when the 'Jfestt key is
pressed AFfER the completion of Stage 1 and :BEFORE any
other key.
The keyboard LED indicators arelitinasequence which proceeds
from left to right along the rows of keys, while the Te1,t LED
remains lit.
DISALLOW ST AGE 2.
TEST !<EY PRESSED? PERFORM KEY
The next tests in the sequence require operator participation in NO ;l> INSTRUCTION

order to check key functioning. Operation of the C, JFuiR

YES

and Zern keys is shown by a symbol on the display immediately

above or close to the appropriate key. Operation of FREQUENCY ST ART ST AGE 2
ENABLE TEST LED
RANGE, MODE, RANGE, FUNCTION and OUTPUT control
keys is shown by the appropriate key's LED. ]n these tests the
display or LED remains lit until another key is pressed.
TEST !<EY PRESSED?
YES
At any part of Stage 2, pressing the Test key will end the test and
cancel the Test LED.
VISUAL CHECI<
ALL LED'S
O.K?

TEST KEY PRESSED?

YES
NO'

,i,
\I
rnsPLAv 0 o
WAIT FOR USER RESPONSE

MA~JUAL CHECK
USER RESPONSE
VISU:\L CHECK
ANY l<EY PRESSED DISPLAY !'(EY FUNCTION

II TEST
t<EV PRESSED?
MO

L---------,---~\1/
-------v-:
EMO;;;-!
CP,NCEL TEST LED

2-10
 In addition to the electronic protection devices used in the ii,stru_rnent, fuses protect against catastrophic component failure.

A blown fuse is merely a symptom of failure, in the large majority The ultiniate causes of blown fuses are so extensive that it is
of cases the cause lies elsewhere. hnpractical to list them. In many cases t.he underlying cause, or
the blown fuse itself, will activate a., electronic protective process
C,B:,llJT!l{:;J~,B which cai, conceal some of the syrnptoms.
occurrence of a blown fuse should be Fault location in the Calibratm should proceed from the primary
the cause. Qy,Jy when satisfied that t.he cause is known, and has Lndi.cations of fault condition (e.g. failure messages described in
been removed, should a user replace a fused lin.1<:. by a serviceable Section 2 .2). These will lead to particulsr areas of investigation,
item. a..n.d atth.is poLnt the relevant circuit fuses should be checked first.
V\lhether fuses are blown or not, the checks will add to the
infonnation available for fu..11:her diagnosis.
The fuses in Lhe calibrator fall into two groups:
Table 2.1 (overleaf) lists fuse locations. TI1e table is indexed in
21. Clip-in anti-surge fuses in the Power Supplies 21.J.nd Mother Circuit Diagram. page order, giving fuse values. The types of
Board protect the power source from damage. fuses to be used can be fm.md in the component lists of Section 12.
b. Soldered-in. fuses are used in some locations to ensure that
the printed circuit tracks are protected in the unlikely event
of extreme failure conditions.

2-11
DC Assembly
F1 1A/Solder-in DC 10V, 100V & 1kV Error 11.5-1
F2 250mA/Solder-in SHl(DCV) 11.5-2
F3 i A/Solder-in Power Lo/Guard 11.5-2
F4 1A/Solder-in Power Lo 11.5-2
F5 1A/Solder-in DC 1kv 11.5-1
F6 1A/Solder-in PHl(V) 11.5-2

AC Assembly
F1 1A/Solder-in 1V range only & Current ranges up to 1OmA 11.7-1
F2 1A/Solder-in All AC Voltage ranges {PHl(ACV)) 11.7-1

:vn Assembly
F1 Not used
F2 375mA/Solder-in PLO(Ohms) 11.8-3
F3 1A/Solder-in SLO(Ohms) 11.8-3
F4 375mA/Solder-in PHl(Ohms) 11.8-3
F5 2.5A/Solder-in All Current/Ohms Outputs 11.8-1

Digital and Display supplies 11.10-1

Power Supply (iG)

F1 4A/Clip-in Supplies -22V(2) 11.11-1
F2 4A/Clip-in Supplies +22V(2) 11.11-1
F3 3.15A/Clip-in Supplies + 15V(2) 11.11-1
F4 3.15A/Clip-in Supplies -1 OV(2), -15V(2) 11.11-1
F5 1A/Clip-in Supplies -8V(2) 11.11-2
F6 1A/Clip-in Supplies +8V(2) 11.11-2

Power Supply (3SV)

F1 1A/Solder-in -38V Supply Line 11. 12-1
F2 1A/Solder-in +38V Supply Line 11.12-1

MoH1er BoanJ
F1 1A/Clip-in Transformer secondary to 400V PSU 11.16-5
F2 1A/Clip-in Transformer secondary to 400V PSU 11.16-5
F3 2.5A/Solder-in Transformer secondary to 38V PSU 11.16-5
F4 2.5A/Solder-in Transformer secondary to 38V PSU 11.16-5

Power input M@du!@

220/240V 3A/Clip-in All circuits 11.17-2
100/120V 6.25A/Clip-in All circuits 11.17-2
..,_,
llo

L,, TllJE fC0TVITIE1IB'Jlli:]}) llikEI'vR(f\J AIL (})JF TOP fo_JiD

JB O1f 1r OM C
A§§EMIBlUE§ AND JR'.lE/-UR:. lPA?{ElL h\,'0,'\,)<CIV

UNSUlP'JPOJR'.1fER THIT§ CAN ICOI'l§Tl[TllJTE A

§AlFJETYIT-lltZA~JRD TC]) B301rf~ lP'ElFt§Oic.;~1:cJE~t i±tl\IlQJ

1 and to 1,

A. 11 circuits are housed vviL.11-in a 'fhe 4802 i\trfOCAL S'ff\NDARD can be ll§ed as a ucne,.n-,uu
board assemblies, the eight major PCBs a ir1strun1ent, or fr :raay be rack monnted in a standard 19'' raclc
"Mother" PCB o,0,0~H"U"

Six The recessed Power

the Selector a:re contained in filter module at the centre of
the displays. the rear
'fhe Calibration Enable switch (with removable mid the
are mounted directly
and the cooling-air
inwlce filter.
The ini:al(e filter is retained a grille but is removable for
a.,
deaning. At the extreme left of the panel, extrnctorfan draws
cooling air through the filter a..11.d internal heat exchangers,
discharging to atmosphere.
The IBJEE 488 standard connector socket (J27) with instrument
address switch, the Calibration mterval Swhch and the external
frequency switch (S53) are all mounted on the Interconnection
PCJB assembly. 'This is fitted on spacers to the inside face of the
panel with external components protruding to the rear. Socket
J54 is provided to facilitate future expansion.

3-1
3.3 LOCATION AND ACCESS

3.3.1 External Construction

Rigid side extrusions, together with the front and rear panel The top cover locates into the side extrusions and is secured by
assemblies, form the basic chassis of the instrument. The side screws. The bottom cover is attached in the same way, and
extrusions have handles and rear spacers fitted for bench-top use, includes six domed feet. An operator's instruction card pulls
or are fitted with 'ears' and slides for rack mounting (see User's forward from below.
Handbook, Section2).

3.3.2 intemai Construction

The chassis is enclosed top and bottom by ground and guard The main printed circuit boards in the forward compartment fit
screens. The upper ground and guard screens allow most internal across the full width of the instrument chassis. They slide into
adjustments to be performed without removal. Locations of vertical slots cut into the moulded chassis, their PCB edge-
adjustable components, instructions and warnings are printed on connection fingers making electrical contacts with sockets
its upper surface. mounted on the Mother Assembly. Interleaved between the
The interior of the chassis is divided into two compartments. A assemblies are screening shields. These are also guided by slots,
and make similar electrical contact.
thermally-enclosed compartment occupies the forward half of
the chassis, and is used to house the low power, precision printed The Power Amplifier assembly PCB slots in behind the forward
circuit board assemblies. compartment across the full width. It connects to the Mother
PCB in the same way, but has additional discrete elec!rical
The rear compa__rtment contains high power components, is air-
cooled and further subdivided. One section is positioned across connections for the high power lines.
the intake airflow, housing the In-guard and Out-guard Power Each PCB is identified by the color of its ejector lever. The color
Supply assemblies and providing anchorage for the Mains (Line) name is coded at its correct location on the top of the internal
Transformer assembly. The other section houses three Heats ink moulded chassis (refer to Table 3 .1 ). Also, each assembly's edge
assemblies, provides anchorage for the LFTransformer assembly, connector is uniquely configured to prevent incorrect fitting.
High Voltage assembly and 38V Power Supply assembly.
The Front PCB assembly, carrying the display components,
Filtered air passes over the power mixes with air in the connects into the front end of the mother PCB outside the
rear comp.J.rl:ment, is drawn through the heatsink assemblies, and thermally-insulated compartment.
is finally expelled from the instrument by the ex!ractor fan.
Guard screens are provided against the outer walls of the power
supply sub-compartment and the heatsink compartment.
Interconnections between l:he Power Amplifier assembly, all
forward-compartment assemblies, and the Front assembly are
made via a Mother PCB. The latter fits across the bottom of the
forward compartment, extending at the front to the Front assembly
and at the rear to the 38V Power Supply. Four moulded stiffeners
keep the motherpcb rigid, also providing lateral locating slots for
printed circuit boards and guard screens.
3A GENERAL ACCESS

ENSURE THAT POWER lIS OJF!F, ][f, during

a procedure, sufficient access has been obtained then no
Heed the Gelllie1rn1Il Pirern1.diom, 3JU & 3,1.:t further dismantling is required.

3.4L41 TOP COVER

(page 11.18-1)

lRemovail
a. Remove the eight M4 x 12mm socket head countersunk Locate cover at rear first, then reverse the removal procedure.
screws from cover.
b. Remove cover by lifting at the front.

3.4.2 BOTTOM COVER

(page 11.18-1)

Removal
a. Invert the instrument. Locate cover at rear first, then reverse the removal procedure.
b. Remove the eight M4 x 12mm socket head countersunk
screws from cover.
c. Remove cover by lifting at the front.

3.4f.3 FRONT PANEL

(page 11.18-6)
Remove covers (paro.s 3 .4.1 o,nd 3 .4.2).
lRemovail FfiUmg
a. RemovethefourM4x6mmscrewsfromtheside-wallsofthe Reverse the removal procedure, referring to page 11.184.
front panel.
b. Ease thefrontpanel forwards anddisconnecttheribboncable
which connectsto the switch pc board and power switch.
c. Remove the Front Panel.

3-3
3.4.4 TOP GROUND/GUARD SHEET
(page 11.18-3)
Removal of the Top ground/guard shield involves breaking Datron' s calibration seal and renders manufacturer's calibration invalid.
Instrument cooling air-flow adversly affected. Internal temperature rise triggers Fail 1. Power OFF and allow to cool as required.
Remove the top cover(para. 3.4.1).

RemovaR lFiiUJ:ng
a. Refer to page 11.18-3 and remove: Reverse the removal procedure.
1. ten M4 x 8mm pozi-countersunk screws;
2. six M3 x 6mm pozi-pan screws and M3 shakeproof
washers;
3. one M3 x 12mm pozi-pan screw and M3 shakeproof
washer.
b. Remove the top ground/guard assembly.

3.4.5 BOTTOM GROUND SHEET

(page 11.18-2 detail 8)
Invert the instrument
Remove the bottom cover (para. 3.4.2).

RemovaR Fi.Hing
a. Refer to page 11.18-2 detail 8 and remove: Reverse the removal procedure.
ll. ten M4 x 8mm pozi-countersunk screws;
Z. six M3 x 6mm pozi-pan screws and M3 shak.eproof
washers;
b. Remove the bottom ground sheet assembly.

3.4.6 BOTTOM GUARD PLATE

(page 11.18-2 detail 7)
Invert the instrument. Remove the bottom cover (para. 3.4.2). Remove the bottom ground sheet assembly (para. 3.45).

Removal
:n. Refer to page 11.18-2 detail 7 and remove ten M3 x 6mm Reverse the removal procedure ensuring that no wiring is strained
pozi-countersunk screws. or trapped.
b. Remove the bottom guard plate.

3-4
3.5. REMOVAL AND FITTING

Nq_,te:
Do not remove the Top Ground/Guard sheet if only In addition to the following location instructions, refer to
selecting pre-cal, erasing cal memory, or removing the Reference Handbook page 11 .0-1.
Instruction Card or Rear PaneL

Instruction Card 11.18-1 3.5.1

Front Bezel and 3.4.5 11.18-6 3.5.2

Switch Assembly

Display Assembly 3.4.5 11.48-4 3.5.3

Digital BLK BLACK

Analog interface BRN BROWN
Reference Divider
Chassis
RED RED
Output Control ORG ORANGE 3.5.4
Sine Source 3.4.4 YEL YELLOW
Code
AC GRN GREEN
Current BLU BLUE
(OR Current link pcb) BLU BLUE

Common Guard and 3.4.4 11.18-2and11.18-3 3.5.5

Ground Screens

Power Amplifier 3.4.4 11.18-2 (4) VLT VIOLET 3.5.6

}
Power Supplies
Out-Guard 3.4.4 1 U 8-2 (1)
In-Guard ·1 ·1. 18-2 (2)
±38V 11.18-2 (5)

Heatsinks 3.4.4 11.18-2 (4)

High Voltage 3.4.4 11.18-2 (5)

Transformers
Mains (Line)
HF
LF
} 3.4.4
11.18-5 (9)
11.18-4 (6)
1 U 8-5 (10)
3.5.12
3.5.13
3.5.44

Mother Board 11.18-4(3)

interconnections 3.5.28 11.18-7(15)

Terminal Board 3.4.3 11.18-5 (8) 3.5.15

11.18-4 (6) 3.5.16

3-5
3.5.1 INSTRUCTION CARD
(page 11.18-3)
RemovaB
21, Pull the instruction card forward to its fullest extent. <c. Reverse the removal procedure.
b. Bow the card and release the rear lugs from the slots.

3.5.2 SWITCH PCB ASSEMBl Y

(page 11.18-6 detail 12)
Remove Front Panel (para. 3.45)

Removal Fitting
a. Remove the eighteen M3 x 6mm pozi-pan screws and wavy Reverse the removal procedure.
washers which secure the switch pcb assembly to the front
bezel.

3.5.3 DISPLAY ASSEMBLY

(page 11.18-4 detail 6)
Remove Front Panel (para. 3.45)

Removal Fitting
a. Remove the five M3 x 6mm pozi-pan screws and wavy Reverse the removal procedure. Ensure all mating connectors are
washers and the two M3 x 12mm pozi-pan scews and wavy full engaged and that the surfaces of displays are clean.
washers which secure the display assembly to the chassis
assembly.
b. Ease the lower edge of the display 21Ssembly PCB away from
the Mother PCB, to disengage the mating connectors.
c. Remove the assembly.

3.5.4 MAJOR PCB ASSEMBLIES

ENSURE THAT THE INSTRUMENT POWER IS OFF.

Removal FEUing
a. Identify the PCB assembly to be removed (see Table 3 .1) a. Identify the chassis location of the PCB assembly to be fitted
(See Table 3 .1 and page 11.0-1).
Note (operations b to d):
The I/Q's Link PCB has only one ejector. To remove, grip Note:
the top edge and pull gently while levering the ejector The single ejectoroftheI/O's Link PCB locates to the 'BLU'
upwards and outwards. identifier of the chassis.
lb. Place the thumb of each hand under the lip of the two ejectors ibJ. Ensure the ejectors are in the 'down' position.
on the PCB assembly to be removed.
c. Insert the PCB edges into the identified slots in the side walls
c. Gently lever the ejectors upwards and outwards to release the of the chassis.
edge connectors.
d. Allow the PCB to slide down to the Mother PCB, then press
d. Remove the assembly. home by gently pushing down on the ejectors.

3-6
 COMMON, GUARD! il.1f/1Ul GROUn'!D SCREENS
(page 11.18-2 and 11
The first screen (counting from_ front to back) is the Ground Screen a.,d has two ~F-_,,m·mo screws. Of the six remaining screens the
first five are aluminium, single screw and h1tercha.T1gable. The rearmost screen is steel and not interchangable. Each plate mates with
a miniature connector on the Mother PCB act1ac;er1t to the side wall of the chassis.

2-. Rernove a._11y assemblies to obtBin access. a. into the cor£ect slots in tl1e side ~Nalls of t_11e
correct orientation).
b. Undo securing screw(s).
ltl. Allow the plate to slide down to the Mother PCB, then gently
c. Grip the plate and lift out from the chassis.
press home.
<\:. Secure with a 3 x 6nun Pozi-screw and shakeproof washer
for the screen).

POWE!K A~1~PUFnE!Rl !~1SSFMi2ll Y

11.18-2 detail 4)
Do not pull on the col11J.ector v;hes. So:m_e resistance to movement will be felt from the of the connector bases.

Ensure that Bll wires and connectors are clear of the PCB area.
DiscoJLT!ect the five connectors from the as shovvn
onpagell.18-1 detai/4. [», 111rert the PCB edges into their,Pcn,er-i0rnP slots in the side
w:,Jls of tI1e chassis; component side faci_ng the re~_r of the
iristrumenL
,;:, Place the thumb of eachhai,d m1derthe lip of the
c. Allow the assembly to slide down to the Mother PCB taking
d. Gently lever the ejectors upwards &nd outwaxds to release the care not to trap sny wires.
connectors.
o1. Ensure the ejectors are in the 'down' position then press the
e. Remove the assembly. assembly home by down on the ejectors.
e. smd fit the five connectors JI to J5, as shown on page
11.18-1 detail 4.

3-7
3.5.7 OUT-GUARD POWER SUPPLY
(page 11.18-2 detail 1)
Do not pull on the connector wires. Some resistance to movement will be felt from the locking clips of the connector bases.

Removal Fitting
a. Disconnect Jl, J2 and J3 from the In-Guard Power Supply !il. Ensure that all wires and connectors areclearofthePCB area.
Assembly (page 11.18-2 detail 2).
b. Insert the PCB edges into theirrespective slots in the chassis
b. Disconnect the connectors J5 and Bl/32 from the PCB. sub-compartment.
c. Fold back the connectors and wires clear of the assembly. c. Allow the assembly to slide down to the miniature connectors
on the chassis, taking care not to trap any wires.
d. Grip the top edge of the PCB and lift gently from the chassis.
d. Fit the J3 connector to the assembly.
e. Remove the assembly.
e. Press the assembly home by gently pushing down on the top
edge of the PCB.
f. Fit Jl, J2 and J3 to the In-Guard Power Supply Assembly.

3.5.8 IN-GUARD POWER SUPPLY ASSEMBl V

(page 11.18-2 detail 2)
Do not pull on the connector wires. Some resistance to movement will be felt from the locking clips of the connector bases.
The Out-Guard Power Supplies components can obstruct the removal of the In-Guard Power Supply. Remove Out-Guard Power
Supply Assembly (para 3..5.7)

Remoivall lFi.Uilillg
:11. Disconnect the three connectors Jl, J2 and J3 from the PCB. a. Ensure all wires and connectors are dear of the PCB area.
b. Fold back the connectors and wires clear of the assembly. b. Insert the PCB edges into the respective slots in the chassis
sub-oompm:tment.
c. Grip the top edge of the PCB and lift gently from the chassis.
c. Allow the assembly to slide down to the miniature connectors
d. Remove the assembly.
on the chassis, taking care not to trap any wires.
(jj[_ Press the assembly home by gently pushing the top edge of
the PCB.
e. Fit the Out-Guard Power Supply (para. 3 5.7)
f. Identify and fit the three connectors Jl, J2 andJ3 as shown on
page 11.18-2 detail 2.

3.5.9! 38V POWER SUPPl Y

(page 11.18-2 detail 5)
Heed the General Precautions 3.1.

Removal • Fitting
a. Grip the edges of the pcb and pull the assembly vertically !ll. Locate the assembly into the guides
upwards. Some resistance will be felt from the edge connector.
lb. Apply downward pressure until the connector is felt to have
engaged.

3-8
 lrl!E,!l, TSIINI~ ~SSIE!\JDBU!ES
(page 11.18-2 detail 4)
Heed the W a_rnings and Cautions 3 .1.1 & 3 .1.2 . .AJlow heatsinks to cool before on the connector wires. 'When
disconnecting connectors, some resistai,ce to movement will be felt from the of the connector bases,
AJthough the heatsink assemblies aie discrete items, removal is simplified when np·n·0.,-mPr1 in the order:
l. '""''""u v,; Heatshik 2. Positive HeatsLnk assembly. 3" Power i Cunent Heatsink assembly.

a. Remove the six M3 x 12mm scre'ws frorn !1;. Disconnect 3.i: Lhe
11 Po~Ner t11nplifier rs,,M,HHn y
b. Remove the heatsLnk retaining plate. Bl, 119 Mother nbbc,uu,,v
J1 In-Guanl PSU Assembly
c. Disconnect cmmectors:
h. Remove the Power Supply / Cunent Heats ink assembly.
Jl at the N"EGATIVE HEATSII\11( ASSEIVIBLY
J2 at the POWER AIV!PUFIER ASSEMBLY
id!. Remove Negative Heatsink assembly.

e. Disconnect J3 at the Power PLmplifier ='"""'",u·'-'

Reverse
the PCB side of each heatsink to face inwards

lr1uGl1 V'IWJLu~GE &zSS!Euilll2lt V

11.18-2 detail 5)

2. Refer to page 11.18-2 detail 5. Reverse the removal pn)c,c0,1!1'e Refer to page 11.18-2 detail 5.
Lift the ~,,-,,,.-.. , as in the
Remove the CDJmections J2 and B.

31,5, ·i 2 u11WJ1i\JS (ULJ\IE} TIR\ANJSFOPiM!ER ~SSEMrsll V

(page 11.18-5 detail 9)

2. Disconnect the connectors from the transfo1mer at the !Ji, Tum the instrument to stand on its left side (on Left Hand
following assemblies:
J2 - fa-guard Power Supply PCB Assembly (facing c. Release the four M8 x 110mm bolts, washers and nylock
page 11.18-2 detail 2.) nuts.
J3 m-211:Ma Power Supply PCB Assembly (facing
Gli. Remove the M3 x llrnm oo,z1--co,un1er screw, M3 steel
page 11.18-2 detail 2.)
nut and shakeproof washer which secures the solder tag
JS - Out-guard Power Supply PCl3 Assembly (facing
terminals of four ground wires. Fold back the wire which is
page 11.18-2 detail 1.)
fitted to the rear panel assembly.
J6 - Interconnection Assembly (facing page 11.18-5
detail 8.) e. Remove the Mains (Line) Transformer assembly.
J3 l/32 - Out-guard Power Supply PC:B Assembly(facing
page 11.18-2 detail 1.)
J32 - Motlier PCB Assembly page 11.18-2
detail 3.)
!FnWllillg
J33 - Mother IPCJEI Assembly (facing page 11.18-2 Refer to page 11.18-5 detail 9; reverse the removal prcicei1ure.
detail 3.)

3-9
3o5o13 HF TRANSFORMER ASSEMBLY
(page 11.18-4 detail 6)

Removal • !FiUilillg
a. Remove four M3 x 8mm pozi-pan screws ( see Fig. 3 .1 ). Reverse the removal procedure referring to Fig. 3 .1.
b. Disconnect connectors at the following points:
J2 - High Voltage Assembly;
J5 - Power Amplifier Assembly.
c. Remove the HF transformer assembly.

3-10
 lF Tfllti,l\iSfORMEiRl tl1SSEMl8ll V
(page 11.18-5 detail 10)
Remove High Voltage Assembly ) and the HeatsinJ:0,

@. From the LF Transfor:rner; remove the four MS nuts

a_nd flat steel washers, Remove a paiir of the transformer
a. DiscoTu"'°J.ect connector J4 from 1:he Power ,-'-'"P''"''°' and J3 65nun screvvs closest to the rear pa_nel and the
from the Assembly (see 3.2).
transformer bolt
lb. Turn the instrument to stand on its right hand side (on R.H. <B Slide out the LF Tra_n.sformer.
extrusion).
c. Desolder J34 from the mother board and connections A, B, !FliUliIIBg
M, H, K, & L. Remove associated supporting clips.
Reverse the rernov al procedure. Refer to Fig. 3 .2 and page 11.18-
2 detail 10.

CAOP WUlE.S TO LE.NGlM AND

..,,s11:;:1P 4=""' oe.i::o.i& SOlDERlNG

LACING CORD S9000?

IN 3 P0Sl7!0N5
WHIH
- rt°AOM
l~ 7JJ: P1.AYl::

COO? PIN$ TMAT At::ll

TC AVO!tl
!JNC,C::I'.::
~'\M..Q.5.6. TD !NSULA'flON
c.A[}l..[:
\1\. . .E.>oR
.S071'"
3, ov~
~ ;
,3 OV\>

'f='' CUP 630004

S!·lA~-<~PROOF
\!JMHl:a 613.00S
QHP' ..-lDME.Sll/1::
GY.'.>2G5

:t2, POZ!PAM scaaw GIIDI~

GISOD7
CLIP

L.~. ffiAW S r:'013:MER

,-'\.S5l:M!1L1 4006S!

~
f J1 (M'J)<"' 'u'tJUw® ITJsstJJ~GJ.Qk!1mJ©JmJ
II lFVl(ASD1/ C@U@e D.!@ili1ee l:ii@m@

~ 2, 3
6
White
Blacl,
Pin L
J34-8
7 Brown J34.5
8 Red J34-G
g Orange J:34-4
10 Yellow J34.9
12 Blue J34-12
13 Violet J:34-13
14 Red/Gm J34.3
·15 White J34-10
16 Gresn J34-14
17 Redl81k J34-7
18 Grey J34-15
19 Red/While J34-2
20 Pink J34-1
21 Red/Blue J34-16
22 0mg/81k J34·11
213 Coax Center - Pin H
\ Screen - Pin K
2 u MS LA'"6& WA.SNEii'< 3·; White Pin M
Gi303'El
J 1-6 lo J 1-22 ar0 inside Heatshrink Sleave

3-11
3.5.15 TERMINAL PCB ASSEMBLY
(page 11.18-5 detail 8)
Remove Front panel (para 3 .4 .3 ).

Removal
a. Remove the four M3 x 6mm pozi-pan screws (page 11.18-4
lFitti.1111g
detail 8) Reverse the removal procedure.
b. The terminal board can be tipped down to facilii.atecomponent
access.

3.5.16 REAR PANEL ASSEMBLY

(page 11.18-4 detail 6)

Do not remove the rear panel assembly when Top and Bottom covers and Ground/Guard assemblies are removed. Perform the
following operations with Top and Bottom covers and Ground/Guard assemblies fitted, or with AT LEAST the Top OR Bottom
Ground Sheet assembly fitted.
This procedure provides access to rear panel-mounted components by releasing the Rear Panel assembly and moving it away from
the chassis to the extent allowed by internal wiring connections.

Removali IFiiUilll1g
a. Remove the six screws of the two rear spacers page 11.18-4 !ill. Press the Rear Panel assembly to the chassis while ensuring
detail 7. that:
b. Remove the two rear spacers. 1. The wires in I.he cut-out in the moulded internal
chassis;
c. Remove the four screws of the filter grill.
11. The ribbon cables fa in the recess in !he moulded internal
d. Remove the filter grille and filter.
chassis;
e. Remove the Pozi-pan screw revealed by the removal of the
m. All other wires are free and not trapped by the rear panel
filter and grill.
assembly.
F. Remove the four rear panel screws (page 11.18-4 detail 6)
ll». Fit sc:rews, filter, filter grille and rear spacers, reversing the
g. Looking at the rear, locate the upper right hand screw procedure.
securing the extractor fan. Above this screw, locate anM3 x
6mm Pozi-pan screw (screw fixing hole only shown on
diagram). Removal of the screw allows the rear panel to be
detached (see cut-away sketch above Rear Panel in detail 6
of page 11.18-4).
h. Gently pull the Rear Pmiel assembly away from the chassis
to the extent allowed by the wiring. Do not stress I.he wires.
 E

This section which removal of covers or

A· Routine
!Pt Internal CzJibration
C: Adjustment Following nv'"""'·""'

i
(or less in adverse conditions) t3.2

(a) Sect. 1.3

iilen
5 4.3 (b) Full rouiine User's Hand-

C®W!llwtmti©I']
L9'W©K;®cilm&

Routine SecU.4
4-wire & and
2-wire Q User's Hand-
book, Sect. 8

4-1
 Adjustments Following Replacement of PCBs
Prncechm! l"re-cal Routine cal
PCB Assembly Adju~tmants
(Secnon 4) (Sect. 1.3) (Sect 1.1)

Terminal Capacitive Load Test Full

4.6

Digital Full Full

Reference
Full Full
Divider

DC Capacitive Load Test 4.6 Full

Sine Source Full

Capacitive Load Test 4.6

AC Sense Amp zeros 4.10 Full

Quiescent Current 4.7 AIII ranges

Current/Ohms Compliance 4.8 AIII ranges
Assembly Resistance 4.4 Ohms

Power Amp 100V PA bias 4.5

Mother Common-mode null 4.9 Full Full

Out-guard Common-mode null 4.9

PSU Full

Heatsinks 100V PA bias 4.5

+ve & -ve

Power supply
Quiescent Current 4.7 All I ranges
Current Heatsinks

HF or LF
Transformer

Mains (line) Common-mode null 4.9

Transformer
a. Disconnect the in..st:rnment from any power source before
attempting to dismantle it (for dismantling and reassembly
h1structions consult Section 3).
b. If the top ground/guard assembly is removed, subsequent
testing with Power On should be completed in less than 5
minutes to avoid overheating. HAZARDOUS ElECTRiCAl POTEu'-!IT!AlS ARE
E}t'.IPOSED WHIEi\l THE INSTRUMENT COVERS
c. After servicing ensure that all connections have been made
correctly arid t_hat the top and bottom shields and covers have
ARE REMOVED.
been replaced. Leave assembled instrument powered-up for
at least 1 hour before carrying out any adjustment, ElECTRiC SHOCK CAN KilU
dl. Although replacement assemblies are set up by the
rnarmfacturer, tlie internal adjustments recomrnendedinTable
4.1 must be carried out to ensure correct operation. These
adjustments need to be carried out once the assembly is
installed in tlie user's instrument, in order to account for
interaction between assemblies.

AFTER Al'\TY MAINTENANCE OPERATIONS WHICH DAMAGE CAUSED BY UNAUTHORISED REPAIRS OR

INCLUDE REMOVAL OF TOP OR BOTTOM GROUND MODIFICATIONS CAN JNVALIDATE INSTRUMENT
ASSEMBLY, CARRY OUT THE FULL SELF-TEST W ARRAl""\JTY. CHECK THE W ARRAN'TY DETAILED IN
SEQUENCE (Section 2.3) BEFORE RETURNING TO THE "TER1'1S AND CONDITIONS OF SALE". H APPEARS
NORMAL USE. ON 'fHE INVOICE FOR YOUR INSTRUMENT.

(Datron Part No. 450277-1)

The filter should be deaned at intervals no greater than one yeaK. Exrunine Lhe fmim filter for wear, replacing if links are
In dusty conditions lthe frequency should be increased. broken.

21. Remove the four M3 x lOm,-n pozi-countersunk screws Place tli.e filter i,, t_he grille housing and secure the grille to the
which retain the filter grille. rear panel using the four M3 x 10mm pozi-countersunk
screws.
b, Remove the filter grille and reticulated foam filter.

21. Wash the foam filter in a dilute solution of household

detergent (hand hot).
Rinse thoroughly in clean hand-hot water and dry
completely, without using excessive heat.
b. Clean the grille, and tlie grille holes in the rear panel (use
a vacuum cleaner and soft brush on the rear
4,3 UTHIUM BATTERY REPLACEMENT O

(Datron Part No. 920101)

FIRST READ THESE NOTES! Caution

This procedure is to be performed at intervals of 5 years If the calibrator has been in use; allow to cool for 2 hours.
from new. From power ON (step f.) the internal temperature of the
instrument will begin to rise. Ensure the procedure is
Procedure 4.3.1 allows calibration memory to be retained completed within approximately 15 minutes; any Fail 1
during battery replacement. This requires the use of an message which occurs during this time period can be
Extender Card (Datron Part No. 400625) to give access safely ignored.
to the battery, and during its removal provide a supply to
the non-volatile RAMs. To ensure memory integrity the Precautions must be taken to prevent solder or other material
soldering iron used must be isolated from Mains (Line) falling into the calibrator.
ground by at least 50.kQ.
Ensure continuity of Mains (Line) supply while battery is
Procedure 4.3.3 resets the calibration memory to its disconnected.
nominal state (but does not require the use of an extender
card) during replacement of the battery. If this method is e. Select power ON. To reduce power dissipation ensure
used a Precalibration and full Routine Recalibration output remains OFF.
(Section 1.3 and 1.1) must follow before L'ie instrument
specification can be realized, as calibration data will Jf. Remove battery (refer to Fig. 4.1).
have been corrupted. In this case it is therefore
recommended that the battery be replaced immediately g. Fit and solder in a new battery. Select power OFF
prior to a scheduled full recalibration. (calibration maintained).

4.::t1 Procedure (Calibratiofnl Jbt. Refit the Digital Assembly into the chassis (Section] 5 .4).

Maintained)
a. Ensure that power OFF is selected.

b. Remove the top cover and top ground/guard assembly Follow the procedure 4.3.Jl ignoring steps (di.) and (e.)
(Section 3.4.1 and 3 .4.4).

c. Remove the Digital Assembly from the chassis (Section Use

35.4).
Refit the top ground/guard assembly into the chassis (Section
Do not place the assembly on my conducting surface or
3.4.4).
touch the gold edge connector.
Refit the top cover (Section 3 .4 .1 ).
d. Place extender card in digital assembly slot. NOTJE: Users who have followed procedure 4.3.2 must
Push Digital Assembly onto extender card. now carry out Pre-calibration :md full Routine Calibration in
accordance with Section 13 and 1.1 respectively.
 Battery
Battery
t Push sleeve back along the red wire to expose the
solder joint. Nega'dve Terminal

[L Unsolder the red wire from the positive terminal of

the battery.

m, Unsolder the negative terminal of the battery from

resistor R60 at the wrap-joint.

iv. Remove battery from battery clip

!FIG. t'do 11 BATTERY RIE!P!LACEMENT

4-5
4.4 OHMS FUNCTION= STANDARD RESISTOR ADJUSTMENT

4.4.4 Possible Damage

Routine adjustment of the standard resistors used in D. function A stressed rnsistor may have been damaged if its value is greater
is not required. A resistor is calibrated by the user entering its than 50ppm outside its tolerance. It is advisable to have such a
measured value into a non-volatile calibration memory. 'This resistor tested or replaced by Datron Service Center.
value is subsequently recalled and displayed to the user each time
the resistor is selected.
Reset lntemai Trimmers
Follow the procedure detailed in Section 1.4 to adjust the resistor
'Error Message value. If this is unsuccessful contact your Datron Service Center.
'Error 6' is displayed if the value entered by the user during
calibration is outside the resistor's tolerance - i.e outside the
calibration memory span. Under normal use the resistor drift will
be well within the tolerance, so 'Error 6' should only appear if the
user enters an erroneous value.

4.4.3 Undue Resistor Stress

If the resistor has been subjected to undue stress, it is possible that
its value may have changed slightly, and be outside its tolerance.
If it is less than approximately 50ppm outside tolerance an
internal trimmer can be adjusted, and the value can be calibrated.

BIAS CURRENT ADJUSTMENT= 1 PA

(Refer to Layout Drawing 480618 Page 11.9-1 and 480637 Page 11.13-1)

Adjustment of the lOOV/lkV amplifier bias voltages must be

carried out after fitting a replacement Power amplifier assembly
or Heatsink assembly. The following procedure ensures the 21. Set 4808 Power OFF to connect DVM as follows;
drain voltages of Q4 and Q2 are+ 120V and -120V respectivly. lbi. Power Amplifier Assembly
Connect DVM in DC function, Lo to V 2C (near Q20)
USE EXTREME CARE TH and Hi to Tab of Q4.
THE !FOLLOWING PROCEDURES.
WARNING
At Power ON (even with Output OFF) the heatsinks are
maintained at LETHAL VOLT AGES!
Digital voltmeter (any Datron Autocal voltmeter) Use insulated adjustment tool.

1:. Select Power ON .

d. Positive Heatsink Assembly - adjust R 10 for a reading
Remove top cover. of+ 120V (5V).
Remove top ground/Guard assembly.
Ensure 38V/400V selecto; is set to 400V. re. Power OFF, disconnect DVM.

Rei:um to Use
Refit top ground/guard shield and top cover.

4-6
 TEST
11.5-1)

The AC lkV current overload detector on the DC Assembly

monitors output currenL ERROR OL is displayed when output
current limit is exceeded.
After replacing the DC Assembly, Terminal assembly, AC
assembly, PA assembly, Positive or Negative HeatsinJcs, or the
HF transformers it is necessary to ensure the limit level is re-set
to account for a.i,y capacitance changes. The value ofR84 will lie
between 2k43Q and 3k65Q. R84 will be selected from the E96
(1 %) series.
a, Ensure 4808 Power OFF.

l:J, On DC board remove Link J, and make Link L. DC

a, Test Load (lkQ non-inductive resistor, capable of assembly must be fitted Ln chassis (not on extender card)
dissipating 20 Watts).

lb. Digital Voltmeter fitted with AC Volts Ranges (any ic, Monitor Link L wiLh respect to V 2B with scope set to 5V
per division.
Datron Autocal multimeter)
d, Connect Load resistor across the 4808 output terminals.

e. Connectthe DVM across the Load resistor and select AC

Top cover removed.
lkV range on DVM.
Remove top ground/guard assembly.
Ensure 38V/400V power supply selector set to 400V.
We Set 4808 Power ON.

g. On 4808 select AC lkV Range ~md adjust OUTPUT

for 90V on the OUTPUT display. Select lOkHz
range and set frequency to 4kHz. Set OUTPUT ON.

lm, Increment demanded voltage and check that 'Scope goes

to zero volts when the DVM indicated between l 08V and
112V. Select output OFF.

UEYHJ l

j, ][f outside limits set in (Im,) reselect R84 and repeat from
step (11,).

lk, When correct operation occurs solder in R84 break Link

L and replace Link J.

4.6.4 Retum to Use

Refit top ground/guard shield and top cover.
4o7 QUIESCENT CURRENT ADJUSTMENT= CURRENT/OHMS
ASSEMBLY or CURRENT ASSEMBLY
(Refer to Layout Drawing 480614 Page 11.8-1)

To allow a measurement of quiescent current in the power 4.7.3 Procedure

amplifier stage, its power supply lines are broken and a 0.1.Q
resistor inserted in series with each 22V supply line. The voltage a. Switch the 4808 Power OFF.
developed across either of these resistors gives a current
measurement. The quiescent current is set by adjustment of R23 ifl. Break the 22V supply connections to the Voltage-to-
on the Current/Ohms Assembly. Current converter power stage by removing connector J1
from the In-guard power supply pcb.

4.7.1 Test Equipment Required c. Re-make each 22V supply connection from its female
a. Digital Voltmeter (any Datron Aurocal voltmeter) pin on the freed J1 connector to its corresponding male
pin on the In-guard power supply pcb, using one O.lQ
b. Two2.5-wattresistors, O.lQ, 10%, wirewound(Welwyn resistor in series with each supply line (Red and Brown
W21 or equivalent) wires).

d. Connect the digital voltmeter across one of the 0.1.Q

4.7.2 Initial Conditions resistors fitted in step (c.).
Top cover removed.
e. Switch 4808 Power ON. Select AC Current, !Amp
Top ground/guard assembly removed.
Range, ensure OUTPUT OFF.

CAUTION
In the following step (f), use a thin insulated screwdriver.

f. Carefully adjust R23 on I/Q assembly for a digital

voltmeterreading oflOmV ±lmV (equivalent to lOOmA
through the 0.1.Q resistor).

g. Switch 4808 Power OFF.

Jbi. Disconnect and remove both O.H.1 resistors and the

digital voltmeter from Jl. Reconnect JI to the In-guard
Power Supply pcb pins.

Use
Refit top ground/guard assembly and top cover.
 (Refer to Layout Drawing 480614 Page 11.8-1)

Ernure that the Quiescent Current Adjuslment Procedure has

been completed (Section4]).
a. Connect the CU Q load resistor between the 4808 current
In the following procedure a DVM is used to measure output outputterminals (I+/I-).
current as a voltage developed across a load resistor. Series
resistance is then added to one of the power leads to establish a ll:;, lH!F' adjll!stme!Illt Select ACI, lA full range output at
compliance voltage. The change in current output due to SkHz. Select OUTPUT ON.
compliance is measured a.i,d an adjustment made to bring the
instrument within manufacturer's specification. c, With the DVM, measure the AC voltage across the load
and note the reading. Set OUTPUT OFF.
4J3.1 Test Equipment Requ!rred
d. Introduce the l AQ compliance resistor in series with the
a. Digital Multimeter fitted with AC Volts Ranges. (e.g. I+ lead. Set OUTPUT ON (fest should be done in less
Datron Irntruments model 1281). than 5 minutes to avoid overheating). Use the DVM to
measure the AC voltage across the 0. H1 load and note the
I,, Test leads, (each containing a 22.lQ resistor). reading.

c. One 25-watt load r-esistor ofO. lOQ, 10%, Wire Wound. e, Remove compliance resistor. If there is a change of
(Welwyn W21 or equivalent). reading> 10µ V between(c.) and(idl,) adjustRl Oto reduce
the change of reading to <lOµV. After each adjustment
dt A 1 AQ resistor to introduce compliance voltage. of RIO repeat (c.) to (e,).

ff, JLIF Adlj1m,tme!I!lt Complete above procedure, leaving the

4808 as selected (AC][, lA Full Range), but change
Remove top cover. frequency to 500Hz and limit to SµV.
Remove top ground/guard assembly.
g, ff change of reading in (di,) is >5µ.V adjust R3 L
Im, ][f an adjustment was made to R31 repeat complete
procedure from (1:J,) until no further adjustments are
reqll!ired,

j. Output OFF, disconnect load resistor.

Replace top ground/guard assembly and top cover.

4-9
 COMMON MODE NULL ADJUSTMENTS
(Refer to Diagram 400996 Page 11.10-1)

The procedure ensures that after replacement of Outguard Power Procedure

Supply, Mains (Line) transformer or Mother Assembly, any
power supply noise breakthrough on the Lo or Guard tenninals a. Set 4808 to AC lOV range with Output OFF.
is adjusted to a minimum. Resistor Rl2 on the Outguard Power
Supply Assembly (accessible through a hole in the top ground b. Er1sure that 1:he OUTPUT display is 0.000,00 V with
shield) is adjusted to minimize the voltage between Lo and local guard selected.
Ground. On the Mother Assembly (accessible through a hole in
the bottom ground shield) R25 is adjusted to minimize noise «:. Connect the oscilloscope AC input to the 4808 Guard
between Guard and Ground. terminal and the oscilloscope Ground to the 4808 Ground
terminal.

4.9.1 Test Equipment Required d. Locate Rl2 on the Outguard Power Supply assembly
Oscilloscope (with AC input and sensitivity to 100mV/div ). (accessible through the hole in the top ground/guard
assembly)

4.9.2 Initial Conditions e. Select OUTPUT ON and adjust the oscilloscope controls
to obtain the line related noise waveform.
Remove top and bottom.covers.
Ensure all guard/ground screws are correctly tightened.
if. Without touching the top ground/guard assembly, adjust
Rl2 for minimum waveform amplitude.

g. Select Remote Guard and obtain a noise waveform.

lhl. Locate R25 on the Mother pcb assembly through the hole
in the bottom ground/guard assembly

j. Wilhout touching the bottom ground assembly, adjust

R25 for minimum waveform amplitude.

Jk. Repeatprocedurefromstep (lti.) to step (j.)untilminimum

waveform amplitude is obtained.

t Select OUTPUT OFF. Disconnect the oscilloscope.

Return
0. Refit top cover.

bo Refit bottom cover.

4-10
4.10SENSE AMPLIFIER ZEROS
(Refer to Layout Drawing 400844 Facing Page 11 ]-1)

The sense amplifier, situated on the AC Assembly, is provided

with access holes located in the top ground/guard shield. In the
following procedure the reading and adjustments teps are al ways 21. Connect the DVM Hi to TP5 on the AC Assembly
taken with the48080UTPUTON and atone-tenthoftheselected (accessible via the hole in the upper guard shield).
Full Range value. Connect its Lo to the 4808 Lo terminal. On the DVM
select the DC lOV range wiih filter in.

OU Test Equipment IJJ. On the4808 select the AC 100V range, set lOV and lkHz
Digital voltmeter output. Select OUTPUT ON and adjust R 122 for a DVM
(e.g. Datron Instruments model 1281 or 1271). reading ofless than 200µV.

c. On the 4808 select the AC 1OV range, 1V output. Select

4.10.2 Initial Conditions OUTPUT ON.
Remove top cover only.
d. Note the DVM reading.

e. On the 4808 select the 1V range, 100mV output. Select

OUTPUT ON.

!fo Note the DVM reading.

g. AdjustR107 on the AC assembly to set both (d.) and (t)

readings to less thm 200µV.

h. Repeat procedure from (IJJ.) to (g.) until readings are correct

and the difference between all ranges is less than 400µ V
taking polarity into account.

j. Disconnect the DVM.

Retum Use
Refit top cover.

4-11
 PART2

TE HNICAL DESCRIPTI NS

SECTION 5 Principles

6 Digltaii; Coriltrn~ i.Wniuinr!!:l\11' S6Jlpplies.

SECT~ON 7 Voltage Outputs = Amplitude Control _.,"".-""'

8 Outputs = Frequency

SECTiON 9 AC Voltage Outputs = Amplitude Control System

SECTION 10 Current Outputs; Resistance

SECTION 5 PRINCIPLES OF OPERATION

DC Voltage
100µV-100V
Ranges

Isolation
Barrier

Out In
Guard Guard

DC Reference

Precision
Reference

Quasi-sinewave
"'"""""'""'""'""' AC Reference

Micro-
Sinewave
Synthesis
Processor
and Shaping Output
System Swttching

Remote
Inputs & Ou!puts """"""""""'""'ifl/JJ
Analog
Control

FIG. 5.1 4808 SIMPLIFIED BLOCK DIAGRAM

5-0
Figure5 .1 illustrates the general f-unctions and signal flow within For DC and AC amplitude control, an adjustable precision
the 4808. reference is derived from a pre-conditioned zener diode.
For AC outputs, the calibrator frequency is synthesized using a
crystal-controlled oscillator as a frequency reference.

The lDiatrn!l1l 4808 Autocal! Multilfu!Ilctfoi!iil §tmmdaird mainfrnme

contains just a microprocessor system and IEEE-488 interface. ft 11
To provide any useful functions, Option 10 and/or Option 20
must be installed as a minimum.
Figures 5 .2 (Digital, Control and References), 5 .3 (DC/Q) and
Option 10: DC Voltage function to ±200V. 5 .4 (AC) break the main functional divisions into smaller blocks.
Option 20: AC Voltage function to 200V. They can be thrown clear of the handbook to provide a functional
Option 30: Integral 1OOOV amplifier for AC Voltage and/or overview; they also form an index to other sections of Part 2.
DC Voltage functions. (Requires either Option
10, Option 20 or both.)
Option 40: Current converter to provide DC Cunent and AC
Current functions. (DC Current capability
requires Option 10, AC Current capability
requires Option 20.)
Option 50: Resistance function. (Requires Option 10 or
Option 20.)
Option 60: DC Current and/or AC Current rai,ge extension
to 1 lA. This option includes the Datron 4600
Transconductance Amplifier and all necessary
cabling. (Requires Option 40.)

The microprocessor accepts inputs from two main sources:

The front pmel keyboard provides local control inputs.
The IEEE 488 bus system provides remote control inputs.

The microprocessor system outputs digital information to five The frequency synthesizer and sinewave oscillator together
main areas: determine the frequency and purity of the AC outputsinewave
signal.
The front panel displays provide local outputs for monitoring
and control. Various decoders control function and range selection, internal
processes and status monitoring.
The IEEE 488 bus system provides remote outputs.
The precision reference generator produces an accurate DC
reference for output-amplitude control. Seru;ed DC outputs
are scaled and compared against the DC reference directly.
Sensed AC outputs are scaled and compared against a 'quasi-
sinewave' reference, whose peak value is set by the DC
reference.

5-1
5.4 PRECISION REFERENCE
(Fig. 5.2)

AMPLITUDE REFERENCE
The circuits produce a DC reference voltage which can be set d. For AC outputs, a negative version of the DC reference is
between OV and±20V for DC outputs, and between +0.126V and generated by inversion. Both positive and negative versions
+2.794V for AC outputs. The value of the reference is set by the are passed to the quasi-sinewave generator, which sets the
value on the left-hand OUTPUT display, modified in software by positive and negative inputs to a potential divider, whose
range scaling and calibration corrections. centre-tap is tied to reference common.
For DC, the range-scaled sense voltage is compared directly with The outputs from the divider are selected in ten equal time-
the reference - the resulting error controls the DC output value steps by digital logic, the ratios being selected so as to
directly. For AC outputs it determines the amplitude of the produce a periodic signal of quasi-sinusoidal form. The
'quasi-sinewave', a stepped waveform which is used as the AC Crest Factor of this signal (Peak value divided by RMS
amplitude reference. This operates in the error sensing loop, value) is 1.397, close to that for a pure sinewave. The RMS
having a shape whose crest factor closely approaches that of a ratio of sinewave to quasi-sinewave is stored during
true sinewave. calibration, and reapplied as a correction during normal use.
The circuitry is divided into four main areas: Because the amplitude of the quasi-sinew ave depends on the
value of the DC Reference voltage, its settling time to a stable
a. The period division comparator, outside guard, consists of a value is determined by the 7-pole DC reference filter.
binary counter and comparator, both effectively of 25 bits.
For accurate sine/quasi-sine RMS comparison, it is important
The counter is driven by a crystal-controlled clock; the
that both the quasi-sinewave steps and the comparator
comparator being set by latched data from the microprocessor
sequence are synchronized to zero-crossing points in the
system.
sensed output sinewave. This is ensured by:
When the binary count matches the data set in the latches, the
(a) including the divide-by-ten logic of the quasi-sinewave
comparator produces a switching pulse (reset). The counter
generator as part of the range-divider chain for the
fills to overflow point, at which the comparator produces a
frequency synthesizer,
second pulse (set). Thus accurate mark-period timing is
generated.
(b) feeding the quasi-sinewave frequency to the comparator
b. The switching integrator receives the pulses across guard.
to synchronize the ten-step sequence which controls the
They are used to drive solid-state divider switches, chopping
RMS comparison process.
the output from a very stable 20V DC Master Reference. The
resulting square wave is very accurately defined, both in
mark-period ratio and amplitude. Integration of the square REFERENCE
wave, by an active low-pass filter with high rejection at the
When the 4808 is operating in AC function, its internal frequency
chopping frequency, generates the DC Reference voltage.
reference is derived from the 13-bit counter in the Precision
c. For DC outputs, the selected output polarity controls a switch Reference out-guard circuitry. The counter is tapped at 16kHz,
which inverts the DC Reference for negative outputs. which is fed directly to the synthesizer to establish the frequency
of the VCO oscillation.
For users who wish to lock the output frequency of the 4808 to an
external frequency source, a phase-locked loop ensures that the
16kHz reference frequency phase is tied to that of the external
Reference Frequency. With correct frequency selection on the
front panel, this ensures that the 4808 output frequency locks to
the external reference frequency.
This function is performed in the External Reference Frequency
Buffer.

5-2
 l
(Fig. 5.2)

The analog circuitry is controlled by data held in a48-bit in-guard

latch. The microprocessor regularly updates the latch contents,
using the serial link to pass the data (through opto-isolators)
across the isolation bai"Tier. Certain analog status signals are
returned to the microprocessor, also using the serial lirol<.

E
(Fig. 53)

output resolution available is matched by the resolution of the

OUTPUT display.

On the l V and lOV ranges, the input from the Hi and Lo (sense)
The basic DC range of Lhe 4808 is lOV (19.999,999V FS). The terminals is applied to the error amplifier.
lOV range output is derived from a buffered 'Error' amplifier,
which compru-es lhe sensedouiput directly with the DC Reference. For the millivolt ranges and the 100µ V range, there is no remote
sensing. To complete the sense feedback, the 1V DC buffer
For the 1V range, the DC reference is attenuated 10: 1 before output is applied directly to the error runplifier, which is configured
being applied to the error amplifier. The error amplifier output as for the 1V ra.nge.
is buffered before being applied to the I+ and I- terminals.
For the 1GOmV range, the l V DC buffer output signal is reduced E
by a passive 10: 1 attenuator before passing to the Hi and Lo
terminals. The I-:- and X- terminals are not used. The lOV range signal is applied to the 100V power amplifier,
which drives the output terminals directly from the VMOS output
The lOOmV attenuator <1Jso serves the lOOp.V, lmV and lOmV
stage. The sensed signal is attenuated before being applied to the
ranges. Output values on these ranges are set purely by scaling
error amplifier.
the DC reference in software, and the consequent reduction in

E
(Fig. 5.4)

then phase-compared with the 8kHz reference. The integrated

output from the phase comparator controls the charge and
dischru-ge current of the capacitors in the VCO. Thus the VCO
To control AC outputs, the frequency synthesizer and quadrature frequency is adjusted to: n x 8kHz.
oscillator together generate a reference sinewave of stable The frequency range data is decoded and used to define division
amplitude and high purity. ratios in a series of frequency dividers, which act on the output
from the VCO. The result is the user-selected frequency, to an
5.7\1.1 accuracy of 1OOppm.
The user-demanded frequency is related to frequency range
selection, and is expressed as a binary number 'n' by the 5.1.1.2 SiIT'leWSIV® Sh~p!ng
microprocessor. It is passed into guard together with binary- The quadrature oscillator is approximately tuned to the user-
coded frequency-range data, to control the frequency of the selected frequency by the binary word 'n', together with the
synthesizer. decoded frequency range data, which combine to switch its
The binary counter in the reference divider is synchronized to the circuit constants. The oscillator output is applied to a second
4.096MHz master crystal-controlled clock. This counter oui:puts phase comparator, !lildreferred to the synthesizer frequency. The
a 16kHz frequency reference signal to the synthesizer, where it comparator output adjusts the oscillator frequency to that of the
is divided by two to 8kHz. synthesizer.
In the synthesizer, binary subdivisions of'n' switch the capacitors The quadrature oscillator feedback is conditioned to ensure that
of a voltage-controlled oscillator, adjusting its relaxation time- its unity loop gain and its 360° loop phaseshift occur together;
constant so as to cover five possible frequency bands within each only at a specific amplitude, md at the synthesized frequency.
frequency range. The VCO oul.put frequency is divided by 'n', The oscillator oul.put passes as reference sinewave to the VCA.
 E~CONTROllED AMPLIFIERS

The output from the quadrature oscillator is applied to two

cascaded voltage-controlled amplifiers. The gain of the second
The output sinewave is sensed and scaled to 1V levels before
of these (the 1Vbuffer) is adjusted in coarse steps; the gain of the
being applied to the comparator, which compares it with the
first being adjusted in response to the error between the scaled
reference quasi-sinewave to generate a DC signal whose value
output amplitude, and that of the quasi-sinew ave reference.
represents the output RMS error.
The settling curve of the 7-pole filter in the precision reference
In a strict sense, this circuit does not compare RMS values
divider is imposed on the 1V buffer slew rate, by using the filter's
directly. Instead, it compares the magnitudes of the mean-
DC reference output to control the coarse gain. This signal is
squares of its two inputs, but if these are equal, then the RMS
changed into a 10-bit word by an analog-to-digital converter,
values are equal. The error loop gain is virtually linear, due to the
whose digital output adjusts the input resistance of the 1V buffer
scaling applied to the error amplifier.
in steps of 1OOOppm of Full Scale. As the 1V buffer is part of the
error loop, this adjustment injects an undesirable scaling into the A cycling sequence is continuously imposed, each cycle having
loop. Therefore, to correct the loop gain, the same 10-bit word a duration of ten quasi-sinew ave periods. During the first cycle:
is used to apply inverse scaling to the error signal from the
si. the reference quasi-sinewave is first squared and integrated
comparator, before it reaches the first VCA.
as an analog DC signal (REF), which is memorized in a
sample-and-hold circuit;
5.7.3 LOW VOLTAGE~ 1mV TO 10V lh. the sensed sinewave input is squared, the (REF) value is
RANGES subtracted, and the result is integrated and memorized as the
DC (SIG) signal in a second sample-and-hold circuit;
ir. the DC (SIG) value is output as the mean-square AC error
On the 1V range, the output from the 1V buffer is passed to the signal.
JI+ and JI- terminals directly. On subsequent cycles, the (REF) value is also subtracted from the
For the IOV range, the lOV amplifier (a XlO amplifier on the squared quasi-sinewave, so that both (REF) and (SIG) signals
Power Amplifier assembly) is inserted between the 1V buffer and converge to steady states as the4808 output reaches the demanded
the JI+ and JI- terminals. voltage.

For the millivolt ranges, the 1V buffer output signal is reduced by The mean-square AC error signal is pru;sed through the scaled
switched, passive attenuators before being output via the Hi and error amplifier to control the VCA.
Lo terminals.
HIGH VOl TAGE 1 rn E
The high voltage loop uses much of the low voltage circuitry; the
On the 1V range, the input from the Hi and Lo (sense) terminals only differences being in the power amplification to the range
is applied to the non-inverting input to the 1V/lOV sense amplifier, voltages, and the attenuation of the sensed output down to 1V
which acts as a voltage follower. range levels.
For the 1OV range, the sense amplifier is configured as a divide-
by-ten inverter.
For the millivolt ranges, there is no remote sensing. To complete On the lOOVrange, the lOOV amplifier (on the Power Amplifier
the sense feedback, the 1V buffer output is input directly into the assembly) is included in the output path from the 1V buffer to the
sense amplifier, which is a configured as for the 1V range. K+ and JI- terminals.

The 1V/lOV sense amplifier is not used on the lOOV range.

Instead, a separate inverting sense amplifier reduces the sensed
sinewave by a ratio of 100: 1.

5-4
 1
1 O«:JJOV RANGE "1000\f E
(Fig. 53) (Fig. 5.4)

AnAC voltage-amplifier/rectifier system is employed to transform The output from the AC 1V Buffer is pre-amplified by the lkV
the DC Reference levels up to the high voltages required for the error amplifier, before being applied to the 100V power amplifier.
DC 1000V range. The lOOV amplifieroutput is transformed up 1: 6, then passed
to the][+ and][. ternC11L"'lals. 'The error amplifier receives feedback
The error voltage, which results from comparison between the from the transformer secondary.
scaled sense voltage and the DC Reference, controls Lhe amplitude
of a 16kHz AC signal output from a DC modulator. The To cover the full frequency range, two transformers with a
modulated signal drives the HF step-up transformer via the 100V frequency overlap are employed. The HF transformer is selected
AC Power Amplifier. A high voltage rectifier a.nd elliptical filter as frequency is increased above 3kHz, but the LF transformer is
convert the AC transformer output into the DC voltage output. used as frequency is reduced below 3.3kHz. A second feedback
Output polarity is determined by a changeover switch, inserted loop from the LF transformer primary only, eliminates any
between the rectifier and the filter. saturation of its magnetic circuit.

5J3.1.2
The sensed signal is reduced to DC Reference levels by an The amplifier used to sense the 1OOV range is also employed for
extensively-guarded precision attenuator, before being applied the 1000V range. Although the basic amplifier is common to
to the error amplifier. both, each range has its own input attenuator and feedback ratio.
On the 1000V range this ratio is 550:1, and software scales the
reference divider digital input to set the quasi-sinew ave to values
which at full scale are equivalent to 1100V RMS. The amplifier
output is compared to the quasi-sinew ave in the RMS comparator,
the resulting error signal controlling the output from the VCA.

OUTPUTS
1 IE
(Fig 53, 5.4)
The DC Reference is switched to drive a voltage-to-current IT the 4808 is fitted with Option 30 (the resistance and current
converter (this converter is the same current amplifier that is used option), then it has the capability of slave mode control over the
for the AC Current function). model 4600 Autocal 'frnru;conductance Amplifier, extending the
AC and DC Current functions to effectively include a 1OA range,
The various ranges are selected by digital control signals from the
controlled from the front panel or IElEE-488 interface of the
microprocessor system. The converter shunts are switched into
4808. An analog bus to the model 4600 carries the reference
the output circuit to scale the current.
voltages (either DC or AC) which the 4600 will 'convert' to an
omput current, while a digital bus carries status and control
signals between the 4600 and the 4808.
(Fig. 5.4)
The AC! Reference signal is obtained by activating either the AC
lOV range (used for the lmA, lOmA and lOOmA ranges), orthe
AC 1V range (lOOµA and lA ranges). 'This is switched to drive
a voltage-to-current converter, followed by a current runplifier.
Range selection is the same as for DC current output.

5-5
 10 RES~STANCE
(Fig. 53)

Eight fixed precision resistors, in a decade range (from lOQ to

lOOMQ) are switched to the output terminals. The resistors are
fully floating, being selected by relays under the control of digital
signals from the microprocessor system.

Precision components are used in all critic al locations. Individual

analog corrections for frequency-response, gain and offset errors
are not applied. Instead, the accumulated errors are measured
during calibration, and stored digitally in non-volatile memories.
In subsequent use, characteristic equations are applied to the
stored errors to generate software corrections, which are then
used to modify the reference dividerratios and so compensate for
the accumulated analog errors.

5-6
 to
Isolation Barner Frequency
to Synthesizer
I kV (DC)
ModL•lator

~I~
Ou, Gu,,:d I !11-Gudld
DC Mod vco Qua.2.i-Sinowave
Rei'erer.ce Frequency X 10
-- --i6kHz
Reference
F;cque11cy :=requcncy
Ex~0rna1 fercnce
R,-3fe1ence.:,:;.--.. - - _..-.. ---····-· .. _ ·-,·--······-· ··-··-· -----r 1ency (':.::1~(EJ--16kHz s-~-
lo Sequence Logic
of Rf\11S Com~,arato,
i=reauencv uf1er
(IG) -9r
t
I JL.1
__L,t_1
16~Hz
(INT)
Quasi-
Sinowavo
Generator
Reference
Ouasi-Sinewave
--- ----------,:>----
AC REFERENCE
to RMS Compsratc-
input selector switch

,---(-c~-SI ----
Sect.6.6
'REF+' 10 VCA lor coarse
----------------------·----0 qain trackinq

!t 1· Controlled
Ck;,ck
7-Pole
3osscl
Filter
AC

DCV
l Pulse
Reference
Io DC Err,.11

! Central I'"
Transformers
Polarity
Change
Voltane
Amplifier

I Processing I Input Data Divider -Over

Unit La1cl1es Switches to LJCJ

I DCI
Reference
Voltage-lo-Current
Converter

II ,_.._,_~:_=:::;--"'
Base-Level
RAM
!PRECISION REFERENCE
Voltage

It Non-Volatil
RAM
(Sect 6.5)

I +5',J , :'"i~ 1-36V

Program
Meciory
(
IEC:E488
Interface

I
DIGITAL
(Sect. 6.1)
5 +5V +SV Output
Control
Signals

Local
Control

Inputs

I AN4LOG CONTROL
I (Sect. 6.4)
+8V
+5\i '\;7 ,s -16v
I V
~ to Guard terminal

1808 Outc,uard an~ lnguard Power Supp/les are dercribed in Seciion 6. 7

i
SV - 19.SV -27 2V

5-7
 frorn
Precision Reference
25-bit Counter
(via op"io-isolator)
"'----------~-------~
DC Modulator
Re-r-er·ence Frequency
16kHz
\.-!=
100V
Amnlifier
t"'~"4,
LV
l
LV
IOOV,; 1kV
sanse Attenuator
Remct 0

!-,--,.:- . ·~AP"4, (DC\ 100V O @ ~ I I I F - - - - - - - - ~ s ~

02 • , 100V 0h
Unipolar DC,-,,,."'- E, ror (DC) l,.'
,'l "-=·-"'""" _,1·, ({_1Kv
E., · . •
Bulie' 1kV (X20'

1Polarizer
kV Ranqo 1
----ti
.'ff· kt.·
. ~ oov
~ - - - -(DC'
--- _ 1,r
.,,,,, 1001/ ~ 0 10V

Bipolar DC 27 . ,. i V

·kv 0

_, _ _ l100V __,,_,, _ _ , _ _ ,,

DC HIGH VOLTAGE
(Sect 7.7)
,..,...,.,.,.,.....,___...,___________________..,...,..,.,_?~,,~-ill!lffi",;"~}~~~.. .
ww
,.:;..!!illi!ili::-':s~~~~.:~..: . . , , ~ ~ , :

±15IV .a!v ±401ov

10VDC
X2 Buffo

1Volt DCErmr
Atten'Jator Amplit;er
oa:·!OV

from
Precision Reference
Polarity Changeover
Switch

)-
~i~-oo'J!f'
-
f: 10"'2 ::c
/,;
, ,0 "3,_,,
·--100rnV J

,--,,,-----·---------,, ____ _________

V
.. , _.

DC LOW VOLTAGE
(Sect. 7.2)

r
Il fil!ESISTAN(;E
{StE"•;;t. ,; 1.2t
~.,,,.,,.,,,,_,,,,._,,,,,'!Jiif,,.,,_,,,,n,,,,Jil
'V ±iSV

,·,,_,
5-9
 Voltage- Phase
L.
®
Controlled Comparator
.___.,,,....J,
Oscillator
I 1kVErirr
I Amplifier
vco
8i I I
+~P-10-
! 1kV 1
'

f 0--··-···
(,;:\
...
Reference
Frequency ( Ph;e
, Freq
Range
QUAD. OSCILLATOR
Freq n' Freq
Range
rJ,·--

1 stov' 1100v '--·--·-· I

I w
I 16kHz (IG) from
Comparator
(Sect. 8.2)
'
,.J
Reference Buffer 100V

I to
· Ouasi-Sinewave
Ouasi-Sinewave Frequency x 10

FREQUENCYSYNTHESIZER
±15V
'AC ERROR' I
1> I I Power
Amplifier
1kV 1kV t,

100V 100V 100V

. Control LO!liC (Sect.8.1) Signal
I.
I VCA <10V

I\
(DC Levels) 'REFc-'

l
(Sect 9.3)
to
Precision .,
I ±15V
I AC HIGH VOLTAGE POWER DELIVERY
(Sect9.5)
Divider
(Fig. 5.2) ±15V

from Quasi-Sinewave Frequency ±15V AOOV

I Quasi-Sinewave
Control Logic Comparator
Sequence Sample DC Reference

I lrom
Quasi-Sinewave Reference 'SIG'
~~·-·
§,,/
""-----"
,.,,,,~~·~·-,..

E~-{fr-.\~
Logic . . . .~,.,~.,.

·':,,.

6SIG' ln~~r;::~r
and
Hold
from
Precision Divider
10V
a,100V
o
ACV
, Generaior Quasi-Sinewave --·D- - Squarer - ·
I --+-:~---·--
C}.---··~- --o f
1, {!iJ ·1V-Rang~
L2vels
'REF' " !' DC l:~EF'_Jit1 Sample
and -~-o,.&-
mV
"b~ I
ACT

Sensecl-Ou1pu1
Sinewave Signal
I/'"
'Reference'
Hold
mv
integrator

m DC Ciicuitry

r for Output Switcl1inq

SINE/QUASI-SINE RMS COMPARATOR

{Sect.9.9)

illV ±15\/ \ 7Sig

v· Lo
!L j

ao1 OOV 1V/1 OV Sense

1V/mV
--------,---~--+!-,--'---~~~_ .._-10_'!.._..o_,•o,-···-----""""3···J_...........,Q........-
o
:e"iOOV
mV

mV
i Al'l

ACV r·· L~ -·~

Hi
I'
II
I
r~_,...,..____.___ . ~--'-···- ~-~-
ACI _!3,eference Current (from 1Vor 10V circuit, depending on Current ra.nge) Amplifier .
Lo J
I r\
\/
Sig
rocr Lo

I ACLOWVOLTAGELOOP
(Sect.9.4J

w
I
Sig
i ±15V ;,JBV

I
Lo

I
I ,--- I+ l
j... to Output Switching
I- J
1~
' t ·,
AC: Current Amplifier
(DC: Voltage-to-Current
Converter)
550:1, 1000V
Attenuator
1kV

l!CCURRENT
(Sect Ul1) AC NIGH VOLTAGE SENSING
(Sec,t!UJ)

±15\/

5-'1
The circuits described in this sub-section perform the following
functions:
Any key operation (other than the Reset or Di§]Plfa.y keys), or one
Central processing, with supporting memory, formanagement of two internal com:litions, will initiate an asynchronous interrupt
of instrument operation. (IRQ) which suspends Lhe CPU's current task. The CPU absorbs
Storage of calibration constants in non-volatile memory. the new instructions, rearranges its schedule to conform to the
demanded new configuration, then continues with the interrupted
Generation of Master clocks, with clock-waveform shaping. task until it is completed. Finally it returns to th initial operation
Address decoding to generate control signals. of the amended schedule and proceeds synchronously.

Controlled power-up and power-down of digital circuits. Three main sources of interrupt are used:

Servicing IRQs from asynchronous sources. Remote Command via the Digital Interface

Interfacing the instrument to the IEEE 488 bus. Keyboard Commai,d

The functions are performed by circuits located mainly on the Real-time Clock Pulses (8ms intervals)
Digital Assembly (480796). Master Clock generation, The CPU identifies the source by polling the data bus each time
synchronization and division is carried out by circuits on the it receives an IRQ interrupt.
Analog Interface Assembly (480648).
Fig. 6.1 shows the arrangement and main interconnections of the
central digital circuits.
From user inputs of output value, frequency, error and calibration
constants, the CPU computes a binary value to a resolution of 25
bits. This is used to adjust lhe mark/period ratio of the Reference
Divider switch which ultimately controls the Working Reference
The instrument is managed by a 6802-series microprocessor Voltage for the output analogue circuitry.
system, under the control of an operating program held in 52k
bytes ofEPROM. All front and rear panel controls provide direct
it,puts to the system, except for the Power ON/OIFJF switch and
!Reset key. The system ensures that the processor reverts to a s!lfe The vacuum fluorescent displays are continuously refreshed by
state on power-up and power down. cycling l:hrough character data stored in a separate display-image
RAM. To alter the display the processor merely alters the
Work space and stack is provided by 2k bytes of random-access
memory (RAM). A further Sk bytes of CMOS RAM act as anon- contents of the RAM.
volatile memory to hold c~Jibration constants, powered by a
back-up Lithium battery when the instrument is turned off.

The operating program manipulates the internal circuitry by

activating control signals, providing peripheral decoders with
specific address/data combinations. The program is run at a
680kHz cycle frequency, derived from the instrument's 4.096MHz
master crystal oscillator.

6-1
 ,,. .< ,..
" RIW
to
Model SSDI\
4!600

~
A
"' t:iigil,al
}?
lnlerlace
" V
(Sect 6.1.9)

"
---
IRQl/0
"'
V
IEEEill:lll
Digilal
lnterlaoo
(Sect 6.1.8)
r MEMCLK

R/W

I +r +7
KYBDIRQ RTCIRQ
J
A ' IRQ
Ssrvicing
Dig ilal Supply
Fail/Restart
I\..
Address
Decoding
• Control "/;
Control
Signals
.,
t>-...

V
,?)

" (Sect 6.1.2.6) (Sect 6.1.4) " (Sect 6.1.2)

...
i

Data Address
.A
Bus r,,_ C1amlml Bus
Processing !Jniil "
V V
" (Sect 6.1.8)
vMA 1
VMA
EXTAL E MR R/W j
MEM CLK
to SSDA
an<J
Keyboar~
,:::::/·.'· ""-'• MEMCLK =
.

i l< 1 >····._):
I·.· SYNC1 1.024 4.096 SYNC •••• J
MHz MHz
Addre~
Cll<'.l©k Wal!@lmm I\.. Decoding
Masler Clocl(9i
2.048
Sh"!'i"lll • Memouy
Geooralimi
(Sect 6.1.6) MH2 ~ (Sect 6.1.7) ' " (Seci6.1.2)
1..:
WSTR8

·.: Analog lfltertace >\si$ernbty .· • /

"
Prc>gram mid
Co1u11an1 Dal1't
oi!smOfY (El'ROl\ll)
(Sect/3. 1.2)
C ~, -
cs
,. , ~ WSTRB

@':I

~
Wolksp11©®
A I>.
m'id Sieck
Memoiy (RAM)
V
" (Sec/6.1.2)
cs

"
A
"
V
1>!011-1/'oieli~
Calil:m,1io11
Memory (RAM)
-A

7
(Sect 6.1.5) cs "
"
1
~-IJIRAl\/3 _Jv
+
Supply
C0mm1111110r
(Sect 6. 1.5.2)

!FIG. 6.1 DUGiTAL

6-2
6.1.2 CENTRAL PROCESSOR and PROCESSOR MEMORY
(Circuit Diagrams 430796 Pages 11.2-2/3)

A 6802 microprocessor (M34 ), together with its memory, controls With the external CALIBRATION switch set to RUN, NMI
communication throughout the whole instrument. initializes the processor system.

With the CALIBRATION switch set to ENABLE, NMI

6.1.2.1 Memory
clears the non-volatile calibration memory (M23) before
The memory can be split into four main areas, the microprocessor's initializing the processor system.
on-chip RAM not being used:
Progrn:m Memory (Ml8) - defines and controls the
operational functions of the whole instrument system.
Any one of three asynchronous Interrupt Request signals are able
Constant Data Memory (held in EPROM with the Program to activate the maskable IRQ input at M34-4:
Memory)- stores fixed factors used in processing; such as the
key mapping tables, and the instrument specification tables RTC IRQ is areal-time clock occuring every 8ms to provide
that are used in SPEC Mode. timing information for the processor's monitoring facility.

Non-Volatile Calibration Memory (M23) - stores all the KYBD IRQ occurs each time a front panel key is pressed.
calibration constants used to correct each output value, (Note: Not the Reset or Display keys).
which are determined during the 'Autocal' cycle. IRQ 10 occurs when theIEEE488 Interface has a transaction
to communicate to the processor.
Volatile Operating Memory (M22) - used for volatile data
storage such as computation results andpresentoutputvalue. Dl, D2 and Ql constitute a DTL OR-gate to isolate the IRQ
This memory is also used for scratch pad operatioru;. inputs. On receipt of Logic-0 on pin 4, M34 stores its register
contents in stack RAM, saving the current processor environment,
Separate memory is used for special purposes, such as the
and vectors to IRQ service addresses FFF8 and FFF9.
Display Image RAM M16 (which is synchronously loaded but
asynchronously read); the storage areas in the IEEE 488 GPIA The IRQ Service Routine addresses MS l and M52, setting
(M29) and the Keyboard Interface (U201 on Display Assembly); Logic-0 at M52-9 which enables the tristate buffers M36 and
and the Memory Address decoder PROM (M3). These are M37 (atM36-l and 15, M37-15). This sets IRQ data bits D 5 , D 6
described in later sub-sections. and D7 on the data bus so that the processor can identify the source
of the IRQ and select the appropriate sub-routine to service the
6.1.2.2 Central Processing Unit interrupt request.
(Circuit Diagram 430796 Page 11.2-2) The IRQ inputs are released as part of the service sub-routine, and
The MC6802 (M34) is a monolithic 8-bit microprocessor, with after its completion, the processor recovers its environment from
interrupt and clock-stretching facilities. It is driven by a single stack RAM and proceeds with the interrupted operation.
phase4.096MHz square wave generated by the Master ClockXl
in the Analogue Interface Assembly. (This clock synchronizes 6.1.2.1 Software Interrupt
the reference divider switch with the processor cycle). The 6802 will ru.so recognise Opcode 3F on the data bus as an
interrupt request ('Implied' addressing mode). This code is hard-
6.1.2.3 Address and Data Unes wired via R9, R 10 and AN3 onto the data bus so that if the CPU
Address lines A 15 _11 are decoded as chip-select signals for the tries to access a non-available address, the floating bus will be
RAM/ROM circuit, lines A 13_111 are connected to the iru;trument pulled to 3F, initiating the software interrupt. The CPU vectors
address bus. Data lines D7 _111 are linked to the instrument data bus. to FFF A and FFFB, whose contents cause the 6802 to re-initialize
the system.
6.1.2.4 E, MR and MEMCLK

The 4.096MHz clock input at M34-39 (EXTAL) is divided by

four and used as output at M34-37 (E). Although the natural The processor sets the R/W line to Logic-1 when it is in Read
frequency ofE is 1.024MHz, the action of the waveform shaping state, and Logic-0 when it has data to write into the addressed
input to M34-3 (MR) reduces it to approx. 680kHz as MEM CLK device.
when certain peripheral devices are accessed (IEEE 488 interface,
The R/W signal is passed only to the SSDA on the Analogue
Analogue Interface and Display assemblies).
Interface assembly, and to the IEEE 488 GPIA (M29). All other
devices which require read-write control, operate from the
6.1.2.5 NMI RD STRB and WRT STRB signals generated from R/W by
The internal switchS 1 provides anon-maskablehardwareinterrupt M49/50.
which has two functions.

6-3
 lnrtialize

Update
Run/Cal
Remote/Local control Status
selection is made via the !-----------------...
IEEE 488 bus Controller

Analog transfers are requested Remote Control? YES Disable Keyboard

at 40ms intervals, obtained by
counting Real Time Clock pulses. ~o

,------- Transfer Data to (and

Interrupts generated from Real Collect Fault-Status from)
Analog Transfer Required? YES
I Time Clock pulses (8ms) suspend
the cuffent CPU task so as to modify
NO
Analog Sub-system
the decrementing Delay Counters.
When the counters reach zero, the
CPU signals the relevant action. -~I
System faults are reported during Report Faults and
Any System Faults? YES actton as Required
the bi-directional analog transfer
NO

Delay expires when decrementing

counters reach zero. Counters are
Coniinue
activated as required by various Delay Expired? YES Delay Process
command processes, and run at
the rate of the Real Time Clock NO

Commands Translated from Action

Any Remote Commands? YES
Incoming Messages Remote Commands

NO
Remote Messages are inniated
by the Remote Controller

Translate Message to
Any Remote Messagss? YES Remote Commands
lnterrupls are generated JA,t,/ch
suspend the current CPU task. NO
The CPU stores the information in
buffers, acknowledges receipt,
then resumes the suspended task.
Action
Any Keyboard Commands? YES Keyboard Commands

Keyboard Commands are initiated NO

by pressing a Front Panel Key

Messages generated by command

processes for the remote controller are Set SRQ Status Byte
Service Request? YES
signalled by the Service Request (SRO) and Generate SRQ

FIG. 6.2 SOFTWARE OVERVIEW

6-4
6.1.3 SOFTWARE OVERVIEW When the +8V supply rises above about +7.lV, M28-3 voltage
rises above the +2.45V on M28-2, so M28-l rises to place a
The software management organization is shown in Figure 6.2. Logic-1 both on M8-5 (D input) and M7-l. M7-3 thus falls to
The machine cycle progresses through the task schedule as Logic-0, removing the resets from 14-bit counter M9 and restart
illustrated, being interrupted by the demands of activities flip-flop M8. So M8 is enabled to receive its clock from M9,
dependent on real time, and those dedicated to local and remote which itself starts to count its own 2.048MHz clocks.
commands. Real time and command interrupts suspend the
At full count, Sms after M9 is enabled, M9-3 clocks MS. As MS
current activity of the processor so that the immediate task can be
'D' input is already at Logic-1, this is clocked to M8-1 (Q), with
serviced. The processor then resumes the suspended task and
continues with the programmed routine, accounting for any Logic-0 to M8-2 ( Q). The PWR ON RST and PWR ON RST
alterations introduced by the interrupt. signals revert to their inactive states, and start-up proceeds:
2. PWR ON RS'f al: Logk-0:
6.1.4 DIGITAL SUPPLY: On the Display assembly, enables keyboard encoder U201
FAIL/RESTART CIRCUITRY and LED cathode driver decoder U203.

Power-up, restart and shut-down of the digital circuit...")' are b. PWR ON RST at Logic-1:
performed in a controlled sequence to safeguard against both
t Removes reset from CPU M34, allowing the software to
hardware and software failures. The Safety Monitor ('Watchdog'
initialize; and also removes the reset from the IEEE bus
-Section6.4.6)maintainsacontinuoussurveillanceofihesoftware
controller M29 (page 11.2-4).
management, and shuts down the instrument in the event of a
failure either in the digital control circuits or in software i.!. Removes the reset from the SSDA M44 on the Analog
management. Interface assembly.
ir::o MS-1 to Logic-1:
6.1,4, 1 Power-up Sequence
!, Provides an enabling input to Ml0-1
(Circuit Diagram 430796 Page 11.2-2)
(See Non-Volatile RAM - Section 6.1.5).
Power-on is first sensed by the Supply Fail Detector circuit. This
H, Triggers monostable M53-4. This monostable has a
draws its supplies frcim ihe +8V DC umegulated supply, which
relaxation period of 470ms, during which time it holds
is the first of the power supplies to rise to a working level. The
comparator circuit of M28 has a nominal threshold of + 7 .1 V, theFP RST outputatLogic-0. OntheReferenceDivider
above which a good working level of the +5V DC supply is assembly this allows the Watchdog circuits to reset.
assured. (See Section 6.4.6)
As the+8V supply rises, butstill below+7V,M28-2followsuntil m. Enables the 'Real-Time Clock' IRQ viaM7-13 and flip-
the Zener D6 avalanches, when it is held at +2.45V. At this level flop MS-10. The actions of M9 and MS interrupt the
M28-3 voltage is less than l V, so M28-l remains at OV holding software routine every Sms. 'RTC IRQ' sets five external
the 'D' input ofM8-5 at Logic-0 andM7-3 atLogic-1. Thus MS states onto lines D4 _0 of the Data bus (M36 andM37), and
and M9 are held in reset, initiating and maintaining the following forces the CPU to observe them.
states: Address decoder M51-5 is normally held at Logic-1, so
a, M8-2 ( Q) at Logic-1, PWR ON RST active. This signal is the Logic-1 at M7-ll and M8-10 allows M9-3 clock to
affect the RTC IRQ output at M8-13. For so long as the
fed to the Display assembly, holding the keyboard encoder
U201 in reset, and disabling the LED cathode driver decoder +8V supply holds above +7.lV, M9 continues cycling
U203. through its full count, clocking M8-11 to initiate the RTC
IRQ at 8ms intervals.
b, M6-4 at Logic-0, PWR ON RST active. This signal holds
The CPU terminates each RTC IRQ service sub-routine
the microprocessor M34 in reset state. The VMA output at
by addressing M51, pulsing M51-5 (M7-12) to Logic-0
M34-5 is held at Logic-0, disabling address decoder M3,
(Real-time clock reset 'RTC RST). M7-ll and M8-10
setting all M3 address outputs to Logic-1.
are pulsed to Logic-1, resetting M8-13 (RTC IRQ) to
c. The Logic-0 of PWR ON RST also holds the IEEE 488 Logic-0. At the next full count of M9; M8-13 is once
GPIA M29 (page 11.2-4) in reset. It is also fed to the Analog again clocked to Logic-1, initiating another RTC IRQ.
Interface assembly where it holds the SSDA M44 in reset. Pulses from M9-3 regularly clock the binary state of MS-5
through to MS-1, monitoring the supply status. When rurming
nonnally,MS-5 andMS-1 are boih atLogic-1. If the supply fails,
M8-5 reverts to Logic-0, but M7-l at Logic-0 provides a fast
reset setting M8-4 to Logic-1 without waiting for the next clock
pulse. M7-3 also resets the 8ms counter to zero count atM9-11.

6-5
6.1 .4.2 CPU Re~start
(Circuit Diagram430796 page 112-2)
Memory addressing by the CPU is monitored by logic in
programmable logic array M3.

In a valid addressing sequence the CPU control and address

decode signals are:-
VMA (M34-5) = Logic-1
E (M34-37) = Logic-1
and
one M3 output (M3-13, -14, -16, -17 or -18) = Logic-0
For an incorrect addressing sequence the CPU control and address
decode signals would be:

VMA (M34-5) = Logic-1

E (M34-37) = Logic-1
and
all M3 outputs (M3-13, -14, -16, -17 or -18) = Logic-1
This situation indicates that· the CPU is attempting to access
memory locations which do not exist in the 4808, and is most
likely the result of a software failure. This condition is detected
by the logic inM3,resulting inM3-19 (INV ADDR_L) being set
to a Logic-0. Via M7-2, this sets M7-3 to a Logic-1 which:-
Resets counter M9 to zero and flip-flop MS (M8-4)
Forces M8-1 to Logic-0. This forces M7-ll to a Logic-1,
resetting MS (M8-10) and removing an enable fromMl0-1.
(See Non-Volatile RAM Section 6.15)
Forces M8-2 to Logic-1. This change:
Resets the CPU by M34-40 to Logic-0. VMA is forced to
Logic-0 which in tum causes M3-19 to go to a Logic-1,
removing the reset from M9-1 land M84.

Makes PWR ON RS1' and PWR ON RS1' signals active, thus

resetting the other software-controlled areas.
After 8ms from CPU reset, flip-flop M8-3 is triggered from clock
M9. M8-l and M8-2 change state and the start-up sequence
proceeds again.

6-6
6.1.5 NONeVOLATILE RAM

6.1.5.1 'NV INHIBIT' Signals S. il o5.2 Supply Commutator

(Circuit Diagram 430796 pages 11.2-213) (Circuit Diagram 430796 page 11.2-3)
Chip-select to the non-volatile memory M23 is inhibited during This circuit provides the non-volatile RAM M23 with a battery-
power-up, re-start and power-down operations, by the logic driven standby supply when the instrument is in the power-down
signal NV INHIBIT being set to Logic-0. During normal condition. It also ensures continuity of supply during the change-
over period between normal (line) operation and standby,
running this signal reverts to Logic-I. With the NV INHIBIT
:minimizing battery current leakage.
signal at Logic-1 (M 10-4) during normal running; write access to
the NV RAM is available, but only enabled if the calibration ][n the power-down condition, the battery powers Ml O and M23,
security keyswitch on the rear panel is set to ENABLE. The returning from battery common (f Pl3) via D7 and R60. The
NAND logic gates MlO, used to control the inhibit, remain battery common is isolated from the general common 5A by
powered from the RAM standby supply after power-down. transistor Q2, which is cut-off.
Conditions for normal running are as follows: During power-up, M28 is powered from the +8V supply before
the +5V supply voltage becomes established. As long as the +5V
Supply fail detector circuit provides a Logic-1 (supplies
supply voltage is less than the battery voltage, Q3-4 is biased
valid) output to opto-coupler Ml 1. This action causes its
negatively, and Q3 is unbalanced in favour of heavy conduction
optically-coupled transistor to conduct and hold Ml0-2 at
through Q3-6. M28-5 is held low, and M28-6 high as the +SV
Logic-1.
supply voltage increases, so M28- 7 remains at Common-SA
Ml0-8 is held at Logic-1 (to +SV via R6). potential, and opto-coupler M39 is not energized. Q2 stays off,
maintaining isolation of the battery supply from Common-SB.
Ml0-1 is held at Logic-1 by flop 11/!8-1.
MlO andM23 remain from the battery.
The above conditions ensure a outputfromMl0-10, the
fu;, the +SV supply voltage irtcrcases, D7 cathode potential rises,
NV JNHIBIT signal. reducing Q3-4 bias, reaching zcrn when the supply voltage is
Dming power-up, NV INHIBIT i5 held act.ive until the power equal w the battery voltage (less tfoffi J. Orn Vis developed across
supplies have settled ruid the CPU h2JS gained control of memory; R60) .

The input to Ml0-8 is delayed on the +SV supply by the time- When the +SV supply voltage exceeds the battery voltage, Q3
constant C8, R6. Also, the input to Ml 0-1 is held at Logic- becomes biased in favour of heavy conduction through Q3-2,
0 by flip-flop M8-l until the CPU reset is removed. pulling M28-6 low and reversing the differential input to M28.
M28-7 rises to the +8V rnil and energizes the opto-coupler M39,
At power-down, or in the event of a supply failure, NV INHIBIT which switches Q2 on, connecting common-SA to the battery
becomes active before +5V supply fails: wrn.nmn. · Ml O and M23 arc now from the +5V supply
The first indication of supply fajJurc is made by supply fail and the standby battery is isolated by reverse-biased diode D7.
detector M28 output going to This cuts offtheoptu- power down, Q3 compares the +5V supply against the
cuuplcr Ml 1 which takes Ml 0-2 lo Logic-0. Ml0-8/12/13 battery., switching Q2 off via M28 andM39 when the +5V supply
are held at Logic-1 by the +5V supply, thus Ml0-9 is taken voltage falls below the voltage, and the non-volatile
to Logic-I and Ml0-10 to Logic-0 ( NV INHIBIT active). RAM supply commutates to standby battery. Alternatively, Q2
is switched off by failure of the +8V supply to M28 if this occurs
In the event of a CPU reset, the NV INHIBIT is made active for before the +SY supply voltage falls below the battery voltage.
the period of reset by the switching action of M8-1 and Ml0-9.
Eventually the +5V and +8V supplies both fall to zero, the battery
provides the supply to the non-volatile RAM, and battery common
is isolated from Common-SA by Q2.

6-7
6.1J5 MASTER CLOCK GENERATION
(Circuit Diagram 430648 page 11.3-3)
(Refer to Fig. 6.3 for waveforms) The CPU (M34) divides the EXTAL input internally by 4 and
outputs the result as E (Enable) at M34-37, to act as a 'Phase 2'
Memory Clock for the SSDA on the Analog Interface and the
keyboard controller on the Display assembly.
If M34-3 (MR-Memory Ready) was permanently held at +5V,
4.096 MHz
(TP7) the E signal would be 1.024MHz. But in the 4808, a 'stretching'
circuit (M35/l\149) doubles the Logic High (+5V) time of Eby

J
switching MR to Logic Low (OV) for part of the cycle. This is
2.048 MHz
(TP20)
L shown on Fig.6.4.
The frequency of E is thus reduced to approximately 680kHz,
with lµs available for data access to the SSDA, Keyboard

'L
1.024 MHz Controller, IEEE GPIA and memory.
(TP9)

6.1.7.1 Memory Clock Stretching Circuit

1.024 MHz
(Fig. 6.4)
(M41-10) The action of M35 and M49 is dependent upon the finite
propagation time between clocks atM35-l/l\135-6 and Q output

Jl 1L atM35-15. WhenM34-3 (MR) is+5V;M34-37 (E)is toggled by

SYNC 1
(TP11)

~ ~30to80ns
n Logic Levels: High~ 2.4V
Low -s:: o.av
alternate positive-going edges of the 4.096MHz clock, with a
propagation delay of approximately 80ns. Also, the 4.096MHz
signal is divided by 2 in M41, resulting in 2.048MHz signal
whose negative-going edges clock M35. M35 cascade action is
FIG. 6.3 MASTER CLOCK WAVEFORMS controlled by the condition of the Memory Clock (E) and affected
by its own propagation times.

The master clock generator is based on crystal oscillator XI 6:ll.1.2 Shaping Act!Oi'B
which provides a precision 4.096MHz squarewave reference
(Figs. 6.4 and 6.5)
frequency output.
At 1[']_ a!flidi '1['2: The 4.096MHz clock edge at Tl causes E to rise
The primary frequency of 4.096MHz is divided by JK flip flop from low to high at T2. As M35-10 is also high, MR changes from
stages M41, both of which are connected to toggle when clocked.
high to low at T2, holding E high. M35 pin state is 4 and 10 high,
The first division stage is synchronized at its reset input, M41-3,
9, 12 and 16 low.
to the memory clock via flip-flop M42. This ensures correct
phasing of the 2.048MHz squarewave output from M41-14. At ']['3: The 2.048MHz falling edge clocks M35, and M35-9
rises to high awaiting the next clock edge (not until T5). M35-10
M41-l 1 andM41-10outputs provide complementary 1.024MHz also remains high, so MR is held low and E stays high.
and 1.024MHz squarewaves respectively. Monostable M40,
which is triggered at 2.048MHz from M41-15, provides the At T4: MR is still low, so the 4.096MHz clock has no effect on
positive-going 2.048MHz synchronizing pulses, SYNCl. E, and E is stretched.
At 11'5: MR returns to high when the Logic-1 on M35-9 is
6.1 CLOCK WAVEFORM clocked as a Logic-0 to M49-4. This allows the 6802 to toggle
E at the next effective clock edge.
GENERATION
(Circuit Diagrams 430796 page 11.2-2 and At '1['6: The rising edge of the 4.096MHz clock causes E to fall
430648 page 11.3-3) to low, setting up M35-4 to low, M35-12 and 16 to high. (M35-
9 is already high.)
NB: As the circuit locations in Fig 6.4 are clearly marked,
and as there are no duplicate designators in the circuits, At 1'7: M35-I0is toggled to high, butasM49-5 isnowlow,MR
this description does not refer to a component's location remains high to allow E to be toggled at the next effective
except where necessary. processor clock edge (not until the nextTl). Also atT7, M35-15
is clocked to low to set M35-9 ready for the next (T3) clock edge.
NOTE: To avoid confusion, the terms 'high' and 'low' are used The circuit is now set up to its initial (pre-Tl) condition so the
to replace 'Logic-1' and 'Logic-0' respectively in the action repeats.
following description.
Note: A remote possibility exists, that a severe disturbance could
The crystal oscillator on the Analog Interface Assembly provides upset the synchronization of the 'E' signal with the 2.048MHz
a4.096MHzMasterClocksignal(Xl-8)forthewholeinstrument. clock. To guard against this, M42 acts as a monostable to provide
This drives the 6802 CPU at M34-39 (EXTAL) -M34-38 not negative reset pulses into M41-3. Under all normal conditions,
being connected. M4 l divides 4.096MHz to generate a2.048MHz these will occur when M41 is already toggled in its reset state.
clock for the Memory Clock Stretching Circuit (M35/l\149).

6-8
 +5V +SV
2
Aoolcg
• J

1
l\'M1 """"""'
"""""
CIK

16
I<
A

""" "" +SI!

39 E!ZW

--
2
s NC 38 ~id
• J S 01-'-5_ _ _..... ,
a a~c
M42 M:15 M3<1
1 C!k aoo• 5002
CR< CII<

a• NC °"'""
..sv
"3

nn TI
I I I

ll.lEM. CUC (E)

M:!5-4, ~~l!lll-4

MEflll.CUC(E)
M3S.~6 & ~2

For all waveforms: logic-0 = OV;

loglc-1 ~ +5 V

FIG. 6.5 CLOCK SHAPING WAVEFORMS

6-9
 IEEE 488 DIGITAL INTERFACE o9 MODEL 4600 DIGITAL
(Circuit Diagram 430796 Page 11.2-4) INTERFACE
The IEEE Interface circuitry is located on the bottom right-hand (Circuit Diagram 430796 Page 112-3)
comer of the Digital PCB (viewed from the front of the instrument). The processor communicates with the external Datron 4600
M29, M40, M47 and M48 execute and decode interface functions, Transconductance Amplifier using 9 signals in the digital bus,
and transfer data input/output. Eight signals are controlled by the processor using the PIA M26,
The General Purpose Interface Adaptor (GPIA) M29, is software- which drives the digital bus via the bus buffer M25. The signal
driven by the 6802 CPU, as part of its normal function, M29 is IDIGBUSON is driven from +5V ( circuit diagram 430604 page
addressed at CS by XIOBBD from MS 1, and its internal registers 11.16-4) so that the model 4600 may detect that the 4808 is turned
are accessed by A 0 , and A--i from the address bus, on.

The GPIA is clocked by Memory Clock E, with read or write The data on the digital bus IADO to IAD4 is bi-directional so
control direct from the processor R/W signal at M29-5; and at model 4600 control data can be written from the model 4808, and
instrument power-on, the signal PWR ON RST from the Restart status information read back. Writing occurs when signal IWR
Generator circuit (M6-4) initializes M29 at M29-19. pulses low and reading occurs when the signal IRD pulses low.
Information is passed betweenM29 and the CPU (M34), via the When IA/D is low, they are in data mode as described, when
data bus D 0 -Dr The address switch data is linked to D 0 -D 6 by high, they are in address mode, The address mode is used during
tristate buffers M47. During initialization and at subsequent a write or read to determine which address is to be written or read.
intervals, the state of M29-4 (ASE) changes from +5V to OV, The 4600 latches the address on lines IADO to IAD4 when WD
enablingM47. The status of the address switchesonthe4808 rear is high and IWR pulses low, All subsequent writes and reads are
panel is transferred into M29 via M47 and the data bus for to this address until another address is latched, The 4600 uses
comparison with the received address. only addresses 0, 1,2 and 3, The remaining addresses 4 to 31 are
M40 and M48 are bidirectional bus-driver arrays, The drivers for reserved for future expansion,
busmanagementlines: IFC, ATN and REN areperrnanentlyheld The processor reads the 4600 status registers each 40ms to check
in Receive state, and the SRQ driver in Transmit state, The EOJ[ for malfunctions, that the analog bus is connected, and the status
line driver is switched from Receive to Transmit by M29-28 of the on/off keys. The digital bus is reset by driving both IWR
(T/Rl) changing from OV to +5V as required by M29. M29-27 and IRD low, either by the processor or M24 (ie BARK DEL
(T/R2) is normally held at OV for reception of system data via (OG) is set),
DI0 1~6 bus lines, andsetto +5V for instrument data to be sent over
the bus.
Some system controllers output excessive noise along the REN
line. To avoid spurious switching of M29 between Local and
Remote control states, the noise is filtered by R58 and C3 L
Difficulty has been experienced with certain controllers in that
NDAC can transfer data on to the bus too early. Resistor R62 and
capacitor C7 slow down the transitions of NDAC to overcome
this problem.

M29-40 (IRQ) is used to inform the CPU when certain states

occur, In particular, the IRQ IO signal is generated at each byte-
transfer over the bus, whether the byte is sent or received,
Additionally, IRQ IO is activated whenever certain specific
commands are received, e.g: 'DAC', 'SPA', and changes between
Remote and Local Status.

When the CPU receives IRQ IQ , it addresses M29's 'Interrupt'

Status Register, then M29 identifies the reason via the instrument
data bus,
For further information refer to 'Getting Aboard the 488 Bus'
published by Motorola, or the appropriate device data sheets.

6-10
 (Circuit Diagram 400994 Page 11.1-1 and Circuit
400993 Page 11.1-2 and 11.1-3)
The circuitry described in this section perfonns the following
functions:
Provides front-panel operator control of instrument Output,
(Fig6.6 and CircuitDiagram400993 Page 11.1-
Function, Range and Mode circuitry, by push-button keys.
Key operation is detected internally and transferJCed to the
2 and 11
CPU via the instrument data bus. U201, a P8279 keyboard/display controller, interfaces the
keybo3rd and LEDs to the instrument data bus. It is addressed by
Indicates the present instrument state by means of LEDs
KYBDCS _L from the Digital assembly, to chip-select CS which
fitted in the keys.
enables commands or data to flow via the data bus at D 0~7 • The
Generates audible wa.ming of errors, failures, and high voltage CPU sets addressA0 to Logic-0fordataflow; butforprogramming
at the Output Terminals. the interface for mode change or during i.i,itialization, A0 is set to
(Also see Circuit Diagram430648 Page 11.3-3) Logic-1.
In addition a pushbutton switch sets iristrument Power ON and
OFF (refer to Section 6.7) and a 'Reset' key provides a hardware
reset for the safety monitor (Watchdog) circuits (refer to Section The WRTSTRB_L signal from the Digital assembly is applied to
6.4 ). The circuitry is located on the PCB Assembly WR on U201. Data or Command is input to U201 from the CPU
(400993) and the Switch PCB .Assembly (400994), linked to the data bus dULing VVR low and CS low, and is latched on the WR
CPU by control signals and the data bus. positive- edge.
The RDSTRB_L signal from the Digital assembly is applied to
llEllJ) MATfil!CIES U201 RD. Data is output from U201 ontothedatabusduringRD
400994 11 low m1d CS low.

The keys are electrically mnmged in a.r18 x 7 matrix and the LEDs
in the keys arn electrically a.TYanged in an 8 x 4 matrix as shown
in the circuit diagram. These key and LED matrixes, which am Switching power on to the mstrumentcauses U201 to be cleared
situatedonbothhalvesoftheSwitchPCB !">s:s1o1nu11 the PWRONRST pulse from i:he Digital assembly. 'fhe
to each other and to the Display PCB assembly via a ribbon cable. interface is then programmed during initialization as follows:
21, Cnock di.vk'leir §et to 'divide by The memory clock
(E) at approximately 680kHz is divided by 8 to give an
internal clock frequency of 85kHz.
l:J" AKI !!!ilieireKii di.vfuliofill by ].(Oi reduces the scan clock to 5kHz
giving a scm cycling frequency of 333Hz.
+SV
ov
_l_ >------
PWRONRST
<to EIDltooed OCeybrnud §tam:
1
PowerON The scan output from SL3~0 is a 4-bit count.
SL3 is not used; SL2 _1 scaris U203, SL2 _0 scans U202.
' 'i FlESET

D j •:([~·~~~"~!~ B~s· DATA do KeyllMJJSJ!frdl Mode:

Key Relum lines
(Matrix Rows)
The internal keyboard RAll/l is programmed as FIFO, input
being routed via RL7_0 return lines. Two-key lockout is
Memory" Cloc!t CU<
68-0ltHz employed with debounce.
EncodedScan to U202 snd U203
KYBDIRO_H INT VVhen decoded, selecJs:
'I Key Matrix Colunms
°‫ﹰ‬
"" ]l))fapfay Mooe:
SL 0 LED Matrix Rows Eight character left entry for the LED display.
KYBDCS_L cs
Inter-digit blanking: all 1's onB 0_3 and A0_3 between digits.
ROSTRB_L li1l

WATSTRBJ. WJ!I
l!So2o2,3 ll201 Reprogramming
LEO Output byles
(columna)
The frequency Store key and the 13 dual C keys have a
Address bit~
COMMANDS• 1
(lnltta:llon and
Mods change)
"' reprogrammable function. When one of these keys is pressed,
U201 is reprogrammed into Scanned Sensor Mode. When
released, U201 reverts to Encoded Keyboard Scan - Mode.

IFUG" (Ui U201 (P8279) ~

SHMPI..U!FIED SCHEMA THC

6-11
 SCAN DECODING 6.2.5 KEY LED OPERATION
The encoded scan output from U201 (approximately 333Hz After performing the change requested by the key depression, the
cycle frequency at SL2 _0 ) is decoded by U202 to energize each CPU changes the bit-patterns stored in U201 i~Lernal display
key-matrix column line once every scan cycle. SL2 _1 scan outputs RAM. As this is scarmed internally in synclmm:'.sm with the
are also decoded by U203A to energize each LED-matrix cathode decoded outputs of U203A, each output byte of B 0_3 / A 0 _3 drives
driver once in every scan cycle for a period of two digits. the row of LEDs accessed by U203A output lines.
The bit-pattern of the byte selects the LEDs to be lit in t.hat matrix
SELECTION
The keys are electrically grouped within a matrix of 8 rows of 7 Logic-1 = LEDs unlit;
(Note that the Reset and Di§pllay keys arenotpartofthis matrix). Logic-0 = LEDs lit.
This does not conform to their physical grouping on the front During changes of output between successive bytes, all the lines
panel. Each of the eight return lines RL0 7 defines a matrix row, fromB 03 / A 03 are set to Logic-1 to avoid spurious LED flashes.
whose seven elements are scanned by U202 (Low active).
The eight power drivers in U206 drive the LED anodes, from a
The keyboard memory RAM in the P8279 (U201) is an image of +SY supply regulated by U207. Darlington drivers U202- U205
the key matrix, internally synchronized to the SL20 column scan, drive the LED cathodes.
and receiving row inputs from RL0 _r It thus stores the state of
each of the 55 keys. The use of 2-key lockout rejects two or more
simultaneous contacts. Any single key depression is debounced,
initiating the interrupt KYBDIRQ_H to the CPU which then
interrogates the keyboard image RAM in the P8279.
The next action depends upon the key's function:

a. !key pressed:
i. U201 is reprogrammed into Scanned - Sensor mode for
as long as the key is pressed, the CPU acting on the key
information.
ii. If a single - or 'v" key is held down for longer than half
a second, the display enters 'auto mode, running at
about 3 digits per second.
m. When the key is released, U201 is returned to Encoded
Keyboard Scan mode.
b. 'Store' key pres!ledl:
i. U201 is reprogrammed into Scanned- Sensor mode for
as long as the key is pressed, the CPU acting on the key
information.
ii. If an FI to FS key is pressed while Strnre is held down, the
appropriate frequency memory location is accessed, and
the output frequency is reset to the value in the memory.
iiL When the §t((])]re key is released, U201 is returned to
Encoded Keyboard Scan mode.
c. Any other key pre§sed (but not IRe!>€1i: or Displlay):
i. U201 remains in Encoded Scan mode; the scan continues
as the CPU is acting on the key information.
ii. KYBDIRQ_H interrupts are generated only by the low-
going edges of the key contact pulses, so U201 remains
sensitive to subsequent key depressions.

··-·- ·-·------~--·-····-~------·------------
6-12
6.2.6 AUDIBLE WARNING BUZZER
There are two ,easons for an audible w2.rning from the calibrator: 6.:'2J:L2 "Beeper' Control
When the instrument enters fligh Voltage State(> 1 lOVDC (Circuit Diagrams400993 Page 11.1-land
o~ >75VRMS). A 4kJJ:z tone is used, pulsed as described in Circuit Diagram 430648 page 113-3)
the User's Handbook. TheAlann Controlcircuitr; on the Display assembly is overridden
When a.n inappropriate selection is attempted, or if any FAIL for Beeper control. During a 'Beep', the HF TONE signal is
or Enor message is displayed. For this purpose a sbgle inliibiicd, and the LF TONE signal at U209-12 is enabled to
580Hz 'Beeper' p1;lse is generated . contrcl the bm:,:er output.
0,, thB Analog Interface assembly (page 11 .3-3) the Beeper
16,2.6.:l High Voltage State Alarm Cq::mtmi ccnsists cf a monostable timer and NAND logic. Unless a
(Circuit Diagram 400993 Page 11.1-1) requiremeni: arises for a 500Hz warning, the BEEP signal is at
U203B and U209 act as a control latch for the warning buzzer. Logic-1. ThusM55-3 is atLogic-0, soM54-5 atLogic-1 inhibits
With ALARM_L at Logic-1 (+5V) U209 remains unchanged; the LP TONE signal, M54-4 remaining at Logic-0. M54-8 is at
but with ALARM at Logic-0 (OV) the state of U209 depends on Logic-0 enabling the 4kHz HF TONE, which is passed to the
the condition of the A 0 lL'le: Disphty assembly at U209-8 (page 11.1-1).

A 0 at Logic-1: the buzzer sounds a tcne. When required, a single 'Beep' is originated by the CPU pulsing
A 0 at Logic-0: the buzzer is silent. M34-3 (pagell 3-l)tol.ogic-0. Thisis the BEEP signal applied
to L'le monostable M55-2. MSS-3 rises to Logic-1 for approx.
The latch is operated at CPU speed. Two ALARIVf_L pulses Me
150ms until the rr,onostable times out, then reverts to Logic-0.
used for each burst of sound. The first, 'Nith Ai at Logic-1, starts
M54-8 is at Lcgic-1 dwing this period, inhibiting the HF tone and
the b1Jrst; the ,econ<L with A 0 at Logis-0, ends it.
setting M.'.:i4-ll to Logic-L This is pa~sed to U209-8 on the
The Viavcfomu; !'c!,d huth ~able in Fig.6.7 illmtraL the ac:ion (of Display assembly . where it eru;ures that U209-13 ir at Lugic-0 lo
the latch. override imy High Voltage alarm. M54-5 at Logic-0 enables the
DuringPOWERONi.njtill.Hzation,ther:omhi.m~tfanafP.lARM_L 500Hz LJF TONE signal to pass via M54-4 Lo U209-12 on the
atLogic-0 andA9 atLogic-0is applied to U203B to forcepower- Display assembly (see po2ge 11.1-1). As U209-13 is held at
up in me disableo condition. L:igic-0 tluring the beep, the buz,.cr p10d-.1ces 150ms of audible
500Hz output
Ti1e 4kHz HF TONE signal at U209-8 migi.,ates in the Precision
[,,iviuer com-ner wh ::h ill iitua,w 0n the Analog Inlerface
0

fo_ssembl:;. (Refe, to 'C:ir::uit 1Jiagran430648 pcge U 3-J.). Et.J,~BLl, ~,,i I""· LATCH D 1St,G LE -'"1 I·"' uncH
(ENABLED) I (DISABLED)
The SOOHz LF TONE signa: at U2C9-12 runaLi.s i;,t Lugic-'i'.3
-sv
I I
unless thP, 'Beeper' in the Analog Interface assembly is switched.
(Sec: section 6.2.6.2).
Note thatA0 may re used for other purposes whenALAr~_Lis
!.1200-15
ALARM_L
''"
~J Ll
I I
at Logic-l, but this will not affect the buzzer state. •Sv
I I
u200-·14 I I
Ao
,)V
I I
I I

!.1209-9
L"_,V

ov ""'
-·1 :______~_J: ____
I I I I

I I I I
•SV
I I I I
U200-11
1111111111 111111111111111111111111111111r_: _ _
ov =

tl203/li209 Truth TaDle

U203-15 U203·H u2m-12ju200.11 UW9-9 BUZZER

(ALARM_L) (",,)

0 0 1 0 1 DISABLED

0 1 0 1 0 ENABLED
j )( 0 0 NO CHANGE NO CHANGE

0 e OV; 1 e 5V; X e Eilhar 1 or 0

FIG, fi.1 BUZZER CONTROL LATCH ACTION

6-13
 II
II
II
l
I
I
II
i
I
L
l

II
I
I

I
I
I
I
I
I
!

0-J,~
The circuits described in this section perform the following STAT~C
functions:
400993 Page 11.1-2)
Storage of display data in a Display Image RAlV!, updated
All vacuum fluorescent digit/block grids and all the
under CPU control.
segment anodes are driven from the +5V supply. They are
Generation of multiplex count which selects segment data connected to this supply by conduction of the grid and anode
from the RAM, and energizes the appropriate digital blocks drivers in UI05, Ul06, U107 a.nd U108.
in synchronism. When not energized, all and anodes are pulled to
Distribution of negative supplies to energize ,he vacuum- approximately -34V by lOOkQ resistors connected to the
fluorescent displays. -VDISP supply. The -VDISP supply is generated by voltage
doubler circuit D102 - Dl05/Cl 13 - Cl 15 which is driven from
Part of the Digital assembly (480796) houses the display
the filament driver UllO.
multiplexer, which includes the display image RAM, the interdigit
and multiplex counters, and control circuitry. To energize a particular digit/block (simultaneously on both
displays), the multiplex decoder causes the relevant grid driver to
The two vacuum-fluorescent displays, the block multiplex decoder
tum on, lifting the two grids to +5V.
and segment drivers are located on the Display assembly (400993).
The block diagram. of Fig.6.8 shows the a..""Tangernent and main At the san1.e time, the two sets of data (for the characters to be
intercon_nections of the display circuitry. displayed in the two blocks) are extracted from the Display Image
RAJviI, as1d to the segment ai,ode drivers.

G
(Fig.6.8)
The purpose of the Display Image RAllliI is to accept and store
cu..rrent display data, which is read out to drive the display
segments. The Display Block Counter generates a 4-bit count at
2kHz which scai.---is the 11 digit-blocks of both in parallel.
The same count scans the RAM, selecting segment information
for each block in turn. As there are two displays, and therefore
two RAM bytes to read for each block, the 'MODE' display data
is first entered into a holding latch during the i..,ter-digit blanking
period at tl1.e sta.n of the time-slot for its block.
To update the displayed characters, the CPU writes into the RAllliI
at high speed (680 kHz), using signal XDDSP to connect the
Address bus through the Address Source Switch to the RAiv.!.
XDDSP also connects the Data Bus to the RAM through the Data
Bus 13 uffers, writing the new segment data into the selected RAM
Address. The high speed of the transfer, compared with the much
slower scanning speed in Read mode, avoids spurious effects
appearing on the displays.
Each RAM address contains only 8 bits, but !:here m-e nine
segments in each display block. Comma-segment information is
therefore not written into its normal block address in the RAM,
but stored as a bit in a sepm-ate 'Commas' byte, which holds the
data for all eight blocks having a comma. The byte is read out into
a Commas Data Holding Latch, once every block-scan cycle, and
then selected for display by a Commas Multiplexer 8-into-l
switch.

6-15
 WRITE MODE

Addr©SS
Sourcs M41B Scan
Swilcil (Read Mode)

+SV

M16
TP4
Display
[}!'------1---------o,__--"'¾
10 CS
0
lmaga
RAM

M111! M2
lwislal@ ISlull,mi

!FffG. 6.9 RAM ACCESS~ WRffE MODE lOGiC

Whenever the CPU is prograrnmed to update a display (eg. for Sc~il11 Adcires$ 11uull'i\1rn~~"
Range, Function, Mode or Value change) it sets address decode 430796 Page 11.2-1)
XDDSP to Logic-1 with each byte of data to be transferred. This
causes M3 l and M33 to select the CPU address lines .1\ 0 which M31-l (SEL) at Logic-0 causes the RAM to be addressed from
are mapped directly to the RAM address input lines A 4_0 • The the display block scan, mapping M41B outputs: Q4B, Q3B,
RAl\/i is placed into its write mode by signal XDDSP at Logic-0 Q2B, Q lB to RAM address input lines: A 0, A 3, A 2, A 1 respectively.
(M17-8, TP5, Ml6-16). This bit-rotation interlaces the extraction of display data, in
synchronism with the interlaced block selection by the Display
The RAMM16 is divided into two sections, using the address bit assembly Scan decoder.
A4 to differentiate between OUTPUT andMODE display images.
When the CPU is loading the RAM with OUTPUT display data,
ft3,4,2 Block M11Jiil!p!@x
it sets A 4 to Logic-1, passing to set M 16-19 (A4) input to Logic-
1. MODE display and COMMAS images are written into M16
(Circuit Diagram 400993 Page 11.1-2 and
with A4 at Logic-0 (M33-4 and 13 at Logic-I in write mode). Figs. 6.11)
(In Read mode M 16-19 is again used to differentiate between the The 4-bit Block scan output MUX A3_0 from t.h.e multiplex scan
two image sections). counter M4ll3 (Digitalassembly)is usedatDATA41 input to UlOl
The signal XDDSP (Ml 7-8) enables the tri-state buffers Ml and (on the Display assembly, which decodes it into an active-low 16-
M2, connecting the CPU data bus to Ml6 data input/output lines line scan S 15 _0•
D 0_7 • With each byte of display data, the CPU also generates the To strobe the commas, M3 output S6 generates the signal COMMA
write strobe signal WRT STRB. This is combined with XDDSP STRB, and its When the count reaches output S 13, feedback from
(Ml 7-6, Ml6-10, TP4) to enable Ml6 internal Input/Output tri- this ouput via the MUX RESET _L signal terminates the scan
state buffers to accept the data byte (chip select CS 0). Once the cycle by resetting M41B on the Digital assembly. Count 6 of the
display data has been loaded into the RAM, the CPU returns multiplex count is decoded at Ull3-6 to produce the
XDDSP to Logic-0 and the RAM reverts to Read mode. COMMASTRB_L signal, which is fed back to the Digital
assembly to control the latching of comma information from the
display RAM into a holding register (see Section 63.4.7).
Eleven of UlOl's outputs sequentially drive the display grids
Unless the CPU has data to update, the signal XDDSP remains at
(both displays in parallel) via level shifters in UI05 and Ul06.
Logic-0, to hold the display multiplexer circuitry in Read mode.
As can be seen from Fig. 6.11, the interlacing is used to avoid
The RAM data bus is isolated from the CPU data bus by tri-state
consecutive activation of adjacent blocks.
buffem M l/M2, and M 16 is chip-selected in read mode by M 17-
6 andM17-8 atLogic-1.

6-16
 0 ~~UXRST
J2-76 (•"F,°'"om'--,,-F,-on~,~Ass-.Gm~b~ly)~--~

CPU Aelciu'901] Sm,

(Not Selec@d)

Dai:o

'OUTPUT
Commffi
Data
J2-S8

CPU Address
Line A, 4

{Ignored in
Read Mod2)

l(DDSP !Jol'.l:J!Jl(mblo

lsolal.0d l'iom
CPU Data BU3:
by Mi/M2

~~"---,i
CPU Aclclress
Logic-0 during MUX 0110
(Logic-0 for Lina A 0
Mode Display)

S'//l!ffCC'i.iNG

1ftl)!L::S [J)n§[oiiai17 [J)81i©J S®i®~in©rru li\/lUJC /ill 3-<lSCAM

430796 IA.3 I /ii\2 I
A1 ~ I Display Block
U1!!1 1:lt\utl<il-1 l11p!Ji Grid Energized,
1)4 I 0:3 I 1Ji2 I D1
or Signal Selected
When the processor writes display data h1to the (for both displays
Display Image Rfa~. the I\ used to select slmultarieously)
the MODE or OUTPUT display data storage area
(seepara633 InReadmodealso, Ao t\3 li\2 A1
A 4 is set to to read OUTPUT display data,
and to Logic-0 for MODE or COMMA data. 0 0 0 0 So Al
0 0 0 S1 A3
For an alpha-numeric display block, 18 bits of data
could be required: 0 0 0 S2 AS
0 0 I S3 A7
One byte - OUTPUT display block segments;
0 0 0 S4 Ag
One byte - MODE display block segments;
Two bits - COMMAS (one for each display). 0 0 I S5 Al 1
0 I 0 S5 Not Used
The problem of transferring two bytes of data
0 I 1 I S7 Not Used
along the smgle-byte RAM data bus is overcome
by strobmg each MODE display segment byte into I 0 0 0 S5 A2
a holding latch (M32), during the first 30µs of its 0 0 Sg A4
block selection time-slot. The MODE display 0 I 0 S10 A6
section of the RAM is selected by setting its A4 0 1 S 11 A8
input to Logic-0 for this 'Inter-digit' period, during 0 0 A10
S12
which the inter-digit blanking gates, (M42/43,
0 1 S13 MUX RESET
M45/46), set all the segment lines going to the
Display assembly to Logic-0 (segments OFF).
0 S 14 Not included in cycle

COMMA data is stored in the Display

S15 } (MUX RESET at S
13
)

RAM as a separate byte (refer to Section 6 3 .4 .6).

6-17
6.3AL4 ""'"'"""'" Timiflg
(Fig. 6.12)
Read mode is driven by a 32kHz square wave (Waveform 'A', ,r;:, The positive-going edge of Waveform B lifts the RAM A4
generated from the 13-bit counter in the Analog Interface input (Ml 6-19) to Logic-I, addressing the OUTPUT display
Assembly Ml5-l l), used as clock for a 4-bit counter (M41A). section of memory. A,_ 0 is still at 0101, selecting block 6
The three most significant bits are combined at M30-10 to display data (in our example a figure '8') which it loads on to
produce Waveform B, the display master-timing pulse, used also the RAM data bus.
for inter-digit blanking.
The end of the master timing pulse also releases the blanking
The following example explains how the display data is set up for by enabling gates M42/M43/M45/M46, so the data for both
the next display block in sequence, during the 62.5µ,s of the MODE and OUTPUT displays are now delivered to the
display timing pulse. anode drivers on the Display assembly.
This condition persists for 437.Sµs until the next master
Example
timing pulse, when Waveforms B and C repeat the process
for the next block of stored display data.
Initial State: M41B count has already reached 1001, and the
block-4 grids of both displays are energized (Fig.6.11). At any time during the cycle, the CPU may force Write mode.
This will not disturb the scan from M41B, but XDDSP will reset
The OUTPUT display data for block 4 is selected in the Display M3 2 outputs to Logic-0 (M3 2-1 /13 ). However, the speed of byte
Image RAM (Ml6) to drive the segment anodes for a figure '6', transfer from the CPU ensures that the data being transferred is
which appears on the OUTPUT display. not visible on the displays. Subsequently, each block will be
driven by its new stored data.
Block 4 of the MODE display is showing a figure '3', and ihe data
for this is being output from the MODE display Holding l,atch
(M32). The data held in Ml6 for the next byte (Block 6 of both
displays) is:
OUTPUT display Figure '8'
MODE display Figure '7'
JBlod; CharmgeoveJr: The next block is selected during the
display master timing pulse (Fig. 6.12, Waveform
,i. The negative-going leading edge triggers the scan counter
(M41B) whose output advances to 1010 (block 6). On the
Display Assembly, Ul 01 de-energizes A4 grids and energizes
A 6 grids.
lb. For the duration of the Display Master Timing Pulse (Logic-
0 atM12-14), the A 4 input to Ml6 is set to Logic-0 as A 3 _0
inputs are advanced to 0101. MODE display data for figure
'7' is loaded onto the RAM data bus as follows:
i. Ml 7-6 at Logic-1 selects M16 at Ml6-10,
it lVl 17 -8 at Lo gic-1 holds M 16 in Read mode,
m. RAl\1 address A4 _0 = 00101 reads MODE display block 6
data onto the RAM data bus (Ml/M2 isolates from the
CPU data bus),
iv. M30-14 at Logic-1 strobes the byte into M32 during the
30µs of Waveform D, then returns to Logic-0 leaving
figure '7' data latched at M32 output.
v. Ml2-l at Logic-0 blanks the two displays by setting
M45/M46/M42/M43 outputs to Logic-0, regardless of
their inputs from M32 and the RAM data bus.

6-18
 A

'Previous' Display Block 4-:i> 'This' Display Block

211H2 Sc<111 Enabl®
i\li3(J.11J/12
lnl®M:llgil slrnlil® amci f11l418 Clocl,
rr- 62.5µsec -j
V Display 8locl,-increment Trigger

Dala l©acilng Sirnb®

M31li·14 =30µsec-::,..
M32-2/14

E RAM Daila elus;

Cl!l>!'il®111s; Previous Blocl1 This Block This Block
__o_u_T_P_UT_1_D_i_sp_la_y_Da_t_a_ _~j\ MODE Display Data OUTPUT Display Data

~
Previous Block ~ This Block
_____MODE Display Data
,___/'
./~
~~---MODE Display Data
------
~
Previous Block Se9ments Blanl,ed I This Bloci1
__o_u_T_P_UT_1_D_i_s_p1_ay_o_a1_a_ _~ 1---"-------L____o_u_T_P_UT_1_D_i_s_p1_ay_o_ai_a_ _ __

Previous Block Segments Blanked This Block

MODE Display Data MODE Display Data

(Circuit Diagram 400993 Page 11

The strobed segment signals from the Digital Assembly are input The above action proceeds for both displays sii11ultaneously. The
to the Display assembly on Jl02 and J103. These are already grid driver energizes its corresponding block grid on both displays,
synchronized to their blocks by the 4-bit block scan MU'.,( AH at the same time as the anode drivers are loaded with the correct
within the Digital assembly. block bit-pattern for their own display.
For each block in sequence, the appropriate segment bit-pattern During change-over between blocks, all segmentinputs atLogic-
is set at the input to the segment anode drivers in Ul06, Ul07 and 1 are returned to Logic-0 by the inter-digit blanking strobes M42/
U108. The correct block grid is simultaneously switched to +5V 43/45/46 on the Digital assembly. This turns off the drive
by its grid driver, lighting the appropriate digit For bits at Logic- transistors and blanks the display. The high scan frequency and
0 the anode drivers remain off. persistence of the operator's vision prevents the blanking being
observed on the display.

6-19
6.3.4.6 Comma Logie::
(Circuit Diagram 430796 Page 11.2-1)
(Figs. 6-10 and 6.13)

IVIUX SCAN
0110-c,.AIJ 010·1.c,. S5 <> A11 0·110<>S6 1> COMMA STROBE 011 H> S7·i> Noi Used 1000-0>A2

COMMA s'(l'fi:l 500µ.s

1\1112-12/15

-u62.5µ.s
Display 1\/laelsr
Timing Pulse
M30-10/12 LJ LJ LJ
lf30µ.s
Data loacling
Slrnbe M30-14
M32-2/111 _ _Jl,____ n n
Comma Laleh
Clock M30-13

_____0_1d_c_o_m_m_a_o_a_1a_ _ _ _ ~XL______ N_ew_c_om_m_c_~_o_a1_a_ _ _ _ _ _ _ _ _ _ _ _ __

Time-Muliiple~sci
Comma Dala
1\1112-5
OldA9
Comma Data
OldA11
Comma Data
, , , _ 81ankedbyM12-13--+-- AlwaysLogic-0 --o.l NewA2
Data

~ T.iMDNG WA

The corn.ma is the ninth segment (i) in each of the numerical

The block-multiplex scan from M41B selects the correct X input
display blocks. It cannot fit into a block's byte in memory, as
to synchronize with activation of its display block grid. 'fhis is
there are only eight bits per byte. But all the comma information
output from Ml3-14 (Z), into blanking gates Ml2.
can be stored in a single byte of memory in the RJ\.M (RAM
address 01100). This is possible although there are nine numerical Comma information is bfanked during COMMA S'fRB , and by
blocks, because the ninth block never requires a comma. Legend inter-digit blanking during display-block change-over (Ml2-7).
blocks A 10 and A 11 do not have a segment i.
The Comma drive line from Ml2-5 to the front panel, via J2-88,
The RAM COMMA data is updated by the CPU in Write mode, controls the segment i anode driver for the OUTPUT display.
and is read out ( as though it were another display block) by M41B
If commas are required on the MODE display (e.g. in 'Spee'
scan 0110 during the master display pulse (Waveform B sets
operating mode +Lim or -Lim) they will always be in the same
RAM A4 input to Logic-0). 'The sameMUX combination 0110
display blocks as the OUTPUT display. When this mode is
is decoded at U 113-6 on the Display assembly to generate the
selected, the CPU pulses the COMMAS line to Logic-0 at the
COMMA STRB signal (COMMAS'fRB_L on the Display same time as Address line A 0 goes to Logic-L Tristate buffer
assembly). outputs Ml-11 and 13 go to +5V, setting M2-13 output to +5V
ThusforthedurationoftheMUXcombinationOllO,theCOMMA (Logic-I). Outputs Ml-13 and Ml-11 go tristate when the
data is on the RAM data bus, but the blanking gates prevent it COMMAS line returns to Logic-1, leaving M2-13 latched to +SV
reaching segments a to h. by the positive feedback action of Rl L So M44-2 enables the
comma data to the MODE display segment driver, via J2-73, to
copy the OUTPUT display commas on to the MODE display.
When MODE display commas are not required, Logic-0 (OV) is
The COMMA STRB signal is inverted and combined with the
set on A0 with COMMAS signal atLogic-0. Thus M2-13 latches
Data Loading Strobe at M30-13 as a Logic-0 pulse, whose
to Logic-0 md M44-2 disables the flow of comma data to the
positive-going edge clocks the comma data into latches Ml4/15,
MODE display.
approximately 30µsec after it has been loaded on to the RAM
data bus. The permanently-enabled ouputs from these latches are
input as X 0 7 into the 8-into-l multiplexer M 13 during a complette
MUX scan until the next COMMA S'fRB signal.

6-20
 6.4 Jl.NALOG ONTROL ~NTERFACE
The ciri:::uitry described in this ::sctfon p'crfonn£ the folk wing functions: Ti"iG: Trc\llril1fe;' C:·©ls
(Fig.6,14)
Provide, a two-way interface via a serial darn link between out-
guard digi ,al ,:,rov;ssi11g a1d rn-guanJ an2log ,;oni:ml r:ircuitr,;' or, fhe; ;:.'PJ uses an address-code s,gnal Ai~1Ji:~s, ,(i (Analog mterface
the reference divider ?,ssembl:r (s,~e Fig. 614). :;tan) t,, iniliat: er.(;h ?.4-11it t.hift, by triggering 1 s,'<par;ite doc
0

<>,eneratnr (M2, M3, M4) which procl11ces a burst rif 24 clr:,cks per shift.
Moniwrs i.he CPU operalion., serial transfer, ri1gital supply fa1lnn, Data is clocked in a serial string through a continuous loop comprising:
and rcsta,·, o:c:,eraLiorr: (v,"itd,rlo1J, i,,tpc'.·ing a cmtr.ilkd sEc"ety
d"~ault condition if there is a clm1ge1 cflosing digit~.l c<:mtrol of the ,he "18-1::it, r,:rial in/1,arn1lel ')Ut, a:1Liog ,;omml :hift regi ;teY;
am.log functions. the 16-bit, parallel in/serial out, status shift register:
back to the SSDA receiver (Rx DATA).
A manual res;;t of lhe safety moniirH is provid,;don th<c frool:pc1nel (sec
Fig. 617) The ser; ;ii d'cta E'xin;.:; is uJrrcctly locJ.tecl after two 2L1-bit ,;hif1s, so then
the SSDA generate~ a strobe pulse which:

··:·9 l
'
Safety and Conrrol informatinn is inp11 t fror.i DigitJJ.l (Circuit Diagram
21, Transfe;s the data p1es,;:,I1t hi th;;; serrnl data :;trir,g o[ th" six 3-bii.
'lnalog-•:ontrnl Jlift reisten (l'Vi27, M25, M3L }.,,lJ 0 , lv".30, ~,11 'i)
into their enabled p;uallel outout registers and onto the analo1;
~ 4l50796) and Frcmt(Circuit Diagram,400993) A..ssembli,:os to out-guard control bus.
,-"'-~~~-~ <~ crrcmts lm;ated on i:he A_na!og Interface Assembly (Ci1c!1it Diagram
480648 ), pr::icessed and tra,,sferred across the 'Guard' isolation barrier When the strcbe ends, further transfer is disabled and the registers'

1001,:.ang
~ccJ=A
:~i, to in-gu!:lidciicuitsin Lhe fo,ferenceDivide; Assembly (::ircuit Diagro11.
480652). Aftei:fo:i:he~ proce;,ing in the Eefe,ence D:-1ide, AEsen°bly,
output ciata is fatched,

~·rr~.~
Owi-Oucrd/
lr1a~fE.~d S3foty and cont:ol in£ormatiCV1 is ouro~t to i:he 7o!lowing asserr;blies: b. Injects t.tie starus data at each of the 8-bit parallel inputs of the two

~
lnte~is.ro
(Opt:i-Coi;pk::rrs sl.atu.E shift regist,ers (Ml8, M22) intc conesponding :ocaciom in
f,;·1, Mf. J.17, L.'i3)
-Os>
PElrGl.llo!•ln, Sbe Source i.ssemb~y (CirG,it Liag;·a.v;. 480446) the 3erfal data string.
T,lgg<>rio
-,_}/:'ltt<;\ljg~
CfrcuH
Serlci=out
'StE.OJs'
p._c .f'3Sembly (Circuit Diag,·0,m 400;}44;
l Shi-ft A09h;,tern
{M18, M22i
PA A.ssem.bly (Circuit Diggmm d.f,0618) When the strobe ends, the parallel inpJis 1-0 the status registers are
DC Assembly (Circuit Diagram 480536) disablecL
! ---=-= M Current (Cfrcui; Diagram 401008), C:'1..rns (Circuit ;:Jfogn2m
I 40100) or Current/Ohrns AEsembly (Chrnh Dfr2grcn 430614) After th-e sti"obe puhe, the CPU initiate, a f\1rther circufation of serizJ

·i~
I
High Voltage Assembly (Circuit Dic!g;am.480537) data (including the status data), in order to obw.ir, the status data and
1 return the analog control bits tci the SSDA RxDA1' Aregisterforpa-ity
c1_:"0:4::I checking by the CFU.
~
Certain selec.ed 'Status' signsls, Driginati.,g m tl,e analog iJ.sserntlies,
'--==--'--=
I &n-GJar~ B
are returned ,o th" CPU durfr1g the (:'.'!ta trn,,.sfer, Thus, ,he iatE linl::
forms s conli11ucms loop, a; sho"''Il L'! Pig.6.14. 'fhis extr.ii (confirmawry) circulation requires i:li.ree more 24-bii shifts,

,
1
f/EaERE, -ce ;'/V/Oc::'1t!'33!!IL:I'
~ so a complete dara. traru;fe:r consists of five shifts. If no error is detected,
=~=~========== " the SSDA provide3 a trigger-enwle to a]fo,;.' u;;dat<cs to prevent
acti-nifr:m (BAPsK) of the vratchdog circuits.
(Citcuii DJ,2grarrts. 43079c Pcge l 1.2-2, "i306d8F2ge
If an error is detec:ted on ,he first transfer, the CPU ac\ivates a second
113-3, 430652 Pages 11.4-4 and 11.4-5 arid Fig. 6.14))
cornple:e trn:r>sfer, and fr1en a third if a-11 erro;: is detected on the second..
If tl1e ,mo- persists after the third transfer, Jie trigger-enable is
A bi-directiorral serial data li.'1k passes infonnatmn acrcss the guimi
withheld, and the instrument will shut down under the control of the
isolation screen; passing CPU corrn:nmds ,ncc,ntrGl thein-gmrr::lar,_alog
·watchdcg' safety monitor,
circuitrJ, and retumLn.g critical status signals from the gua:;ded circuits
back to the CP:J.
All inte,facing between out-guard and in-guard circuits is 'achieved
using electrically-isolating opto-couplers.
The link is m&naged by ti synchron01.;s serial data aoaptoir (SSDA)
which, h~ ving fa.:;t bc:::n l.:;adt:d v., lth C:.rrec byt;:,s cl cm1trnl ms1.rucuon:;
by tli. rnisrop~occ3sc,; trc,nsrnits ;Jier~sultan,: '24-1}itv.,:;rd acrcss ~,:-Jard
0•

one bit at a time, via its Tx DATA channel. L}~it~ ·ir~mifeir Org~mzgit.mr1
(Fig. 6.15)
The '+8 tits n"cessar; to ,~onuol the Jnak,g Cl!C1Jitry Jm~ rec,uire two.:
s11cc"",;fr,s 24-bit tra:-iSmhsions. Data is transfe1Ted sedally via the SSDA, control registers and status
regJSters as directed by the CPU.
SimuH,,n.,ously withem.:h74-bit li'.ansmission, theSSDA rece1v es a ?.4-
bit v<:ord -,ia ;ls l''.J, lC/l\.T,~,. ch'.l.nr,el, e,rnl::,iing che :PU to ,,,anty-chect The ex,har,,r;e 0f dzta bstwesn the CPU 8ncl SSDA i~ mBde in byres of
its re1:urneci data, ancl obtain the sta!Ps of rhe ruizlog fonrtior,.:1. 8 bits on tilein~trument data bus, each exchange comorising three bytes
(24 bits) of p~.ralJei dat.a.

t-22
6-22
The shifts of serial data the in-guard circuit are i?o A foU_M burst of 24 docks again shifts all data three bytes to the
by clocks which are controlled from the CPU, a,,d the SSDA Rx rntum right. The CPU reads bytes ND2, ND3 md l\1D4 from the receiver
registers are cleared when read the CPU. registers. After the shift is complete, new data bytes ND4, ND5 and
J\ID6 a;re re-loaded inito the transntlti:eI ·r"·''"'"''"·"'·
Once the in-guard serial data is coae,ctl.y pub,uuw,•u. at t.1ie to the
control registers the SSD.A_ generates e, strobe which enables its
9

trn.m;fer to the parallel outputs

enables -·.11--swu
into the serial data string. ends. If fill error is detected betv;een nevv data transmitted and nev,
data receivecl Lhe transfer process is repeated; tl1:ree attempts are
9

The transfer requires five serial data shifts? each c:,llovred before 8~ fault condition is declarecL
bytes, through the registers. t.h.is
are loaded with bytes of nev1 data the status are loaded
with new status data (NS); and the whole of the NO and NS data is
returned to the CPU, whlch:

a. verifies that the analog control bits of the serial data string return to
the SSDA Rx DATA register without error. This indicates that at (Circuit Diag,a1r1 430648 Page 113-3)
least, the correct bit pattern was applied to the analog control
register inputs at the time the strobe was generated.

b. acts upon the status data received. are first switched on or a,, external reset signal
PWR ON RST On Reset) is
8ms.

this period, the SSDA is latched in a reset condition to prevent

The sequence of events in the transfer nn~n,t,,,,.-. is as erroneous output trn:n.sition..s at its Tx and Rx interfaces; i:he internal
follows, referring to Fig. 6.15: tra,-ismit registers are wJubhed to prevent Lhe
data bus and the SSDA strobe output is held at
ru. Three bytes of new data, ND1, J\TD2 ,md J\TD3 l!I'e loaded into the
SSDA transmitter registers; this dataisdestinedforcontrolregisters After PWR ON RS:T returru; to the ii-istrument state 1s
Dl, D2 and D3. The SSDA receiver registers were cleared when iriitialized by the finnwmce program. This routine cleB..rs the latches,
lastread by the CPU. registers md SSDA strobe.

b. A burst of 24 clock pulses, initiated by the CPU, shifts all data three
bytes to the right. After the shift is completed, lhe transmitter
registers are loaded with new data bytes J\TD4, ND5 and ND6
(destined for control registers D4, D5 and D6). During this period, The conditio:ru; for parallel data on the data bus to be accepted by the
no transfers are made between the serial data string and the parallel SSDA are as follows:
control or status registers.
!!i. Chip-select SSDA CS at Logic-0.
c. A second burst of 24 clock pulses again shifts all data three bytes
to the right. New data bytes NDl to ND6 are now correctly
lb,, Read{Writecornmand R/W m~.,ut;1v·'/U. This controls the direction
positioned in control registers Dl - D6. After ..,,.,."'f"""'u" of the
shift, three dummy bytes are loaded into the tra_nsmitter registers. of darn flow via the Data Bus through the SSDA input/output port.
Old data in the receive! register is ignored. When R/W is at Logic-0, data on the Data Bus is written into a
selected register within the SSDA.
d!. With new data bytes ND1 to ND6 correctly located, the SSDA
generates a strobe pulse. This pulse: !:o T]1eme-mory clock 'MEM CU(' 682.6kHz square wave synchronizes
the SSDA operating cycle to that of the CPU.
ft, latches the 48 bits of bytes NDl to ND6 at the parallel outputs
of control registers Dl to 06; With register address bit A 0 atLogic-1 and input conditions present as
above, the SSDA accepts data from the data bus into a 3-byte internal
it enables the parallel inputs of status registers S 1 and S2, loading lFlDFO register. The data is entered over several MEM CLK cycles and
two new status bytes NS 1 and NS2 and clearing old data OD5 stored in the FIFO register in readiness for serial transmission from the
and OD6 from the registers. SSDA.

e. A third burst of 24 clocks again shifts all data iliree bytes to the is at Logic-0, data transferred into the SSDA
right. The CPU reads bytes NS 1, NS2 and NDl from the SSDA ,n~·nrrnst"''"~· TheSSDAisprogrnmmed
receiver (the CPU may take immediate action on NS rui part of the initialization routine. For details of 'Control Byte'
returru:). After the shift is complete, new data bytes ND1, ND2 and operation, refer ro Motorola 6852 data sheet
ND3 are re-loaded into the transmitter

6-23
The conditions for data to be read back from the SSDA on to the data T11e three clocks ro:e derived from t.he 256 kHz square wave output from
bus are as follows: the 13-bit counter. The 256 kHz squarewave is used directly as t.he
signal '1['z CJLOCJK:' into tl1e SSDA. (Refer to Circuit Diagro.m430648
Chip-select SSDA CS at Logic-0. Page 113-2 -Ml5-14).
Read/Write comma_n.d R/W at Logic-1.
After CTS is set to Logic-0, the transition of the first full
Memory clock, MEM CU(, present.
positive pulse triggers the first serial Tx data bit setup. (Refer to
The data read from t.he S SD A may be from one of two sources, selection 6.]6 Wnv;:,!',orm G
being made by address bit A0 :
With A0 at Logic-1, received data from the serial data input FIFO
'lu CLOCK' is an inverted version of the 256ldlz squarewave. After
is transferred to the data bus. DCD is set to Logic-0, the positive transition of the first full Rx clock
cycle triggers the SSDA. The SSDA thus samples the first Rx data bit
With A0 at Logic-0, the CPU reads an internal SSDA status before the SSDAdock triggers theshiftregisters. (Fig. 6.16Waveforms
register. Kand

'§§J!J)A CLOCK' is also anin.verted version of the 256l<l-Iz squaxewave.

The inversion allows approxirnately 2ms of data sen1p time for all serial
data bits prior to clocki..,g the data along the shift registers. SSDA
Serial data transmission is controlled by the CTS (clear to send) input CLOCK is gated atM2-3 by ihe action ofM3-12 to en..sure that the first
totheSSDA. Transmissionisinhibitedby CTS atLogic-1,andenabled Rx data is sampled before it is lost by the first bit-shift. 24 clock pulses
are counted by M4, allowing 24 bits to be shifted before resetting the
when CTS is set to Logic-0 by the CPU address-code signal
Analog Interface SW.rt latch M2-l l (TP3) to Logic-1. (Refer to
AN1/F STRT. The first serial bit is transmitted by the negative 6.16 Wweform!).
transition of the first full positiv_e Tx clock pulse (256 kHz) after CTS
has been set to Logic-0. CTS is held at Logic-0 by the
ANI/F STRTlatch for the duration of 24 full Tx clock pulses, thus
enabling the serial shift transmission of the 24 data bits from the Tx (Circuit 113-3)
Data FIFO in the SSDA.
Tne following paragraphs desc1ibe the action of t.he SSDA clock
generator circuitry.

The action of the SSDA clock generator is ii,itiated the command

Serial data is received by the SSDA, controlled by the DCD (dataca__rrier AJ\lI/F STRT from the CPU. This occurs after the parallel data has
been loaded into the SSDA transmit registers from the data bus. The
detect) level a..nd clocked by Rx CLOCK. DCD is common to the
Logic-0pulseof AJ'\JI/F STRT setsflip-flopM2-10/ll togiveaLogic-
transmit control CTS so that tr~1nission to, and reception from the
serial/parallel shift registers is synchronous. Both Rx CLOCK and Tx 0 at TP3 which then:
CLOCK have the same frequency but Rx CLOCK is inverted with
respect to the latter. The first bit arriving at its Rx DATA input is Sets the D input level of flip-flop M3-5
clocked into the SSDA Receive FIFO register on the positive transition Removes 'SET' to enable shift register M3 at M3-6 and M3-8
of the first full Rx clock after DCD is set to Logic-0. Removes 'RESET' to enable counters M4 at M4-7 and M4-15.
(Refer to Fig. 6.16 Waveforms A and C).

At the next rising edge of the inverted 256 kHz (Rx CLOCK) from
M43-8 after AJ\)J[/F STRT, the shift register M3 is clocked but only
M3-l 'Q' output changes state to Logic-0. This is applied to the SSDA
Serial data is transmitted and received ii, bursts of 24 data bits. 'Three
CTS a,,d DCD inputs, thus releasing the inhibits on the SSDA
clocks are used to time the flow of bits, ensuring that:
transmit andreceiveregisters. (Refer to Fig. 6.16 Waveforms D and E).

Data has time to settle before being clocked along the shift
At the next (second) rising edge of the clock to M3, M3-12 changes to
registers.
Logic-I. This allows NAND M2-3 to pass 256 kHz clock pulses via
The first Rx data sample is taken before it is lost by the first bit-shift. buffer MS-12 to the Reference Divider Assembly to shift the serial data
along the anal.og-control md status registers. (Refer to Fig. 6.16
Subsequent Rx data has time to settle before being sampled by the
l'llfnvc,i',c,r?;,ieD, F
SSDA.
Exactly 24 bits are shifted in each burst. The 2.56 kHz dock at NAJ'\JD M2-3 is applied to the 4-bit up-counter
dock input at M4-1, each rising edge causing the counter to increment
by l.

6-24
The divide-by-Hi output M4-6 is applied to enable M4 at its M4-10 c. 'fhe at TP3 resets the up-countern M4 causing:
input ; the falling edge at count-16 and incrementing the
li. the counteroutputs to fall to Logic-0, iriJtlbitL'lg furthercomting;
second counterto produce, atM4-11, aLogic-l c1°t,::,ut. Later, a: c::,m,:-
24, M4-6 changes again to and tog"Lhe~· ·.':ifuM4-ll ::,1,~x:
.,. l-.TPJ'ID IvI2-5 to rise to Logic-t re-setting flip-flop M2-12 to
a Logic-0 from NftJ\TD .1VI2--", causing ::,,;; 7:·,,owi.-ig aci,:_,:.:",c:
prepare for fr1e next i-\J\TIJF STRT (Refer to 6.16
a. Flip-flop M2-12 is reset to give at 'TP3. r,v,c1w·ms JP BP C, E !2?!.d

b. The Logic-1 at TP3 sets shift register M3 to give:

i. al M3-l, thus inhioiting DC:= s.r,6 CfS;

H. ~,,,c-µ• 8[ lvB-12, Ul06UilH); NAND j•;=2-3 s_,-id thus ~,n.-,,,,.,-,c·
any further SSDA clocks.
r=-= ~~

I A il. 1\I I/ F STRT

1'12-fl ljl
~----------------------------------

[
END COUNT
M2-U12

1\1\! I/ F LATCH\J
t
I
---------------------------M

~----------------------------------'
D 256 [d-iz (INV)
H 3 · 3 / 11
I

·- -----·---····-rt I

F SSOA CLOCK
ENABLE
MZ -1

G Tic CLOCK

H h DATA

SSDA [Lorn
M 2-3
Shift 1 2 3 23 24

Rl1 DATA R)j DATA

BIT CD
Sample

Ru CLOCK

6-25
 The control and status bits in the registers are then circulated three
furlher bursts of clock pulses, until the CPU h21S re~d both the news tatus
data and all fue control data that were written by the strobe. Verification
Serial control data transmitted from ithe SSDA (Analog Interface that Lhe rel.umed control data is identical to tlie trl!lll§mitted data, ends
Assembly), togeitherwiLh theircontml signals (SSDA strobe and SSDA the transfer.
clock), enter the Reference Divider AssemblyviatheMother A\ssembly.
ff after three attempts, the returned data does not match the transmitted
The data and signals cross the isolation barrier data; the CPU omits to re-trigger monostable MlO in the Reference
M6, M7 and M8 into guard.
Divider Assembly. MH! time§ out and allows the signal BARK DEL
Serial control and scams dara is rn1:1.Lmed out of guard to the SSDA to go to Uli>aU•AmCE; 'tri-stating' the
receiver via ,.u-,~uwuJ1 Ml. registers M27, M25, M31, M19, M30 and Ml5.

The nominal logic levels (Logic-1 = +5V, Logic-0 = OV) used in the
out-guard SSDA circuits, are offset at the opto-isolator outputs to: The data latched in M27, M25, M31, Ml 9, M30 lllld M15 outputs
control the operation of the Analog crrcuitry. The effects are therefore
Logic-1 = -lOV Logic-0 = -15V
described in the sub-sections :relevant to their destinations.
a_nd level-shifted for the in-guard circuitry to:
As this is a multi-purpose converter, designed for use in more than one
Logic-l=OV Logic-0 = -15V model of instrument, some of the control and status lines are not used.

6.tt5.2 Ser!©1Mlnl/P@la'©1!!®i 0LJ1t C©lnlirr©! 1iJJ©Jl~

0 0

C©lnl'll'@u[©rnl

Six 8-bit serial shift registers M27, M25, M31, M19, M30 and IVH5
each have latchable parallel outputs. Their serial "D" inputs and "Q's"
outputs are cascaded to form a single 48-bit serial shift register. M27
receives 'serial data in' from MS via the level-shifti.11.g buffer M36-4,
and M15 passes serial data on to the Parallel-in/Serial-out Status-Data
conveners.

Two 8-bit serial shlftregistern M18 and M22 each have parallel inputs.
M18 serial "Ds" input accepts serial data fromM15; Ml8 output
is cascaded to M22 "Ds" ii11p1.1t; a,,dM22 output delivers SERIAL
DATA OUT to buffer Mll-11 and back to the SSDA via Ml opto-
isolator.
Ml8 and M22 thus form a 16-bh serial shift register whose 16
inputs' states can be inserted into the serfaJ data string.

The serial data, organized into five blocks of three bytes (Refer to Section
6.4.2.2), is accompanied by synchronized bursts of 24 clocks. The
output from opto-coupler M7 is buffered via level-shifter M36-2 and
then inverted at M 14-6. The timing of the clock edges allows
all bits of serial data (distributed throughout the shin registers) to
stabilize before being clocked on.
After the CPU h81S generated ,wo bursts of data ilnd clock pulses, !he
serial control data has shifted into !he correct positions in oontrol
registers M27, M25, M31, Ml 9, M30 and Ml5. So before the third
burst of three bytes, the SSDA produces a strobe which writes the
control data into their parallel outputs. Simultaneously, the strobe also
fills the 16-bit serial register of M18 and M22 with the status data
present on their parallel inpms.
'When the strobe ends, further transfers between serial and
registers are disabled. The new oontrol data remains fai:ched in the
parallel control registers, a..nd filie new swtus data fa in the serial starus
register ready for shifting to the SSDA Rx DATA register through
guard.

6-26
6"'406 SAFETY MONITOR (WATCHDOG) 6.4.1 WATCHDOG CIRCUITRY
(Fig.6.17)
6.4.7.1 Orut~Gualf'd Wa1lchdog
6.4.6.1 Watchdog Signals
(Circuit Diagrams 430648 Pages 11.3-1 to 11.34 and
The watchdog circuits continuously monito:rthe CPU/SSDA functional 430652 Pages 11.4-1 to 11.4-6)
process. Detection of a processor malfunction by the watchdog :results
The CPU verifies the validity of each serial-interface transfer by giving
in the following actions:
the SSDA an instruction to generate a 'Watchdog Enable' trigger. This
a. BARK This signal: W.DOG ENABLE SEl' pulse (M44-7 on page 11.3-3), triggers
t removes the drive from the primary of the High Voltage (lkV) watchdog-enabling monostable M29-1 l (page 11.3-1 ).
transformer, W.DOG ENABLE SEl' Lriggering :mdretriggeringextends thenatural
it disables the 400V Power Supply, and (470ms) unstable state of M29 indefinitely. Unless the retriggers fail,
iii. disconnects the Current Assembly output from the instrument
the M29-9 output ( W.DOG ENABLE) remains at Logic-0. Absence
output terminals.
of W.DOG ENABLE SET retriggers, for longer than 470rns, allows
b. BARK. This is returned as a status bit to the CPU via the SSDA M29-9 to restabilize to Logic-1.
to signal a failure.
W.DOG ENABLE is inverted at M43-3 and applied to NAND gate
c. BARKDELAYED. Thisoccurs47msafterBARKanddisconnects M46-12 (page 11.3-4 ).
the AC Voltage Pow0r and Sense circuits from the instrument
output terminals. During each successful processor cycle, the CPU addresses M5 l-9
(Digital Assembly page 11.2-2). The resulting low active pulses at 8rns
dl. BARK DELAYED. This signal disables the registers of the intervals are inverted, and gated with WRT STRB to generate the
serial/parallel data converters. active-low signal W.DOG atM49-ll.

W.DOG travels via the Mother Assembly to the Analog Interface

The watchdog outputs are manipulated by the power-cm reset circuits Assembly to be gated with the W.DOG ENABLE signal at NAND
as follows: M46 (page 11.3-4). The resulting signal atM46-13, W.DOG, consists
of positive-going pulses at 8ms intervals when the CPU/SSDA system
BARK DELAYED and BARK DELAYED are held active for is working normally, or a Logic-1 level if the SSDA fails.
80ms from power-on and then are allowed revert to the inactive The W.DOG signal travels via the Mother Assembly to be passed into
state only after two SSDA strobes have been detected. guaYd on the Reference Divider Assembly (Opto-coupler M9 on page
BARK is forced active until CPU/SSDA functioning has been 11.4-5).
verified; the latter must occur within 470ms of power-on.

BARK is held inactive for 470ms from power-on, after which it

provides a FAIL message to the CPU.

6.4.6.3 Effects after 'Reset'

Operation of the Reset control on the front panel provides a further
lOOms period for the CPU/SSDA functional process to settle, during
which time the watchdog circuits must verify correct functioning
before their outputs are reset.

6.4.6.4 Watchdog Trip Action

The watchdog is tripped if the system fails to transmit analog-control
updates to the analog circuitry. The updates are of two types:
Transferof 'Output value' data via the Analog Interface comparators,
Transfer of analog switching data via the SSDA every 40ms.
The CPU generates pulses at 8ms intervals to verify that the correct
output value has been latched into the Analog Interface comparators.
These pulses are allowed to pass into guard only if the SSDA verifies
that the analog switching data is being transferred normally at 40ms
intervals. Once in guard, the pulses prevent the watchdog flip-flops
from generating their four BARK output signals, by re-triggering a
monostable (Ml0-4: Hlms) to hold it in its 1.1TIStable state.
If two or more pulses are missing, MlO releases the hold, mdl the
watchdog flip-flops 'Bark', octivating the safety circuitry. They will be
missing if the output value comparators are incorrectly updated; if the
SSDA fails to generate 'Transmit' pulses for a period exceeding 470ms;
or if the CPU crashes.
6-27
6.4.7.2 1111l·Guard 6.'1!.7.3 !Poweli'~Oii Reset
(Circuit Diagra.m 430652 Page 11.4-5) (Circuit Diagram 430652 Page 11.4-5)
NOTE: When power is first the build-up of the 15V supply forces shift
The operating levels of Lhe in-guard CMOS circuits are negatively register M37 Set to Logic-0, but its Reset inputs are held at
displaced as follows (nominal voltages): Logic-1 by the charging action
Opto-coupler output circuits So M37 is forced into reset state for about 80ms:
Logic-1: -lOVDC -lSVDC M37-2 imposes Logic-1 at M13-8 Set
Digital CMOS circuits M37-l at Logic-0 holds MlO inactive at Ml0-3, Lhus preventing
random triggering at Ml0-4 from erratic W.DOG as the
Logic-1: OV -15VDC
SSDA/CPU functions start up. output Ml 0-7 holds lVH3-6 Set
Level-shifter M36 carries out the interfacii,g between these two input at Logic-1.
levels.
Also, the Reset inputs Ml3-4 and Ml3-10 are held at Logic-1 for a
The 'W .DOG' signal is opto-coupled into guard by M9. During normal period of 470ms from power-on by the sign3J FP RST, generated by
operation: the W.DOG in-guard positive-going pulses, at 8ms L,tervals, the power-on reset action of M53 on the Digital Assembly.
keep re-triggering the monostable Ml 0-4- to give a continuous Logic- (page 11.2-2).
0 at MlO-7. The l 8ms unstable state of MIO allows for one pulse to
be absent, but if two or more pulses are missing, MIO resets, tald,,g Therefore, the Set/Reset inputs Ml3-8/Ml3-10, initially both atLogic-
Ml0-7 to Logic-1. 1, force Ml3-13 output to Logic-1 to give active BARK DELAYED
and BARK DELAYED oulputs.
The logic level fromMl0-7 is connected directly to the setinputof flip-
flop M13-6. With the reset input to M13-4 held at Logic-0 during The Set/ResetinputsM13-6 andM13-4, also initially atLogic-1, force:
normal operation, the output conditions of Ml3-1 and Ml3-2 are as
Ml3-l to Logic-I BARK), and
follows:
M13-2 to Logic-1 (Non-active BARK).
Set input M13-6 = Logic-0 (no fault);
Ml3-l (Q) = Logic-0 - BARK not active The output states of M3 7 (M3 7 -1 = Lo gic-0, M3 7-2 =Lo gic-1) remain
unchanged after the 80ms time constant at M37 Reset inputs, but then
Ml3-2 (Q) = Logic-1 - BARK not active
M37-ll is free to be triggered from the SSDA strobe input Two strobe
Set input Ml3-6 = Logic-1 (malfunction); inputsmustoccurbeforeM37-l clocks toLogic-1 andM37-2 to Logic-
Ml3-l (Q) = Logic-1 -BARK active 0. M13-13 now changes to '-"-'.i,;1,,-iu, making BAR.K DELAYED and
Ml3-2 (Q) = Logic-0 - BARK active BARK DELAYED inactive, and the inhibit is removed from Ml0-3.
The action of Ml3-2 changing to Logic-0 triggers the monostable 111.e outputs M13-l andM13-2 remain unchanged until Ml0-7 falls to
Ml0-11 which has a relaxation time of 47ms. After Ml0-9 Logic-0 by the clocking action of pulses on the W.OOG input. This
output clocks flip-flopMB-111:0 give the comm:mdBARK DEL.from mustoccm beforeM13-4ret:urns to Logic-0 (at470ms from power-on)
M13-13 and BARK DEL from inverter Ml4-12. for BARK to be made inactive, otherwise BARK remains active and
BARK is set to LJ.J•;,:11c-jl,, producing a fail status bit which is passed to
the CPU.

6-28
6\.4, 7 ,4 Maifm1ct1on
(Fig 6.17)
Any malfu_nction which introduces one of the following conditions will
cause the watchdog to bark:
a, CPU WRT STRB failli at Logic-0.
b, MS l on Lhe Digital Assembly does not receive the address to
activate M51-9.

c, Failure of transmission of bursts of the W.DOG ENABLE SET

pulses from the SSDA to M29 (fhe SSDA is not transferring serial
data).
di, The SSDA Strobe is not triggering M37.
e, W.DOG pulses are not triggering MIO.
As well as these failures the CPU is informed, via SSDA Status byte
transfer, of certain analog malfunctions. Subsequent CPU action can
include deliberate activation of the watchdog by omitting to address
M5 l as in (b) above.

6.4.7.5 Reset
Once the watchdog has 'Barked' it can be reset, if the malfunction has
cleared, by pressing the Reset control on the front panel.

The Reset input to the watchdog circuit, FP RST, is active for lOOms
after pressing the Reset key. (M53-9 on Digital Assembly page 11.2-
2). During this period, the Reset inputs atM13-4 and M13-10 are held
at Logic-1, allowing the correct pulse inputs from the processor and
SSDA to hold M13-6 at Logic-0, and to reset BARK DEL at M13-13
to Logic-0. The watchdog will not reset if the malfunction persists.

6-29
 DIGITAL PCB ASSEMBLY ANALOG INTERFACE ASSEMBLY

- --~
" CPU- - - k T R B J
MEMORY
ADDRESS
DECODING

M51

1 = FAULT CONDITION

I ENABLE PULSES

(s U R ~ L S E S
\ FOR EACH DATA
~-~-~ TRANSMIT
SSDA MONO
IRQ 7 W. DOG ENBL SET 11 4.70ms - 9 W DOG ENBL W DOG ENBL
B a ~-'-'--'--'----=-...c-----1 /
l
M29
W DOG
s
J3 SSDA STRB J3
--- --- --- --- - - -- -- -- --- --- --- - - - - - - - - - - -
J4 104 REFEREN1~ DIVIDER PCB ASSY J4 9'/

OPTO - OPTO - ]
COUPLER COUPLER ___________ _
/
--- ------ - - - - - - --- --- - ----------
~ IN-GUARD
I ONE PULSE PER M9
I M6 DATA TRANSFER
I
I lhs-u- 4
I ~ :Z- PULSE COUNTER~ 'o' AT PON I INHIBITS 18 ms MONO l ~ MONO
I 18ms
8 6 ',' AFTER 80m, • 2 STROBE PULSES
I
I 9 D s s
: STROBE
,,. FLIP FLOP
M37 M37
I 14 3 2 1· = FAULT CONDITION Q 1 BARf\
I CLK ci
~
CLK R . R 'o'=RE-TRIGGERED FLIP FLOP
I 10 4 ---r----:':_:'___ 18'!1s PEPIOD
'j' AT PON M13
I ~
'o' AFTER 80 ms 3 -~2,__,.__ _ _ _ _ _ _ _ _ _ _ _---=B~A~RK~
I _j1s ms k CLK R Q
I l.
8
I 9 s
~s
I FROM P ON
'o' = NORMAL RUNNING MONO
I 1 FOR 470ms FROM PON 1' FLIP FLOP
( 'o' AFTER 80ms 11
8
4 7ms
M13
I 1 FOR 100 ms FROM M10 - 9
FROM P ON l 11
I SAFETY RESET Q CLK R
OPT0-1
COUPLEIR
M4 L - - - - - - - - - - - - - - - - - - - - - - ~ - - - - - - - - - - - - - - - - - - - - - - - - - - ® - - - - - - - - - - - - 1 1(
J4 11S
I
FIG, 6.17 WATCHDOG CIRCUITRY SIMPLIFIED BLOCK DIAGJ'?AM
O

6-29
 The ovt-gl' ard -:irc11i tr:'l aerr:rib<cd in this sertfor perfon,.. sill" fo 1hwing
functions:

Recei'-.res ;_.end ~atch-:~s (i.e c; ~mLnde.J outpul -::.,ra.l 1 ,3: f. \_;n1 ·~1e ~~p1; h-1
the form cf a 25-bit wri,d,
:3u11,3rec
Dc:ta 8us
Gcn<crnH.is a CGHtin:uous 13-b;tup-wun.d'ro,,1 the 1.(;2~-r,,H;r,,1fas,er
C~c:ick (3m:; ccunt :ye::).

Compares the 13-bit count ·with the 13 m-::ist-,ignlfic,,-atbits c-rth"

25-bit word, g<;;ner at.in.g 'S e1. m1ci 'Reset' pulses. 1";1es"' an, ,rnr.,;.fen ed
inEo gL1ard to Lrig3er J1e ·Mc~t Signlilca.f:l JET sv', ~tch h1 1he
Reference Divide

Compares the 12 mnst-significant bii.S 0:,_ the~ cm:.Ht with Lhe 12

.,~j
le:::i:;t-[ign1fica..nt b: :B of the 25-bit \·,,ore\ ge:u..--;r:;r'..ng ·set' .::t:nc, "Rr-:\:2t'

~::-'r·=~Il -~· l pvlses. Thes~ are tr?nsforred int'l pia:rrl to 'Iig,er the 'Lci 1.- 0

Significant' JFET switch in ,he R.efcrenc::! Divider.

,.r.\l~es
IEm!?er ,_,,., u'l;;grnter • 12 unos
J alllfi\-.'Bifm

~-' 'lt:Z:......_~~1,;,:
;',~"-'.7-!!a"'7.'~

•
,~"!JG!Ji

The in-guard circuitry performs the following fulctions:

Pr;wides a.Master Reforence Voltage ('.:'.0£i) ,,-.-1-•icr. is ch'.ljJp<cu by

ths 'J\V:ost Significant' JFET switch 1.-J generate c: sc;_uaJ"e-wa e,
whose M1.1rk/Period rn.tb is concrolled by the 13 most-signiLcan,:
bits of the 25-bit wo:d. A 7-;_Jole Bessel tiite: smooths the sq0Jare-
wave ,o provide a DC voltage, wh;ise 1aL:e vcries di::ectl/ as C:1e
Ma:rk/Peri::1d ratio ,J>f Llie l\.1SB sqcare-wa ,e. 0

Provides a Iluffered Referer,ce Voitage (8-6'..\V) which is c.acJJpecl

the 'Least-Significant' :FE~ sv,:tch to 5ent'.tate a ss11arr~.. -vv;::.:':e,
whose Mz..rk/Period ratio is contrdle,:I. l:Jy :.he ~2 hast-sigr.~ficrn.t
bits of tlle 25-bL word. A 3-pole Bessel filter smooths llh~ square-
wave i:O provide a DC vo:i.,age, whose value varies directly 2-;; u:1e
Mark/Period :,:atic of Ltie LSB squc:re-cvave.

Cor..ditioru; the two DC voltages produ,;ed by ,Ji.e 'Sessel fi,;:ers,

delivering them via fuil 4-wir1c. coru:,eclio11:, to oe sw.n':ne,;:1 on eitl-.e!·
the DC assem'Jly (for DC euti:atse:ec,ioTIE; or onCeA::
(for AC o'.ltp11ts) ~s a DC 'Werking Reference'.
Bipoia7
:SW!ia:-M11~
T.1evalueofthis reference voltage is a.;c'.lrately prnpor~~cn&.l '.o ,:J1e
vclue dern:md~ the CPU's 25-bit 1,ord, Fc·r. [:: o-.:4J1J. .s, y,-_w_
0

pDlMity changeo"er switchLng, it can have ·,-aluef bet'.~'t'.e', -:-20V

Offs®t Bias zmd -2CV (indud.ing zero); but as a reference for AC o'..ltpu,s, its
{->::l)Amplifigr value lies between +G.126V &."ld +2,79V.

For AC cu.:puts only. the iI1-guard circiilitry digit~liy generates a

stepped AC reference voltage whose peak vcilue is u;ual :o th_c; DC
VVorking Ref'oren-:e Voltage. This ~iv~s t~e s.,ns,,./R.~fo,-ence
Comparator (described in sub-section 9.9) ilie comid,::·abb
aJvar,.:ag<.: of oorr.:panng ,-.,C Jense aisairn;. /Ji.;.__ Rc,·ere,1.cc.
V,"ofe ·~on-:lJar:d ,·ii:h DC, srn;Jl :)c Jf-,;.";!s --,-01_ 1;-J. j" ,3.g:,c'fy ml
le0d to 'DC n,-rr:;_o,rer' '!ITO:'"s). T,1e AC wa"':!il'rrn i~ ccnscrP<::ierl in
ten steps by a digitally controlled-switching ,1etworI:, It ha: bec!.1
g.ven the mir.~e 'Quas:-Si.newave'.

--------------------------------------------------------------------- - - - - - - - - - - - - - - - - - ----------- -- ----------- -

5-30
6"5" 1 PRECISION DIVIDER TheMSB and LSB comparators translate this binary data into 'RESET'
pulses, whose time relationships to the 'SET' pulses are established by
COMPARATORS the value of their binary words.
(Circuit Diagram No. 430648 Pages 113-1 to 113-4)

15"5" 1. 1 Geirneir@I lft:5,1 .3 13a1Bli1l{MS9)

(Figs. 6.18 and 6.19) (Circuit DiagraniNo. 430648 Page 11.3-2)

The comparators are designed as a means of translating a binary word The 13 binaxy outputs of the up-counter scan the 13 Exclusive-OR
into the accurately defined Mark/Period ratio of a square-wave" The elements of the MSB Comparator. With the least-significant bit at
ratio of the square-wave's average value to its peak value subsequently 512kHz, and the most-significant at 125Hz, the 8ms scan time thus
defines the division ratio applied to the Master Reference, and must be divides into 8192 time elements, each of 977ns.
adjustable at high resolution.
Each time element has a unique binary code, incrementing by one bit
The required decimal resolution translates into a 25-bit binary word, on its predecessor. When this coincides with the bit-pattern set in the
each bit needing to exert control of the division ratio. A single data register, the comparator provides an output pulse to the MSB sync
comparator of this length would require more than 30 million clocks to
logic. Thelattergeneratesresetpulses RSTl and RST2 insynchronism
scan, which at sensible clock frequencies would occupy several seconds.
with the signal SYNCl (2.048MHz).
To filter out the resultant chopping frequency would require large and
expensive components, and force unrealistic operational time constraints.

In the Datron Precision Divider, the 25-bit word is split into two parts 6.5.1.4 12-Bit (LSB) Comparator
(13 most-significant bits - MSB; 12 least-significant bits - LSB), (Circuit Diagram No. 430648 Page 11.3-1)
allowing a scan-cycling frequency as high as 125Hz to be achieved"
This functions in the same manner as the MSB comparator, but
scarm.ing only twelve bits over the same 8ms counting period, thus
Both MSB and LSB comparators are scanned concurrently by the same
accommodating 4096 time elements ofl 954ns for each binary increment.
13-bit counter, forming two separate square-waves" These act on two
separate reference divider switches and filters to generate separate DC
SYNC2 pulses, generated in the MSB Sync Logic circuitry at half the
voltages which are then recombined, giving the required resolution.
rate of SYNCl, synchronize the RST3 output from the LSB Sync
In summary, 1he two comparators translate information from 1he CPU Logic.
into time-related pulses which control mark/period switching in the
reference divider. One comparator operates on the thirteen most-
significant bits of CPU data; the other deals with the twelve least- fL5L2 COMPARATOR CiRCIUn
significant bits. The comparators operate concurrently, cycling
continuously at 125Hz, taking 8ms per full count 15.5.2.1 Input Data latches
(Circuit Diagram 430648 Pages 11.3-1 and 113-2)
At the start of each 8ms counting period, each comparator generates a
SET pulse to start its reference divider 'Mark' element Then after The input buffered dara latches M3 l to M34 and M37 to M39 receive
precisely-measured delay times, each generates a RESJET pulse to 27 data bits in four bytes from the buffered data bus. Latches are
terminate the 'Mark', and start the 'Space'. At each 8ms full-count, the selected by signals REF rnv l, 2, 3 or 4 from the memory address
clock resets and continues up-counting from zero. decoding on the digital pcb. Data is clocked to the 'Q' outputs of the
latches on the positive-going edge of WRT STRB.
6.5.1.2 Comparator Operation Data from the input latches is used as follows:
(Fig. 6.18)
25 bits form a data word to the comparator registers M47, M48, M49
The MSB and LSB Data Buffers are periodically loaded and latched
(part), M5 l and M52. The remaining 3 bits from the data latches are
with binary 'Demanded Output Value' data under the control of the
used for separate functions:
CPU.
2, M34-5 triggers monostableM29 (part), whose Q output is inverted
At the end of each comparator counting cycle, the 13-bit
and buffered to provide the control UPD (OG) used in the relay
counter FULL COUNT output enables the generation of set pulses
drive logic for analog switching.
SETl , SET2 and SET3 by the MSB and LSB 'Sync Logic' circuits.
b, M34-4 (EXT FREQ SEL) selects between the internal 16kHz
FULL COUNT also generates the LOAD command. This writes the synchronizing frequency and the 16kHz output from the External
data, currently latched in the buffers, into working data latches which Frequency Input Buffer.
form the 13-bitand 12-bitDataRegisters, updating the earlier 'Demanded
Output Value' which is resident in the comparator.
~. M34-3 (BEEP) triggers ilie Beeper monostable M55, which is
activated to draw atltention to display messages"

6-31
6.5.2.2 13l l!:m Cour!it~rr
0

(Circuit Diagram, 430648 Page 113-2)

(Refer to 6-20 for Waveforms)

The counter consists oftruree 4-bit binru-y counters MIS. M16.Ml 7 ai,d M42 output is at 512kHz. clocking of M 15 occurs on the rising edge
/_',E
J-K flip flop M42 (half dual package). The squarewave outputs from of alternate 1.024MHz clocks. thus giving outputs of 256, 128. 64 and
the counter are on 13 binru-y-coded lines. the first (least-significant) 32kHz squarewaves from M15.
being a 512kHz sqmrrewave. the others successively dividedLnfrequency
to the most significant output of 125Ffa. Counter Ml6 is enabled the carry output from M15 together with
512J<-J-Iz from M42 at the count-enable pins M16-10 and Ml6-7
Bit 1 is provided by J-K flip flop M42. which on each falling respectively, thus outputs of 16. 8. 4 and 2kHz squarewaves
512kHz Q and Q outputs. These fromM16.
edge of the 1.024MHz clock to
outputs are used as follows:
Counter Ml 7 functions in a similar mru:mer to give outputs of lkHz,
500. 250 and 125Hz squarewaves.
a. The two complementru-y outputs together provide the least-
significant input to the 13-bit comparator;
The 2µs-long 'Carry' output from Ml 7 occurs at the end of the 125Hz
output \Vhen all counter oulputs a.re at Logic-I. The carry output is
b. The Q output controls the counting rate ofM 15 0 synchronizes Ml 6
NAl'illed with M42Q output to give the lµs-long logic command
and Ml 7. and is used in the gatLng of FULL COUNT.
FULL COUNT. The counting cycle resets and continues. starting
f-rom bit 1.
Counters Iv'!l5. M16 a..ndMl 7 a.re cascaded as a 12-bitcounter and are
synchronously clocked by the 1.024MHz. Ml5 ca.11 count when
its count-enable inputM15-7 is setto Logic-1 by the Q outputofM42.

977ns

BINARY COUNT 8188 I 8189 B190 8191

1'024MHz

1·024MHz

MU-11
512 kHz

M1S-14
ZS6kHz

M17-11
12SkHz

M17-1S
CARRY

M6-11
FULL COUNT

6-32
lfia5.2.3 13-Blt >SS"1[?"1ll&"lf Arc;Uioll1l
(Circuit Diagrom 430648 11.3-2)

The 13-bit comparator provides a output at TP12 whenever a for the 4-byte tr2111Bfer could allow the latches to contai.., spurious data
coincidence occurs between the following two sets of data: until they were fully loaded, and an inaccurate paril-y could be registered
with the counter still running. The counter must not be interrupted, as
a. Data set in registers M47, M48 and M49-l;
its fullcountdefmes the 'period' ofthemark/periodratioused to control
b. Data from 13-bit counter M42, Ml5, Ml6 and Ml 7.
the division of the reference voltage. It is therefore necessary to reduce
the loading time, which is achieved by double-latching the data.
Twelve exclusive-OR elements M2S, M26, M27 and three NOR gates
of M12 are used to detect a coincidence. The data in the registers is
When the CPU has data to load into the input data latches, it first
preset by the CPU, while that presented by the 13-bit counter cycles
m,,,,.,,,,,c,a,tP~ the comparator by enabling buffers M45 using the signal
through every binary combination possible on 13 lines.
REF Dl[V RD. The REF BUSY signal atLogic-1 (M45-3) indicates
Two coincident inputs to an exclusive-OR gate provide a Logic-0 to to the CPU that enough time is available to load the latches (at least
the 12-input NOR gates M24fM[23; full coincidence in bits 2 to 13 is 125µs remain before the LOAD pulse occurs). If the REF BUSY
shown by a Logic-0 at NAND Ml3-6. Coincidence at bit 1 is shown signal is at Logic-0, the CPU waits until it returns to Logic-1 again.
by Logic-0 at Ml2-13 and Ml2-4 (Ml2 acting as an exclusive-OR
When the REF BUSY signal is at Logic-1, the CPU loads the data by
OIIJI P!Jl P!INS
first carrying out four transfers of one byte each into the seven quad
M12 !!IJPUl P!NS
buffer latches M31 to M34, and M37 to M39. Each byte's destination
6 H !ll/12 .II 13 is addressed by one of the chip-select signals REF.DIV.l to
0 1 0 0 0 REF.DIV.4, which enables the selected buffer latches. The data is
0 1 1 1 0 } Ooly 4 iop"1 latched by the WRT STRB signal.
combinations
1 0 0 0 1 available
1 0 1 0 0 Once the full 25-bit word has been latched into the buffers, it is
available as a single word at the data inputs of the comparator latches
gate) as follows: M47, M48, M49, M51 and M52. The CPU again interrogates the
A BUSY signal is generated by the comparator at NAI® MS0-13 comparator by RIEF DIV RD , and five of the elements of M45 buffer
(TP2) when the 13-bit counter approaches full count Bits 8 to 13 are the five most-significant data bits back to the CPU. ff parity with the
at Lo gic-1 for the period of l 2Sµs preceding the end of the counter cycle transmitted data is confirmed, the CPU takes no oction. When the
(see Fig. 6-21). The BUSY level is applied to the M49 D-input at pin counter times out, the FULL COUNT signal is clocked through to
9 and is synchronously clocked through as the signal REF BUSY to M14-6 by S'l{NC2 as the LOAD signal, !lld the new data is transferred
buffer M45-2 by 1.024MHz. into the comparator latches.

As described earlier, the demanded output value is defined by ithe CPU If the data latched in the buffers is not as transmitted, the CPU initiates
to a resolution of 25 bits, contained in four data bytes. The time needed the IF AIL 4 message procedure to ithe operator.

8 ms

----------------------
I= ~ _ :s= -= ::r
=1~

1-024 MHz
----------------Wlflflr-----4
6-33
 (Circuit Diagram.430648 Page 11.3-2) (Refer to Fig. 6.22/or Waveforr,is)

This circuit, Ml4, M6, M7 a_n.d M8, provides the following signals: before S.E'fl, is obtained by gating Lhe FULL COUNT with
SYNC 2, LOAD, SE'fl , SET2, RS'Tl and RST2. 1.024MHz at NOR M7-10 am.cl then N~IJ"JD- gating at M8-10 with
SY.NO.
SYNC 2 is v,,,.u~,.,~u NAND gating 1.024MHz and SYNCl to
a synchronizing pulse at half the rate of SY.NCL Reset pulse genera.tion ( see level at
TP12. This can occur at 0ny one of the 8192 counts of the 13-
The LOAD pulse enables the 13-bi.t compaw.tor bit counter, its actu8l time slot d,,-pe:ndJmg count at "Vhich
generated at Ml4-6 at the end of l:he counter's full-count ouiput. the coincidence OCCUIS"
FULL COUNT sets the D input Ml4-2 s.nd the level is clodced,
The coincidence level at TP12 is NAJ\JD a, M6-8; :M6-10 being
inverted, from Ml4-6 by the next two pulses that occur. for all binary counts except 8191. The JLA>;;ic,-')U at M6-8 is
at M7-1 with 1.024 MHz, tlm is then used to select the next
The inverse of LOAD is used to time the pulse SETl by
SYNCl pulse via NAND M8-4 to provide the pulse RST1 .
atM7 ..L! with 1. 024MHz.
The coincidence level at TP12 is used to set the D at flip-flop
to provide SETl from M8-L The pulse SET2, which occurs 977ns

SYN( 1

To 70ns

~1
I
===========~============~~=====
FULL [OUl'H

============6=======

i
,?==============~~==~=====
Riff BUSY
-~ ========='cJ I
-~
6-34
M14-12. This level is clocked to NAND M6-5 by !he next SYNC 2 RSTl a__nd RST2 are generated with the same relationship in time to
pulse. NAl\JD input M6-4 is at Logic-1 except when LOA.Dis active, the comparator coincidence when the latter occurs in a__ny binary count
lhusM14-9 output is inverted atM6-6 to be NOR-gated with 1.024MHz time slot from Oto 8190 (inclusive).
atM7-13. This is then used to seloctthenextSYNCl pulseviaNAND
MS-10 to provide the pulse RST2. Notel:hatasthecomparatorwordincrementsinvalue, RSTl and RST2
increment in time after ffiI and SET2, which remain stationary
The pulse-timing example given in Fig.6.23 shows the generation of with respect to FULL COUNT and LOAD. RST1 and RST2 are
RSTl and RST2 when coincidence occurs in the comparator at inhibited when coincidence occurs at binary count 8191 to allow for the
binary count= 0 (wavefonru; in continuous lines). re-loading of the input :registers at l:he end of the counter cycle. The
inhibit is performed by the level of FULL COUNT going to Logic-0
Coincidence occuring at binary count 1 causes RSTl and RST2 to
and NAND M6-10, preventing RSTl being generated; and by flip-
increment in time by 977ns withrespoct to the SETI and SET2 pulses flop M14-5 output going to Logic-0 for the period of the load pulse,
(waveforms in broken lines).
inhibiting RST2 .

SVM( 1

LOAD

---- -~--
I
r17-1 --1-----r-:~: .~ 1
I !
I L~--------L!
u I tJ

! 1·11,:11--~----.,
--------------~-....i -- -- - --:-- ~
I
L
F0-1)
---.. r----.,I
--i-----· 1---
I

u ,.
1---------~--tJ
SHNl!.RY COU114 T
. . a,~: •O I ol I
NE>f COUN7!R -
OCLE

FIG.

6-35
 (Circuit Diagrani 430648 Page 113-1) (Refer to Fig. 6.24 for Waveforms)

This functions in an identical manner to the 13-bitcomparatorpreviously The tirning of SET3 is controlled by !he FULL COUNT pulse from
described. 'Twelve exclusive-OR gates, Ml9, M20 and M21, receive the 13-bit counter. The inverted FULL COUNT at M43-6 is gated
the 12-bit bi11ary output from the common counter and compare these
with Lhe inverted SY~C 2 from M43-ll to give, at M46-l, SET3.
bits with the data in the data :registers.
The cmnparn,tor vJJmc;1u,,n~;c;; level is inverted to Logic-0 at M 12-
The least-significa.,t bit changes at a rate of 256klf-fa, and the most-
significant bit at 125Hz. Coincidence occrnrri.ng iii any of the 4096 1; Ml2-2 '-"'""·-"-' except when FULL COUNT is low. 'The
binary-count time slots available ii, the comparator is shown as waveform at M12-l lasts for 1954ns and therefore allows two
a Logic-0 at TP5 for a period of 1954ns. consecutive SY1-.JC 2 pulses to be gated to M46--4 ( RST3 ).

This condition exists for all RST3 timings except at the binary count
of 4095; in this Lm;tance, 1:he FULL COUNT occurs after lhe
gatingof!hefirst SYNC 2 pulse,setsM12--2toLogic-l andsoprevents
the second pulse appearing at RS'T3 . In practice, the second pulse of

r 1951,ns 1
1mM1",J~--Ls=l ___Jr-=i JL
""'
_____Ji=1=

t~~ ~ U_J !J LI
i
fULL (OUNY I

!PS COMPMIATOR COINCIDENCE !BINARY 01

i
I
] - - - - - - - -- - ____=____=____=____=___=____=____=__ _
------------ ,\===

~ULL COU~H

COMPARATOR COINCIDENCE
TP5 (BINARY c0951

BINARY COUNT si,095 BINARY COUNT 0 0

6--36
 RlEFiERJENCJE§ !Ulldl REFERENCE mVIDJER

(Circuit Diagrams 430652 Pages 11.4-1 to

(Refer also to

The set and reset pulses from the precision divider comparators control
Lhe timing of JFET switches, which in tum chop the Master Reference
voltages.

The chopped references are filtered to generate two voltages whose

levels are proportional to the MSB and LSB sguarewaves' mark:period
ratio ( duty cycle). These MSB and LSB voltages are conditioned, m1d
transferred to the AC Assembly by full 4-wire sensed connection where
they are summed at a star-point to generate a Working Reference:
'REF+Ve'. The output voltage increments at high resolution (0.03ppm:
approx. 0.6µV), with a maximum possible range of adjustment of 0-
20V.
The high resolution associated with the full 13-bit count and a 20V
reference is advantageou~ for DC outputs. Such resolution, however,
is not strictly necessary for the accuracies associated with AC outputs;
and also the 1V Range is the basic AC range, all otherranges employing
either attenuation or amplification.

For AC outputs, therefore, the working reference is reduced to a range

from 0.126V to 2.79V by software. This results in a reduction of Lhe
maximum mark:period ratio of the chopping waveform to about 0.14.

(Reference PCB Assembly on Circuit Diagrmn DC430652

Page 11.4-1)

The Master Reference determines the fundamental long- and short-

term stability of the whole calibrator. It is a separate PCB, mounted on
the Reference Divider Assembly, which generates an ultra-stable
output voltage of approximately 20.6V.

This PCB module is assembled~ pre-conditioned and tested by Datron

Instruments as a single entity, and there is therefore no method of
repairing or testing it without specialized test equipment and processes.
If a fault is suspected on the Reference PCB Assembly , contact your
nearest Datron Service Center.

6.5.5 REFERENCE BUFFEfU)!V~DER

(Circuit Diagram 430652 Page 11.4-2)

R80 and R8 l drop the 20.6V Master Reference voltage (V Ref) to

+8.83V. M23/Q40 is a voltage-follower providing +8.83V wilh
respect to Common-4 at !he stllr-point TPl l to supply the Least-
.Significant Digit switch.

6-37
 (Fig.6.26)

SET3 and RST3 pulses from the LSB Comparator in the Analog The combi..,ed action of the switch FETs alternately provides ch::rrging
lmcrface Assembly are WlI!.Sferredinw guard via pulse trBIJ.Sformers Tl cu..v:rent for the 3-pole filter md discharging current
and T2, whose cei1tr,"-t:1p,iedl seco:no.:1rri 1l!e balanced about Con1mon- (during Two JFETs in ai,d are necessary
4 OV (TI) and +9V (T2). _,.··-a·~·a and discharging time-constants matching
th.e "O}f' resistances.
Q5-Q8 form a fast bistable using rm,r-c:oumE,Cl to switch TPl voltage over the
between +9V (mark) and +20V reset
SET3 pulse, Q29 and Q30 are switched ON, connecting LKA to
+9V Ref. Ql-Q4 have the same bistable action as Q5-Q8, switching T'ne 3-pole filter has the advantage of not being in series with the DC
Q3 l off during the "Mark" period -11 Vat TP2, thus disconnecting output signal The 125Hz ripple content is reduced to a level which is
LKA from Common-4 During the "Space" time after RST3 acceptable within the overall insti-ument specification" T'ne filter
pulse, Q29 and Q30 disconnect LKA from +9V Ref, switch output is buffered volmge-follower M16.
Q3 l on, connecting LKA to Common-4 (OV). Fig.6.26 illustrates this
action.

T P1 + 9V TP1 +9V

LKA

TP2 TP2

"Space'1

SET 3
l =------------- BmS fi){ed Period _ _ _ _ _ _ _ _ _ _ _ _ _ r
FIST 3
=-r-= Position is value-dependant

TP~20Vl
t9V ~---------------·
-l- L
ov
TP 2_ 11Vl. . ____________- ~l - L
t 9
LK A
ov

6-38
6.5.6.3
M20 perfonru; a dual role:
+27.5V
a. Its gain is set to 1/3 R65/R64

b. Its output is level-shifted toprnvide imoffsetbias forsu.mming

allows the summed output to have a negative zero offset).
TPS Voltage
Also a small thermal coefficient zero correction is factory-preset (D 10/ (3V Span)
R85).

M20 transfer function is approximately as shown.

The actual values are as set digitally in software, affecting 1:hemark:period +24.5V
ratio of the J-FET switches, using stored calibration constants. ov TP6 Voltage +9V
(9V Span)

The large reference voltage (20.6V) and the need for higher resolution
makes the MSB Switching circuitry more complex thim for LSB; but
the principle is the same: the set ru1;:l reset pulse-timing adjusts the
ma:rk:period ratio of the square wave fed to the filter.

The arrangement used for the MSB switchlng satisfies two

essential requirements:

21. The charge imd discharge path resistimces for the 7-pole filter must
be closely matched.

b. The leakage current of the path switched off must be minimal.

Requirement (ai) demands that the matched devices used in both paths
are of the same type (!P-chmnel JFETs have approximately 10 times the
"on" resistance of N-channel types). But without the voltage standoff
and leakage current shunt created by the switch, the pinch-off
gate voltage for one of the paths would be high enough to generate gate-
leakage current in excess of requirement (b ).

A description of the Main and Gu!IJ"d Switch action is given overleaf.

6-39
 ~JilA!tM iBlril@ S'UlJr!rCMES
(Circuit 430652 Page 11.4-1 o.nd Fig. 6.27)

RefenoFig. 6.27, in which only the Space to Mark state transfer 16J:11,B,~ ~w!·i;©u1
a-b-c is shown. (Fig.

The Mark to Space after SEl'2 and RST2 is delayed

The switch driver flip-flops establish ilie

and TP5 a.s controlled by the set
fastbistables, butnote control the
and

SETl and RSTl pulsestumQ35andQ32onandoff(TP3). Because

ofthe0.5µs delays, Q35 a-11dQ32conductonlyduring the time thatQ36
and Q33 are also conducting.

+21J6V
·t20 6V -11V -:-20 6\/
!lll I b! Icl

10V

-11 V

SET 2

SET 1

ov
TP4
·11V

<- 31 6V
TPS
t- 20 6V

t- 20 6V
TP3
-11 V

LKS
Swilth Oulpul
ov 0 5µ s
J
I a I Fil !er d1scharg1ng through lb) Filter charging through it I Fil hr charging through
0 34 Qnd Q37 a 3 3 ancl 036 only Q :n. Q36, !B 2 ond CBS

6-40
6.5.8.2 F!iteir
Fig.6.27(b)showsthisintennediatestateafter SE'f2 and before SETl,
In Fig. 6.27( a) the switches are in "space" state: mdFig. 6.27( c) illustrates the fully-conducting state after SETl . Note
that for descriptive purposes, the second step on LKB waveform is
Q37 and Q34 are turned on by TP4 at OV, to provide heavily exaggerated, and is not readily viewed on an oscilloscope. The
the filter discharge path. slightly longer charging time-constant durLng this half micro-second,
Q33 and Q36 are lmned off by TPS at +31.6V due to the higher resistance of Q36/Q33, is not sufficient to disturb the
Q32 and Q35 are turned off by TP3 at -11 V linearity of the filter in excess of specification.

The filter discharges via resistor R79 and FlETs Q34 and During TI1e voltage between TP4 1:1_r1d LKB during 'mark' state is some 31 volts.
bothMarkandSpaceperiods, R79 (78.7k0hms) is a major determinant 1n the absence of D19, an adverse voltage distribution could cause
of the 7-pole filter charge and discharge currents. Because in 'space' excessive reverse leakage in Q37. D19 controls the distribution by
state the 'On' resistances of Q34 and Q37 (3Q-5Q each) are very small limiting the voltage at its cathode to about+ lOV, constraining Q37
in comparison, the potential at link B can be regarded as zero when source-gate voltage to a tolerable 20.5V.
considering the effects of the other switching voltages.

Reverse leakage currents in JFET junctions are normally of the order

of a few picoarnps unless the junction voltages are much in excess of
6.5.9 7=POLE FilTER
20V. To control leakage effects from the four JFETs which are turned (Circuit Diagram 430652 Page 11.4-1)
off, the cathode of diode D20 is connected to the common junction of
the four devices. Its anode is returned to the junctionofR125 and Rl26, M26, M28, M3 2, Q4 l and Q42, together with associated capacitors and
close to + lOV. resistors, form a 7-pole Bessel filter in three active elements; providing
approximately 135dB of attenuation at the 125Hz switching frequency
The reverse leakage characteristics for aJ108 PET (Q35 andQ32) axe and increasing at a rate of 140dB/decade. This allows sufficient
generally several times heavier than for a Jl74 (Q36 and Q33). This bandwidth to avoid excessive settling time while reducing the output
means that in this switch, the leakage currents via Q35 and Q32 out of ripple to within instrument specification. Q41 and Q42 source-
the common junction are 4-5 times greater than Lh.ose entering via Q3 6 followers provide input bias currents for M26 andM28 from the 15V
and Q33. supplies, and buffer the line from bias-current effects. M32 bias-
current effects are insignifica_nt.
The net leakage out of the junction holds D20 slightly in forward bias,
so that its cathode cannot rise above about+ 10.3 V when Lne four FETs The '+Ve SUMMING AMP' filteroutput DC voltage (TP13), is fed to
are turned off in 'space' state. Thus D20 guards the "buffer' FlETs Q33 a buffer amplifier for subsequent summing with the output from the
andQ32from the effects of the relatively high voltageonQ36 gate. The Least-Significant Switch offset-bias amplifier. R 101 md CS 1 prevent
effects of the buffer FETs' own leakages on the voltage at the filter input any spike remnants from the chopper-stabilized buffer amplifier being
can be regarded as negligible, because Q33 leakage currents towards fed back into the filter.
LKB are virtually balanced by those away via Q32.

6.5.8.3 FIiter Charge Path

To preserve linearity over the full range ofMark:Periodratios, the filter

charging path time consl:lllnt must closely match that of the discharge
path. Q35 and Q32 are factory-selected to form a matched set with Q34
and Q37, all Jl08 N-channel FETs (the 'on' resistance of P-channel
FETs in a true complementary switch would be much higher, of the
order of 30Q-40Q). Nevertheless, to avoid high voltages being
developed across Q35/Q32 when changing between states (causing
excessive leakage), P-channel FE'fs are employed. Q36/Q33 are
switched on before (and switched off after) Q35/Q32.

6-41
6.5. 10 SUMMING AMPLIFIER
(Circuit Diagram 430652 Page 11.4-3)

6.5.10.1 '+VIE SUMMING AMP" BU1He1r The whole amplifier acts as a voltage-follower, but without bootstrapped
supplies (the small input voltage dynamic range of approx. 2.5mV does
M33, M34 and Q44 buffer the'+ Ve SUMMIN"G AMP' voltage output not warrant it). Otherwise the circuit is identical to the'+Ve SUMMING
from the 7-pole filter (this is proportional to the Mark/Period ratio of the AMP'. M39 /Q5 2 provide the output drive, buffering the output of M3 8
13 most-significant bits of the binary word which defines the instrument and Q51.
output value demand).
The output 'Lo 0/P' is delivered to the DC assembly via RL2 for
M33 is a high-gain, chopper-stabilized integrator with a bandwidth of positive DC outputs, or viaRLl if the output is to be negative. For AC
approximately lOHz, and Q44 provides additional bandwidth for outputs, it is always delivered to the AC assembly via RL2 (RLl being
rejection of HF common-mode noise. permanently de-energized for AC ranges).

M35, Dl4, D15, Q48 and Q49 generate boot-strapped supplies to The feedback voltage, sensed in the DC or AC assembly, is returned via
preserve full dynamic-range linearity. Q46 and Q47 establish 3m.A the appropriate relay, and applied to the inverting input of the whole
constant-current drives for D14 and D15. buffer via R127.

The whole amplifier acts as a voltage-follower, M34/Q45 providing the

output drive, buffering the output of M33 and Q44. The output 6.5.10.3 Summing
'Hi 0/P' is delivered to the DC assembly via RL2 for positive DC
outputs, or via RLl if the output is to be negative. For AC outputs, it On the DC or AC assembly, the outputs from the two buffers are
is always delivered to the AC assemblyviaRL2 (RLl being permanently summed by defining the 'Lo 0/P' level as 'Reference Common'
de-energized for AC ranges). The output is sensed either in the DC or (Common-I for DC, Common-2C for AC), and the 'Hi 0/P' level as
AC assembly to account for the volts-drops in the connecting circuit. 'REF+Ve'. Thus at any instant, the voltage developed as 'REF+Ve' with
The sense feedback voltage 'Hi SENSE' is applied to the inverting input respect to 'Reference Common' will always be 'Hi 0/P' minus 'Lo 0/P',
of the whole buffer via R98. at their current values.

For a zero count in the MSB comparator, the filter output voltage is The reference voltages and reference division ciruitry ;ire chosen to
approximately +3.2mV, and a full count of 8191 would produce allow for softw;ire calibration adjustments, so i:he summing span
+20.6V. These are the voltages which are developed at the buffer overlaps the possible required span of OV to 19.999999V at both
output. extremes:

With an overall 25-bit count of zero in the comparators, REF+ Ve

is +3.2m V minus +23.SmV, a negative overlap of 20.3mV.

M38, M39 and Q51 buffer i:he '-Ve SUMMING AMP' voltage output At overall full count, REF+Ve is +20.6V minus +20.9mV,
from the Offset Bias Amplifier derived from the 3-pole filter (this is approximately +20.58V.
proportional to the Mark/Period ratio of the 12 least-~ignificant bil.s of
the binary word which defines i:he instrument output value demand).

The dynamic range of the filter output voltage was originally defined
by the Reference Buffer (8.83V) for efficient operation of the FET RLl and RL2 are used in DC ranges for polarity reversal.
switching circuitry. However, this is not necessary for AC operation, for which RLl is un-
energized, and RL2 is energized, outputs from the summing buffers
It was scaled in the Offset Bias Amplifier to give +27.SV for an LSB being fed to the AC assembly via RL2.
comparator countofzero (from approx. +l.lmV atTP6), md +24.SV
for a full count of 4095 (from +8.83V atTP6). lltnowneeds to be scaled
down so that it has correct proportionality to the '+Ve SUMMING
AMP' dynamic range.
For DC operation, the summed DC reference is applied to the Error
R99 and RlOO attenuate the '-Ve SUMMING AMP' input voltage by a Amplifier directly (refer to page 115-1), but for AC operation, the DC
factorof0.8545 x 10·3 • At zero count,+27.SV is reduced to +23.SmV, reference is applied to a voltage divider which is used to provide a
and at full count +24.5V reduces to +20.9mV. These me the extremes 'Quasi-sine wave' AC reference signal. The generation of this signal is
of voltage developed at the buffer output. described in Section 6.6.

6-42
 REFE
R!EFIERIENCIE~
The Reference Divider hardware is common to both DC and AC
In the Sense/Reference comparator, a considerable advantage is gained outputs. On DC ranges, the basic voltage range is the 1OV Range, with
by comparing AC with AC. (l[f AC sense were compared wiLh DC 100% ovemmge at Full Scale. In these cases the full span of reference
reference, small DC offsets would be magnified, leading to 'DC values is employed, generating the resolutionnecessary to accommodate
turnover' errors). The AC waveform used as reference is constructed the DC accuracy available.
in ten steps by a digitally controlled switching network, based on the
DC reference as its peak value. Xt has been given the name 'Quasi- The same analog accuracy is not available for AC, so the high
Sinewave". resolution is not necessary. Moreover, the linearity of the analog
circuitry is improved by using a smaller dynamic range in the reference
To drive the VCA, the comparator produces a DC error signal which is circuits. So for AC outputs the 1V Range is the basic range, and the
proportional to the difference in 'Mean Square' values, and is driven to software scales its demanded value accordingly.
zero by the action of the Output-Sense loop. At zero error the RMS
value of the comparator's sense input has thus been adjusted by the loop The sensed output is compared against the quasi-sinewave, whose
to be equal to the RMS value of its reference input. characteristics match those of the sensed sinewave. To construct the
quasi-sinewave, the DC reference voltage needs to be set as its peak
On the 1V Range there is neither amplification nor attenuation in the value.
Output-Sense loop. The quasi-sinew ave is designed so that with the 1V
Range selected, its RMS value is equal to the voltage demanded on the The software imposes the scaling factors which establish the reference
front panel OUTPUT display, (with small, controlled adjustments for voltage at the peak value of the quasi-sinew ave. Thus the full span of
calibration). the 25-bitcomparator, and hence the possible dynamic range of the DC
reference, are realized only on DC ranges and at times when the
On higher ranges, decades of amplification are switched in to set the Reference Divider itself is being calibrated.
output to the demanded voltage. Switched decades of attenuation
reduce the sensed sinew ave back ro the 1V-Range level for comparison Before initial calibration, the maximum obtainable reference voltage
with the quasi-sinewave. for AC is slightly greater than 2.8V, and lhe minimum is slightly less
than 125mV. Titls overlaps the pec!k: voltage.: of the quasi-sinewaves
For millivolt ranges, the instrument output terminals are not within the corresponding to the maximum and miniimum values of sensed output;
output/sense loop. Instead, the AC 1V output from the l V buffer is giving a margin for occwate calibration from digital gain factors held
sensed internally and applied to the comparator to complete the in the non-volatile calibration memory.
The AC 1V signal is reduced to the selected millivolt range levels at the
terminals by precise, passive, decade attenuators.

On current ranges, the current reference is derived from either the

closed 1V or lOV Range Output/Sense loop.

Therefore on all ranges lhe Output/Sense loop gain is driven to a

magnitude of 1, so that the VCA and the comparator both operate at 1V
Range levels.

643
 REFERENCES 6JiL5 QUASl SINEWAVE GENERATOR
0

VAUJES for AC (Circuit Diagram 400844 page 11.7-3)

As mentioned earlier, the DC Reference is used to establish the The SYNC 0 input to Ml 1-15 RESET, ifset to Logic-I, would disable
amplitude of the quasi-sinew ave. When the l V AC Range is selected, the Quasi-sinew ave sequence counter Ml 1. The facility is not required
the reference is set to the peak value of the quasi-sinewave, which is in this application so J?-49 is unconnected on the Mother assembly
1.397 times the demanded RMS (sinewave) voltage output of the (CircuitDiagram430604 Page 11.16-2). Mll-15 is thus pulled down
instrument. In normal use, therefore, the reference voltage is adjusted to logic-0 by R40 to enable the quasi-sinewave for both AC Voltage
by front panel OUTPUT display selections; between 125.7mV and AC Current functions.
0.9V selection) and2.79V (for 1.999999V selection), plus or minus any
user-calibration corrections. The quasi-sinewave is generated at a frequency determined by the
Frequency Synthesizer 1OOHz-4kHz output (para 8 .1.3 .3 describes the
On higher and lower AC ranges, analog range switching in the sense synthesis), clocking the decade counter Mll viaJ7-50. This continuously
amplifiers scales the sense voltages for comparison with the same RMS recycles Ml 1 in ascending count through~ to¼,, ten clocks constituting
voltage span of quasi-sinewaves. one cycle of the quasi-sinewave, so the quasi-sinewave runs at a
frequency of between lOHz and 400Hz. The carry C out of Mll returns
to the Synthesizer via J7-5 l to be selected as the reference frequency
for the lOOHz (10-330Hz) frequency range.
6Jt4 REFERENCE INVERTER
(Circuit Diagram400844 page 11.7-2) With increase of frequency range, the difference between the frequencies
of output and quasi-sinewave increases in decade steps. As the
The quasi-sinewave is derived by a specific form of D-A converter, comparison of sense md quasi-sinew ave signals is performed atmean-
selecting voltages from a divider network. Because negative values are square DC levels, this difference theoretically does not matter, so long
required, the divider is strung between positive and negative reference as the signal is at an exact multiple of the quasi-sinewave frequency.
voltages. The unity-gain Reference Inverter generates the negative However, to achieve optimum operation of the Sense/Reference
reference 'REF-Ve' by inverting 'REF+Ve'. comparator, each zero crossing of the quru;i-sinewave is synchronized
to coincide with a seru;e-signal zero crossing.
Ml, M2 and Ql perform the inversion. M2 generates the bandwidth
necessary for amplitude switching operations, while chopper-stabilized Synchronization is achieved by the clock input to M9, which controls
integrator Ml removes DC offsets, always referring the L,verter output the timing of the quasi-sinewave switches M8 and Ml 4. Using the
to Common-2C. To compensate for RMS value changes i., the quasi- same clocks, Ml 1 andMlO transit times prevent the data from arriving
sinewave (due to switching errors arising from frequency dwnges), at M9 'D' inputs until the data already established there by the previous
feedback from thequasi-sinewaveis appliedviaRl, C4, R4 and CS. Ql clock pulse has been latched at its outputs. Thus data ripples through
provides the output drive to the quasi-sinewave generator. Ml 1 and M9 at successive clock pulses.

The ripple delays the data by one clock period and would, if left
uncorrected, put the switching out of sequence. The arrangement of the
connections between Ml 1 outputs and M9 data inputs, combines
appropriate outputs so ru; to correct the switching pattern. 'fhe table in
Fig. 6.28 demonstrates the rotation of l clock period; the quasi-
sinewave steps being labelled at M9 inputs and outputs.

The quru;i-sinewave is output to the transfer switching input to the Sig/

Ref comparator at Ml 6-1. The action of the transfer switch is described
in Section 95.

A second output is filtered and fed back as compensation to the

Reference l[nvertor as described earlier (para 6.6.4 ).

6-44
 Step OI 1 2 3 4 5 IS 1 s 9

M11 Output at
logic-1: Q9 00 01 02 Q3 Q4 Cls 06 Q7 Oa

111110 Output pin

at logic-1: 4 11 - 11 4 10 3 - 3 10

M9 Output pin
at logic-1: 01 04 Os 04 01 02 00 03 00 02

Switch Energized
MB pin: 5 6 13 6 5 - - - . -
M14pin: - - - - - 5 6 13 6 5
-
Step Voltage
fed to M16-1: +0.42 +1.16 + 1.397 +1.16 +D.42 -0.42 -1.16 -1.397 -1.16 -0.42

REF+Ve

0 4 0

5 9

REF-Ve

FIG. 6.28 QUASI-SINEWAVE GENERATION

6-45
 6-46 is left blank

6-46
6. 7 POWER SUPPLIES
The circuits described in this section perform the following functions: 607.1 UNE POWER DISTRIBUTION
(Circuit Diagram 430830 Page 11.17-2)
Line power switching, fusing, filtering, voltage selection and
(Fig.6.29)
transformation.
The single phase line supply enters via a 3-pole input cable at the rear
Main digital supply generation and distribution (Outguard). of the instrument. The cable connector plugs into a power input module
which contains a fuse, filter and line voltage selector pcb. (For details
Display voltage supply generation. of fuse values and operating voltage selection refer to the User's
Handbook, Section 2).
In-guard stabilized supply generation for Conunon-2 and Common-
4 circuitry. Both 'line' and 'neutral' rails are filtered by a low-pass LC network
before being fed through the instrument to the two-pole 'Power' switch
A simplified power-distribution block diagram appears at Fig. 6.29. on the front panel.

The power input module is mounted on the rear panel. The mains (line) The switched supply is fed back into the power input module, to the
transformer is located in the rear section of the instrument, close to the voltage selector pcb, which configures the line transformer primary
In-guard and Out-guard Power Supply assemblies. circuit as determined by the user. Power for the air circulation fan is
provided directly from the power input module.
(For details oflocation and attachment, refer to Section3; fil!d Section
11,page 11.0-1). All line trfil!Sformer secondaries are electrostatically decoupled from
the primaries by a ground screen between the windings. The secondaries
which supply i:he Common-2 and Comrnon-4 in-guard circuits are
decoupled by an additional screen which is connected to i:he instrument
guard.

Out-Guard
Power Out-Guard
s - - - - ~ Circutts
Supply

Line
nput

8 400V
In-Guard
Power
Supply
In-Guard
Circutts

Power Power
Lina Heatsinks
Transformer Supply Amplifier
ON
Power
Switch
High Voltage
Fan Transformer

FIG. 6.29 POWER DISTRIBUTION SIMPLIFIED BLOCK DIAGRAM

6-47
 SUIPIPUES
(Circuit Diagram,400996 Page 11 ,10-1)

-VFJ!L_HI and-VFIL_LO are generated from a split secondary winding

on the line transformeY by 25V positive voltage regulator U102 and 8V
This circuit provides: negative regulator U103 respectively" The positive output of
Ul02 is connected ltO the +5V out-guard supply so that its negative
+8V supply for the Front and Digital assemblies" output sits at -20V and fue negative output of U103 sits at -28V 0

circuits"

This circuit provides a line-hum cancelling (bucking) output to the

instrument guard network For adjustments refer to Section4"9"
This is taken directly from full-wave rectifier D101, D102 via fuse
FlOl (rated at 4A)"

The output voltage is controlled by series regulator Q102, Q103" Load

current is sensed by Rl in the base-emitter circuit of QlOl, which
provides short circuit cu_rrent lirniting by turning on 1u1d thereby
reducing Ll-ie base drive in Q102 ;md Q103 if the load current exceeds The general 15V supply for the analog circuitry is provided by three
approxirnately 2A The 2.45V zener Dl04 provides the reference integrated-circuit regulators 11 "11-1) as follows:
voltage for comparator U101 at UlOl-3" The output voltage is sensed
between the +5V and DIG COMMON rails on the Mother assembly, +li§V fromM2
and divided down to reference potential at UlOl-2" R106 and R109 Because of the high current taken from this supply, the regulator
ensure that regulation persists even if the sense links 21xe disconnected" power dissipation is shared" The rectifier output is first regulated
to +HLSV by Ql, and D9; and then to +15V by M2"
U 101 output drives current sink Ql 04 whose collector current controls
Ql 02 and Ql03 conduction" Uthe +5V rail voltage falls due to loading, -lSVfrnm M]_
Q104 collector current increases, increasing Q102 and Q103 conduction This is a mirror image of the positive supply"
to restore the rail voltage" Zener D105 prevents the positive excursion
of the +5V rail in the event of regulator breakdown" Zener D103 -UllVl'rnllii11 M\!Ji
restricts positive excursions of Ql04 base voltage, and hence the Derived from the -15V supply"
maximum base current in Q102 and Ql03" Cl02 and C103 give a
controlled fast response to reduce the effects of transients on the +5V The supply is protected by 3"15A fuses F3 md F4 at the bridge rectifier
raiL output.

PTC thermistor Rl12 protects the power supply from high ground- The SV supply for the Sine-Source assembly is provided by two
leakage currents, notably in the external circuits of the IEEE 488 bus integrated-circuit regulators M!l andM9 (page l l ol 1-2 )" The supply is
system" R 112 presents a minimum of80Q between the digital common protected by lA fuses F5 and F6 at the bridge rectifier output. Chokes
line and ground; this resistance increasing with increasing ground- L 7 and L9 attenuate HF transients on the AC input.
leakage current

This provides +22V and -22V unregulated power outputs to the PS/I
Heatsink assembly" Both supplies are protected at 4A by fuses Fl and
The vacuum fluorescent displays on the Front Panel Assembly require F2" The 22V common return is maintained close to the common-2
a low-voltage ( 6" 7V rms typical) AC filament supply centred around - return potential by resistor R l"
24V with respect to Digital Common" This AC supply is generated
from-VFIL_HI (-20V) and-VFIL_LO (-28V) by U110 on the Display
Assembly (Circuit Diagram, 400993 Page 11 "l-2)"

6-48
 The output voltage is divided by R26 and R25 to provide a sense signal
for comparator Ml, which is powered by a local shunt regulator D8/
R l 6/C8. The 2.45V reference for the comparator is derived by D6/R23
This circuit provides +36V, +l5V and -15V regulated outputs to the from the comparator supply o
Reference Divider in-gmrrd circuits. The + 36V is also used to
power the +20V Master DC Reference. Ml output drives whose collectorvoltagecontrols Q6 and hence Q2
conduction. If the +38V rail voltage falls due to loading, Q8 collector
Two secondary windings of the line transformer are used, lli,d inter- voltage ri1Ses, Lncre!IBing Q5 and conduction to restore the rail
supply transients are reduced by the coupling arrangements of voltageo
common-mode choke LlO. The rectified output from bridge W4 is
series-regulated by M3 to produce the +36V supply. R2/R3 sense the Load cunent is sensed by R24 in ihe base-emitter circuit ofQ5, which
output voltage. is normallycutoff lli'1ess the load current exceeds l 70mA. At this point
Q5 conducts and pulls down the base of Q6, setting a hard current limit
Dll andM4 reduce the +36V to generate the +15V regulated supply.
Zener diode D2 turns hard on in fue event of an output short circuit,
bridge W3 and reguiator M7. nn)v1ctrnt2: arapidreponse to catastrophic failure in the power amplifier
As the output falls below +22V, D2 artests the fall
base, hard on ;;i.nd turning Q6 and Q2 off. This
S,1,3i;;J, ±33'\f C©Jmmviiri 2 0 ""'·'"'''llla,;s; ihe output current, which falls to less
430653 11.12-1 and430604 drn._11
Page 11.16-5)
When the load is removed, the conduction of QS via R26/R25 is
The ±38V regulated is used for two purposes: i,,.sufficient to hold cut off, especially as is also cut off by the
comparator. S:o Q2 is allowed to conduc):, the output voltage rises until
first D2, i,nd tllen cut off 8Ild the output is restored to
comparator control.
to provide sm:irce voltage to reduce diE;sitJation
the Power n.,ui,1,u11~1 assembly, when wired-in fuses Fl a.nd F2. These
output on the lOOV DC Rai,ge (refer to sub-section in the event of an output short-circuit
1w,,t,,,.,,F,il from reverse polarity Dl and D2
It is plugged into the Mother =~'"m11m1 i.71 the rear compartment next to
the Heatsinks.

The mains (line) transformer40VRM§ sec:on.d.airy 16:,LS',,5 ±:3"l©l\f ~iUl!JiJIY fF~!!IIJJli'®

to Common-2 on the Mother as,;en1bl'v. (Circuit 430618
output by R25 on the Mother !IB,:emtbh
on the guard screens. The 40V is rectified, filtered and smootlr...d on
the Mother assembly before being to ihe rngulator at :llpprox. The monitor is described in Section 7, pam 7.8.63.
50VDC.

On the ±38V Power assembly the

by series regulators Q2 andl QL J!,,,s the regulator is ""'"l'l"''"'''i"'
the positive side is described. 'f.hi§ is described in Section 7.85 oind 7.8.6.4.

6-49
---
SECTION 7
DC VOLTAGE UTPUTS-AMPLITUDECONTROLSYSTEM
1
When DC Voltage Function ii; selecied, a on the On the 1V sense the output at 1V Range
Reference Divider assembly feeds the output of the sum..Jl1ing levels, comparing the seinsed voltage with the attenuated DC
amplifier into the DC assembly as DC Ref (Hi the value Ref and t,O-ITC'r'.u,n<V the output M on the lOV Rangeo
of which represents the demanded output voltage and polarity" On the 100V Range, sense the output voltage at 100V levels,
The DC Voltage circuitry selects the required range, from
and reduce the sensed voltage to lOV levels. Compare the
switching data transmitted into guard via the Serial Data Lin_lc attenuated voltage with the DC Ref input from the Reference
The selected range circuit generates the demanded voltage at the
Divider and corirect the output voltage as on Lh.e lOV Range"
output tennimik Output switching and protection are provided"
On ranges below 1V; sense the 1V Buffer output at 1V Range
levels, correcting its output as on the 1V
On the rnoov a VCA drive from the Error
Amplifier to a DC Modulatm for ,he hig_li voltage amplification
The DC =ufi·""''"" Control is briefly described circuits" Attenuate the comparing the
in Section 5, and illustrated in the Block diagram of 53 0 attenuated at 10V Range
DC up to 100V aredescribedinSection:506, and levels, and conecti11g the OUi}JUt a§ on the lOV lifangeo
in Section 5 08 .1; ii.t block levet Provide cwar,nrno-ofDC
Sense, under the control of
Interfaceo

The circuits described in i:his section the Sense excess cti1-nents in the output circuit?
functions: Lll\1 ST starus signal to tl1.e CPU via the
Interfaceo
lBuffer i:he DC Ref
output to the i,,stmrnent tennmals, on Lhe lOV DC apprmL
Range" output line, n 7 ,rwrufrrn, a HV ST
Analog Control Interfaceo
Amplify the DC output voltages:
-200V to -:-200V on 100V Range Man.y of Lhe circuits described in tlns section b'Xe located on the
-llOOV to +llOOV on 1000V DC PCB ~"'-"'"-'', The major ex,ceJJtl(,ns are as follows:
Attenuate the DC Ref voltage ;;md provide oulput lOV Buffer stage
between -2V and -:-2V on the 1V DC Range"
lOOV A_mplifier Power Amplifier
Further attenuate Lhe l V Range voltages 8!lld output
assembly and Heamink
voltages:
assemblieso
-200mV to -:-200mV on lOOmV Range 100-0V Rmge output circuits LF and HF transformer
-20mV to +20mV on lOmV Rai,ge assemblies and the High
-2mV to +2mV on lmV Range Voltage assembly"
-200µV to +200µV on FunctionSvri~;hin~ Current/Ohms assembly"
On the lOV Range, sense the output voltage (at the load in Output Filtering Terminal Bmrrd assembly"
Remote Sense), mal<lng continuous, direct comparisons in a
closed negative-feedback loop with the DC Refvohage input
from the Precision Divider" The oompariron generates m
'error' voltage which corrects the output voltage"

7-1
 (Fig. 7.1)

The 10V range is regarded as the basic DC rnr1ge of the ii"IBtrument,

because it uses the fllll 20V Reference, sufferLng no overall
voltage attenuationirmr aii<1.plification i.,,its output loop. However, The low voltage loop a111td routing are illustrated in the simplified
it does require power amplification at dissipations which preclude of Fig. 7.1. vv ,1.1.,,.lll.," contacts are show"TI in positions
its positioning within the thermal shield, so its output buffer is set for 1:he 1V Range.
located on the Power Amplifier a.ss~.mbly. ,=, uu;lm-co:miJfa;aiJ~s DC Ref is variable between -20V and +20V referred to comnmn-
the routing of its 1, imd the ati,ei1LU2Lto:rvro 1ifi(!es un.Uc,<w>e D'el>ween and+2V.
The 1V range is more direct; its buffer is located on tl°ie DC The Error Ai"Tiplifier and 1V Buffer are connected to for.m a
assembly, and tlriere are fewer crrcuh elements to describe in its voltage-follower when I+ is connected to Hi (in either local or
paLh.. Forreasons of simplicity, therefore, the chosen remote seru;e ).
for this description of the basic DC output loop. The oulput from the 1V Buffer is connected directly to the I+
The descriptions in Section 7.2 .1 and Section 73 concentrate on terminal via power switching, the sense feedback returning from
the signal path of the 1V Range loop; from the polarity switch in the Hi terminal, via sense switching, to the Error Amplifier
the Precision Divider, out to the 'Power' terminals, and back to the inverting The sensed output voltage is adjusted by the
'Sense' input of the Error Amphfier. feedbacknntil it equals the attenuated DC RefV alue, i.e. for zero
differential Lnput to the Error Araplifier.
For descriptions ofthe alterations to the acco1n1nodate
the other DC voltage rru1ges, refer 1:0 the sub-sections:
lOOmV 7.4
75
7.6
7.8
lkV Rffige 7.9

Pileclol

1
4f~~

t> 12~0

J
U@ff'riii1ffff'JQU
{ji@ll!J'ai 11
/!J23fX£m@ff)/
[J

'"

·111 & 10V

L trom
High Volte~®
S©ns.s .O.ttenuator

7-2
7.3 DC 1V LOOP

7,3,1 REFERENCE ESW;TCHING

ASSEMBLY On the 1V and lOV ranges the l V + lOV + lOOV star point is
(Circuit diagram 430652 Page 11.4-3) decoupled to Conunon-2A by C28 via contacts 2/3 of energized
For positive outputs, the positive DC Reference PIH[J[(REF), relay RlA-.
PLO(REF), SHJ[(REF) and SLO(REF) pass via energized relay RL5 is energized on the 1V and lOV ranges; and after
RL2, to be output as a 4-wire sensed cmmection into the DC passing through the back-to-back contacts RL5-8/9, which cancel
assembly. The four lines are routed out at J4 9, 10, 11 and their own thermal EMFs, the l V +1OV+ 1OOV signal is renamed
12 into the Mother assembly. For negative outputs, energized 'PHJ[(DCV)'.
relay RLl configures the lines to give a negative DC reference.

7.3.6 OUTPUT SWITCHING

7,3.2 DC ASSEMBLY (Circuit Diagram 430536 Page 115-2)
(Circuit diagram 430536 Page 11.5-1)
The PHI(DCV) output and other connections from the Range
The DC Reference enters atJ5 pins 1, 2, 3 and 4. On DC Voltage relays (Page 115-1) are passed to the instrument output terminals
ranges, RLl 8 -:.,onnects the power and sense lines to the two star- via several relay contacts which provide switching for Remote or
points TP2 and TP3. TP3 is the signal Common- I point, to which Local Sense, Remote or Local Guard, and Output On/Off.
all instrument DC voltage sense inputs are referred.
The output does not travel directly to the terminals from the DC
For the 1V and lowerranges, RLl 6-5/4 connects the output of the assembly, as further switching is required. If Option 40 or 50 is
1V attenuator to the non-inverting input of the Error Amplifier. fitted, function changes switch the terminal lines on the Current/
(On the lOV and higher ranges, RL16-8/9 connects the full DC Ohms assembly. If neither Option 40 nor 50 is fitted, a Current/
Reference to the Error Amplifier.) Ohms Link PCB (Part No. 410288) is fitted in place of the
Current/Ohms assembly. This PC:B provides direct connections
for 1:he signals, on their route to the instrument terminals (para
73.8.1.)
The DC Ref Voltage from the Reference Divider is two
amplifiers: M21 is a high-gain chopper-stabilized integrator of
approximately lOHz bandwidth, Q5 provides additional
bandwidth for rejection of HF common-mode noise. M20 For DC voltage ranges, relays RLlO and RLll are energized.
provides additional gain and output drive, through a transient- The PHJ[(DCV) line from the range relays passes via RLl 0
suppressing diode clamp circuit. contacts, TP8, lA fuse F6, and RL15 contacts (if output is set
ON); to the Pill(V) line atJ5-l 9. For DC voltage outputs, the four
The whole amplifier is bootstrapped by M22, D48, D49, QIS, ACV lines at 15-25/26/29/30 are disconnected by relays in the
andQlO. Q8/Q9provide l.4mAconstant-currentdrivesforD48/ AC assembly.
D49 over the range ofBS-Common variation (-20V to +20V on
the lOV and highenanges ). Power for the bootstrapped amplifier ][n Remote Sense, the power return line PLO(DCV) is linked via
is obtained originally from the ±38V used also to power RLl 1 contacts, lA fuses F4 and F3, relay RL14 and RL15
the lOV Buffer in the PA assembly, referred to Common-2. contacts to J5-23 as PLO(V). PLO(DCV) is held close to
Common-2A by R56/C30 (page 11 5-1 ), being protected against
Extensive screening and filtering is used to eliminate the effects excessive departure from Common-2A potential by the back-to-
of the chopping spikes at inputs 2111d output of M21. back 3V zeners Dl3 and D25.
The voltage developed ocross R56 by the output current is
7.3.4 1V BUFFER monitored by comparator M13 (page 115-2).
On the 1V and lower ranges the error amplifier output is applied
to the l VB uffer, via the closed contacts 10/11 of energized relay 7.:Ut'.2 Output On/Off.
RL16. A current amplifier M23 is chosen, as the buffer has to Because the DCV and ACY lines are separately switched, a
drive the external load directly via the output switching, output single independent 4-pole relay RL15 can be used to set output
lines and external leads. It also drives the 100mV Attenuator on on and off. Thus the lines atJS-19/20/23/24 carry either DCV or
the lOOµV - lOOmV ranges. ACY signals to and from the output terminals.
M23 is powered by a separate, individually filtered, 8V supply Where ACY and DCV join, the power lines change their names
(refer to pages 11.5-4 and 11.11-2). Its input and output are to PHI(V) and PLO(V).
protected by back-to-back zener diodes.
The output from the l V buffer is connected, via contacts 12/7 of
energized relay RL3, to the 'lV+lOV+lOOV' Pffi(DCV) star
point.

7-3
7.3.6.3 Remote Sense Switching. When the output current through R56 exceeds approximately
28.Sm.A, the voltage across it exceeds 285mV and one of the
When Remote Sense is not selected, two-wire outputs to external
halves of M13 switches its output to the negative rail (analog
loads can only be connected from the Hi and Lo tenninals ( a relay
logic-0). Diode D52 conducts, pulling Ml0-6 and Ml0-9 to
on the Mother assembly disconnects the I+ terminal). Relay
logic-0:
contacts RL14-9/8 connectPHI(DCV) to SHI(DCV), andRL14-
3/2 connect PLO(DCV) to SLO(DCV). Relay contact RL14-5/ JLIM DET Acfr11atimll:
4 is open, severing the connection to the I- terminal. On the lOV and lower DC ranges, Ml0-5 is permanently held
at logic-I disabling MI0-6, so the overcurrent signal has no
In Remote Sense relay RL14 is energized, removing the
effect on MI0-4, which is held at logic-I and D3 remains in
connections between the power and sense lines, and RL14-5/4
reverse bias. The LTh1 DET signal is not activated.
reinstates the link from PLO(DCV) to the I- terminal. This gives
full 4-wire sensing at the external load. On the 1OOVDC or lkVDC range, M 10-6 is enabled by M 10-
5 at logic-0, so the overcurrent signal sets Ml0-4 to logic-0
7.3.6.4 Remote Guard Switching and LIM DET is activated at logic-I.

The front panel 'Guard' terminals are permanently connected to LIM ST Activation:
the internal guard shields via JS-15/16 and JS-11/12. With In this case the effect of the lOOVDC and lkVDC signals is
'Remote Guard' selected, the direct connection between Guard reversed, and Ml0-9 is sensitized to the DC overcurrent
and Lo is severed by the open contact of energized relay RLl 7. signal only on the lOV and 1V ranges, when Ml0-8 is at
R121 damps any high frequency resonance in the combined logic-0. For excessive DC output currents, Ml0-10 sets D9
internal and external guard circuits; C62 reducing HF noise on cathode to logic-0 pulling the LIM ST line to its logic-0
the millivolt ranges. With Remote Guard off, RLl 7 connects the active state.
guards to PLO(V) via PTC thermistor R97, which also assists in
The AC lkV Overcurrent Detector receives no input on DC
reducing millivolt noise.
ranges, as no current passes through the sensing resistors Rl07
and R108.
703.7 OUTPUT PROTECTION
Two circuits are described in the following paragraphs:
1,3o1o2 High Voltage Status Detector
fOvervoltage')
The DC Over current Detector, sensing the current flowing in
the PLO(DCV) return line and sending a signal to the status- In order to provide information to the CPU so that it can decide
reporting logic if the DC current exceeds approx. 28.5mA. whether the High/Low voltage state is as demanded, the voltage
level on the PHl(V) line (TP8) is monitored and compared
On the lOOV and lkVDCranges the 'LTh1 DETsignalissent, against areference. The detector senses DC levels for DC voltage
but on the lOV DC and lower ranges the 'LIM ST signal is outputs, or peak levels for AC voltage outputs.
made active.
Ml 7 is a dual comparator whose hysteresis is set to ±1.22V. As
The Overvoltage Detector provides an indication to the CPU long as the voltage on the PHI(V) line remains within approx.
that the output voltage is in 'High Voltage State', ie. the ±125V, the division ratio of M16 keeps the input to Ml7-5/9
'HY ST' signal is activated if the output DC or peak AC within the ±l.22V hysteresis, and Ml 7-12/7 remains at logic-I
voltage is greater than 11 OV. Uthe instrument has not been (OV).
programmed into High Voltage State, then an anomaly The PHl(V) voltage at 'fP8 is applied via R83 and R62 to Ml 6-
exists, and remedial action is taken by the CPU. 2, which is referred to Common-2B, M16-3 being connected
The results of activating the overcu:rrent detecttor are described directly to this common. Resistors R61 and R68 apply feedback
later in sub-section 7.12.7. toM16, setting its gain to -0.0098. C29, C31 andR63 ensure that
any transient switching spikes do not activate the comparator.
The output from Ml 6-6 is. compared with ±1.22V in comparator
M17.
On DC voltage ranges of l V and higher, the current taken by the
instrument load develops a voltage across resistor R56 (page The open-collector comparator Ml 7 is wired to detect excessive
115-1), which is applied to the resistor chain R31/R30/R36 voltages at Ml6 output (R69 is the common bias resistor).
(page 115-2)0 On lOOmV and lower ranges R56 is shorted out Diodes D26 and D27 set the reference potential at Ml 7-10 (for
by relays RL2-5/4 (page 11.5-1 ), RLll-2/5 and 11/8, and RL14- positive outputs) to + 1.22V, and at Ml 7-4 (negative outputs) to
2/3 (page 11.5-2 ). -l .22V. Under normal operation in low voltage state, the output
voltage lies between -llOV and +llOV, and M16 output is
M13 is an open-collector comparator wired to detect excessive between-1.07V and +l.07V. Both halves of Ml 7 are thus held
voltages across R30/R36 (R31 is the common bias resistor). in the open-collector state.
Diodes D17 and D18 set the reference potential at M13-3 (for
positive outputs) to approx. +285rn.V; and at MI3-6 (negative ]f the DC Pffi(V) voltage exceeds 125V (or for an AC peak
outputs) to approx. -285mV. Under normal operation, when !the corresponding to a sinew ave RMS exceeding 90V), either Ml 7-
output current is less than 25mA, both halves of Ml 3 are held in 7 or Ml 7-12 pulls towards logic-0. Current source Q2 permits
the open-collector state. only 3mA to flow in Ml 7 output circuit, so !the voltage input to
D6 cathode and Ml2-ll (B trigger) suffers a negative-going
trigger edge.

7-4
2lo Eflfed of Ovell'Vi(i)U!'lge l[J)]lli DC V IDliltage Ramge:, PHI and PLO pass into the Mother assembly via at 18-25 and 18-
29 respectively.
For DC outputs the 'Q' output of M12 is permanently held at
logic-I by DC FNC'f at M12-13 setto logic-0, so the effect IT no Current, Ohms or Current/Ohms assembly is fitted, a Link
of the negative-going transition at M12-11 is supp:resseil PCB (Part No. 410288) is fined in its place. This shorts:
However, diode D6 conducts, pulling t_he HV ST line at 15- 18-25 [PHI(V)] to 18-8/9 [PHI],
105 to logic-0 (-15V). This is passed to the CIPU, via the 18-29 [PLO(V)] to 18-16/l?[PLO].
status register in the reference divider and the serial data
These connections do not involve any switching.
interface.
The CPU is now awru-e thBJ the DC output voltage exceeds 1.3U?L2 Hl~Otu1~W #1,"~@(;'l>W,!Fitll\f
11 OV. The CPU has to make a decision, as to whet_her the (Circuit Diagro.m430604 page 11.16-1)
programmed output voltage and the detected state are
compatible. ff High Voltage state has not been commanded, PHI and PLO enter at 18-8/9 and 18-16/17 respectively.
a fault is assumed and FAIL 2 message is presented on the PLO passes through the common mode choke L1 via J23-3 and
MODE display. then J26-4 as 'I-' to the Terminal Board assembly.
PHI is switched by relay RLL ][f Remote Sense is not selected,
ll:Do Effed of Ovell'Vl[J)litage ([])JIB AC VIDliltage Rallilge:, RLl is un-energized as shown; disconnecti..ng PHI from the I+
For AC outputs Lhe DC FNCT signal is inactive atlogic-1, so terminal circuit, and shorting it to the sense SHI input line. When
M12-13 atlogic-1 removes the reset. Monostable M12 is set in Remote Sense, RLl is energized and PHI passes through the
to produce a logic-1 at its Q output (Ml2-9) unless its B common mode choke L1 via 123-1 and 126-1, and as 1+' to the
input at Ml2-ll is edge-triggered negatively. In 'Low Terminal JBoard assembly.
Voltage State' conditions no trigger is given, so l\/112-9
remains at logic-1, D7 and D6 are reverse-biassed and the 7'o!3L8o3 Term!l1lai !Bloaiwdl
HV ST line remains at the logic-1 level of OV. (Circuit Diagro.m 400995 page 11.17-3)
When the comparator output switches to logic-0, D6 conducts I+ and I- are filtered and passed to the front panel terminals.
instantaneously to obtain the earliest possible reaction LO the ferrite bead El and C2 protect the internal circuitry from the
overvoltage. But as this is a peak value, the HV ST signal effects of HF pickup in the external circuit.
would revert LO logic-1 without monostable Ml2. Ml2
produces a logic-0 (--15V) pulse of 140ms duration, which
forward-biasses D7, and the HV ST line transmits a logic-0
pulse of 140ms duration. Successive positive or negative
"ilV
peaks of overvoltage retrigger the monostable, maintaining
its Q output (and thus the HV ST signal) at logic-0. 7'o3J3Jo1 Teirmil1lai Boaird
(Circuit Diagram, 400995 page 11.17-3)
ff Remote Sense is selected, the front panel sense terminals Hi
and Lo ru-e connected externally to X+ and I- respectively at the
The power and sense lines from 15-20/24 connect to the model load. The sensed voltage is filtered by JE2 and C3 to reject
4600 analog bus via relays RL2 and RL3. When the 10A range external HF pickup. Except on the 1000V Range, a signal ('R-',
is selected, these relays are dosed and the front panel terminals 'R+') originates as 'TERM lFlLTJER' in the Reference Divider to
isolated using relays on the Current/Ohms Assembly. four wire energize relay Kl, which introduces capaciLOrC 1 to augment this
sense is used, and the 4808 drives the ruialog bus with a -lOV to HF rejection.
+lOV signal that l:he4600 will convert to a-lOA to+ lOA signal.
The4808 guard is transferred to the analog bus by the changeover
relay RL4. The analog bus also contains a grounded signal
ANABUSON which is used by the 4600 to detect that the 4808
is connected to the malog bus.

t'o3J3o1 Current, Ohms or C11..1rrei11t/Ohms

Assembly
(Circuit Diagram 401008 page 11.8-6, Circuit
Diagram 401047 page 11.8-8 or Circuit Diagram
430614 page 11.8-1 respectively)
With a voltage range selected, relays RL8 andRL9 on the Current
or Curreni:/Ohm.s assembly are un-energized as shown. On the
Ohms or Current/Ohms assembly, relays RL24 md Rl.25 ru-e
also un-energized. Voltage Output relay RL23 is energized;
connecting PHI(V) to 18-8/9 as 'PHI', md PLO(V) to 18-16/17 as
'PLO'.

7-5
7.3.!it2 Mother Assembly 7.3.9.4 DC Assembly
(Circuit Diagram430604 page 11.16-1) (Circuit diagram 430536 Page 11.5-2)
Lo passes through the common mode choke and directly to the In normal 4-wire operation (Remote Sense selected) with
Current assembly at J8-18 as SLO. OUTPUT 'ON' on the IV and lOV Ranges, relays RLlO, RLll,
RL14 and RL15 are energized.
Hi also passes through the choke and enters the Current assembly
as SHI at J8- l 0. However, if Remote Sense is not selected, it is SHI(V) enters from the Mother assembly at J5-20 and is passed
shorted to PHI by relay RU for two-wire connection. RLl is directly through RL15 and RLl Ocontacts, IA fuse F2, and to the
energized from the REM SENSE +ve and-ve lines from the DC range relays as SHI(DCV).
assembly.
SLO(V) travels via RL15 and RLl 1 contacts to the range relays
as SLO(DCV).
7.3.9.3 Current Assembly; Ohms Assembly or
With Remote Sense not selected, relay RL14 is unenergized.
Current/Ohms Assembly
RL14-9/8 short SHI(V) to the power Hi output PHI(V).
(Circuit Diagram 401008 page 11.8-6;
RL14-2/3 short SLO(V) to the power Lo output PLO(V).
Circuit Diagram 40104-7 page 11.8-8 or
Circuit Diagram 430614 page 11.8-1 respectively) Refer to Page 11.5-1.
With a voltage range selected, relays RL8 and RL9 on the Current SLO(DCV) is referred to Reference Common-1. SHI(DCV)
or Current/Ohms assembly are un-energized as shown. On the passes to the contacts 8/9/10/11 of energized lV+lOV range
Ohms or Current/Ohms assembly, relays RL24 and RL25 are relay RL4, and via R77 to the inverting input of the Error
also un-energized. RL23 is energized; connecting SHI into the Amplifier.
Mother assembly as 'SHI(V)' via J8-26, and connecting SLO via
N.B. Although the relays are referred to above as 'energized'
J8-30 as 'SLO(V)'.
and 'un-energized', this is not strictly true as polarized relays are
If no Current, Ohms or Current/Ohms assembly is fitted, a Link used to dispense with the power needed to hold the relays in.
PCB shorts:
This distinction is not significant to the present text, but is
J8-10 [SHI] to J8-26 [SHI(V)], discussed later in Section 7.11 where the relay logic is detailed.
J8-18 [SLO] to JS-30 [SLO(V)].
The connections involve no switching.

7.4 1OOmV RANGE

The 1V Attenuator and 1V Buffer are connected into the circuit The other connection to the load returns via the Lo terminal,
as for the 1V range. Relays RLl and RL2 are energized. The arriving at the DC assembly as SLO(V), referred to Common-1
output from the 1Vbuffe:ds connected to the star point atTP5 by (page 11.5-1). Contacts 2 and 3 of unenergized Remote Sense
RU -7/12, and RL2-5 /4 connects the Common-2 star point, at the relay RL14 connect the SLO(V) line to the PLO(DCV) line, and
base of the 100m V Attenuator, to Reference Common-1. Thus through the overcurrent sense resistor R56 to Common-2A.
the 1OOmV Attenuator is connected ocross the l V Buffer output. However, no overcurrent sensing is available on ranges below
1V, as R56 is shorted by the RL2-5/4 connection between
The TP5 starpoint is connected directly to the lError Amplifier
Common-1 andCommon-2Aatthebaseofthel00mV Attenuator,
inverting input via RL2-9/8 and R77, completing the sense
and the contacts of the energized RLl 1 and un-energized RL14
feedback. The Error Amplifier adjusts the voltage at TP5 until
(page 11.5-2).
the error is reduced to zero; the TP5 voltage thus converges to that
of the attenuated DC Ref at RL16-4. N,B. Although the relays are referred to above as 'energized'
and 'un-energized', this is not strictly true as polarized relays are
The output of the 100mV Attenuator, at the TP6 star point, is
used to dispense with the power needed to hold the relays in.
therefore one hundredth of the DC Ref voltage, and can be varied
between -200m V and +200m V. Note that the full DC Reference This distinction is not significant to the present text, but is
voltage resolution is available, so that the 100mV range resolution discussed later in Section 7.11 where the relay logic is detailed.
remains at 7 1/2 digits. This is reflected in the resolution of the
OUTPUT display on the instrument front panel.
The 1OOm V Attenuator output passes through RL2-2/3/10/l 1 to
join the PHI(DCV) line. On ranges below l V the Remote Sense
relay RL14 (page 11.5-2) cannot be energized; so with DC
Voltage and Output ON selected, the lOOmV range output is
routed via RL14-9/8 and the SHI(V) line on towards the Hi
terminal on !he front panel for 2-wire connection.

7-6
These ranges use the seitings as 1ODmV Range, so the Because of this scaling, the resolution available on these ranges
output voltages remain at 1/100 of the DC Ref The is n,-,,n1·w,r1,cm the scaling ratio. The displayed output
differences lie in the spam; of DC Ref voltages used. isw,..m,m,.ucamy adjusted according to :range selection:

To achieve the correct DC Ref spa_n, the is lOV, lV and lOOmVRanges 71/idigits
computed digitally and the 4-byte bb:wry words set ir1 Lhe 13-bit HlmV - 6¼ digits
a:nd 12-bit comparator latches of the Interface. The DC lmV Range - 5 1/2 digits
Ref spans are scaled as follows: Ra_nge - 4¼
lOmV -2V to +2V
lmVRange -200n1V to +200mV
100µ,V Range - -20mV to +20mV

The output from the line buffer Ml4 on the DC assembly (the
signal 'DC lOV + lOOV + lkV ERROR') enters t.h.e PA assembly at
J9-40, passing to the input oft.he 10V Power A.rnplifier via DC/
The DC Ref signal is derived as for the 1V range, entering the DC AC selector RU-11/13 and lOV selector RL3-9/13. The
assembly at the same pins: JS pins l, 2, 31'u1d4. Relay RL18 again signal is attenuated by Rl 71 and Rl24 in a ratio of 4.17:1. So a
connects the power and seru;e lines to the two star-points TP2 and positive full range DC Ref signal of + lOV from the Reference
TP3, TP3 being the signal Common-1 poi.,t. Divider avpears at J9-40 as -SV, and is further attenuated by
On this ra_nge, RL16-8/9 connects full DC Ref to the non- Rl 71/Rl24 to approximately-1.ZV across Rl24, which refers it
inverting input of the En-or Amplifier, which operates as for the to Common-2B. The amplifier is best regarded as having
1V range, except that the span of voltages is now the full -20V to separate DC and AC paths.
+20V.

1 The DC pat.h is blocked C56; Ml 7 is the DC input buffer,

connected as an integrator with diode c13!IT!ping. M 19 operates as
an inverter in open loop, so applies high DC gain to the output
The Error Amplifier output is blocked from the 1V Buffer by the £mm Ml7 on Ml9-2, referred to Comnwn-2C by Rll2.
open contacts 10/11 of RLl 6. Instead, it is connected by RL6-6/
4 as input to M14. The output from M19 drives both halves of the symmetrical,
ii,verting, discrete power amplifier through current-limiters Q21
For the lOV and lOOVranges, Ml4 is connected as an inverti.ng and Q24, and is buffered by emitter-followers Q22 and Q23.
+2 line buffer by the un-energizedrelay RL6-6/4 and 11/13. For Common-emitter devices md Q29 form a voltage amplifier,
t.h.e lOV range, Ml4 output passes to the Power Amplifier driving the complementary output stage Q32 and Q33. Resistors
assembly via JS-73 and the Mother assembly. Rl 19 and Rl20 set the gain of the discrete stages to approx. 4.5.
The forward amplification contains three inversions, negative
DC feedback being applied to Ml 7 inverting input by R122,
defining an overall gain of 10 in conjunction with input resistor
(Circuit Diagram 430618 pages 11.9-1 and 11.9-2) Rl23.

The discrete, complementary, lOV Range buffer-amplifier is a For DC range selection.•, the DC error signal is applied at Ml 7-
dual-purpose circuit, generating power to the output ten-ninals for 2, is amplified by 10 and output atTPl 1 via the low DC resistance
both DC and AC functions. of UL The forward voltage gain, from the output of the Error
Amplifier ltO the output of the l OV Buffer, is thus of the order of
As it provides the full output current, it is located on the Power 1.2. This is more than sufficient to support the specified output
Amplifier assembly so that the heat from its power stage can be current, when corrected to the demanded output voltage by the
developed outside the thermally-shielding Chassis assembly, sense feedback to the Error Amplifier.
and dissipated by forced-air cooling from the fan. Its output is fed
back to the DC or AC assembly for range and output switching, In AC operation, the effect of the DC path is to sense and correct
as !he 'DClOV+lOOV' signal. the DC offsets throughout the whole AC amplifier, referring the
output to Cornmon-2A at Ml 7-3.

7-7
7.6.3.2 AC Path 7.6.3.6 10V Buffer Output
The AC path is blocked by the integrator Ml 7, but is applied to For DC and AC lOV ranges, relay RL3 is energized.
the non-inverting input of M19 through the coupling capacitor
For DC, RlAisun-energized, so the lOVBufferoutputpassesvia
C56. Ml9 operates in open loop, applying its output to the
RL3-8/4 and RlA-4/6 as the 'DC lOV + 1OOV' signal, Jl 9-19/20 to
discrete power amplifier (see para 7.63 .1 above).
the Mother assembly, and thence to the DC assembly.
The amplifier AC gain is also set to 10 by Rl22 and Rl23, the
For AC, RL4 is energized, diverting the lOV Buffer output via
circuit time constants being selected to allow overall instrument
RL4-4/8 as the 'AC lOV+ lOOV' signal, and out at Jl9-15/16 via
output operation over the full frequency range of l OHz to 1MHz.
the Mother assembly to the AC assembly.

1.Q).3,7 10v Ampmieir Powell'

The lOV FLAG line, connected to D71 cathode, is pulled up to Ml 7 andM19 aresuppliedfrom±l5VCommon-2Arails, but the
OV (in-guardlogic-l)by7.2kn(Seepagel 1.9-5 -Rl54inparallel discrete amplifier receives power from the ±38V supply, which
with R38). An Error OL message results from this line being is also used for the Error Amplifier on the DC assembly.
driven to logic-0 by Q34. During DC operation, relay RL8 is un-
energized, configuring the collector loads of emitter-followers
Q32 and Q33 as low-pass filters. This de-sensitizes the overload
7.6.4 RANGE SWITCHING (DC Assembly)
detector and the overload limiters Q28 and Q30 from the effects (Circuit Diagram 430536 Page 11.5-1)
of transient currents. The DC lOV + lOOV signal enters the DC assembly from the
Overload detector Q31 reaches Vbe threshold when the DC Mother assembly at JS-37/38, and R73/L6 filter out any spikes
current value in Rl39 and Rl41 exceeds approximately 35rn.A. picked up in transit. Relay RL4 is energized, shorting the high
Similarly, Q34 detects currents inR147 andR149. In either case, voltage resistor R67, so the signal goes directly through the
Q34 conducts, pulling diode D71 cathode down to -15.7V. This lAmp fuse Fl to the lV+lOV+lOOV star-point.
drives the lOV FLAG line to logic-0, so the status message is
returned to the CPU via the SSDA serial interface, and the 7,6.5 REMAINDER THE 1
'Error OL' message is displayed_.
From this point, the 1OV range loop follows the same path as the
This does not preclude further increase in output current, but 1V loop, both outwaxds to the I+ and I- terminals and back to the
under these conditions the insLrument accuracy specification is Error Amplifier inverting (sense) input. Of course, on the lOV
not guaranteed. range, the relllming sense signal is compared with the full
During AC operation, relay RL8 is energized, the filter is removed, DC Ref voltage, rather than the attenuated DC Ref for the l V
and the Overload Detector is adjusted to operate as a peak current range. (Refer to sub-section 7 3; from para. 73.6 onwards).
detector. Rl 72/Rl41 and Rl 73/Rl47 cause the lOV FLAG to
activate for RMS values of output sinewave current in excess of
approximately 80mA.

If the DC output current increases to approximately 39mA, the

current in either Rl39 or Rl49 causes the Vbe threshold ofQ28
or Q30 to be exceeded, shunting l:he base current of the
corresponding voltage amplifier. Thus the output drive to the
final stage is limited.
In AC operation, if the RMS output current increases to
approximately lOOmA, the peaks of current cause the Vbe
thresholdofQ28 or Q30 to be exceeded. The output drive to the
final stage is limited at this level.

7.fiio3,5
The output current passes through the combination of R144 and
L8. At DC and low frequency AC, the inductor provides a low
output impedance, whereas at high frequencies the resistor
stabilizes the amplifier when driving capacitive loads.

7-8
The Ln.strurnent i..t,cludes two high voltage DC ranges. T11e 100V JF([)]i' Hne ]_!))«Jc!))V t.he DC reference is first converted to
ranges extends from -200V to +200V full scale, the 1000V range a 16kHz AC signal, amplified in the same lOOV an1plifier,
from -1 lOOV to +1100V full scale. then stepped up to 1000V range voltages ilirough a separate
transformer. Subsequent high voltage rectification, filtering
The simplified block diagram of Fig. 7.2 illustrates the high voltage
m1d n, .. ~,,,,,,,-,rn·m converts the AC output from the
DC circuit arrangement and signal flow. Details of the lOOV and
transformer secondary Lnto a DC voltage. A separate line
1000V raI1ges are described in Sub-sects. 7.8 and 7.9.
conveys the lkV I3u"'lge voltage back to Lhe DC assembly for
range switching and output from the insttument.

Both ranges employ the same referencing arrangement used for HiGH E
the l OV DC Range, but the techniques necessary to generate high
A guarded high-voltage switched precision attenuator reduces
voltages differ from those in the low voltage loops:
the DC sense voltage from the Hi and Lo terminals to Reference
lFor Une WOV Rmmge, a VMOS circuit amplifies the ±20V levels. The attenuated sense voltage is compared with the
Reference directly, as a DC signal, powered from a separate DC Ref voltage, their difference being used as an error signal to
±400V supply. The 1OOV range voltages a:re passed back via correct the range output level.
the range switching circuiLry in the DC assembly to be output
from Lhe instmment as for the low voltage ranges.

10\Jf'i"J
Ati.nmJotar

-e-u--t-t-------<r-">_10_,v2,,=ls)--4""..------vw ,cov

FffG. '1.2 DC HHGH VOLTAGE !LOOP SHM!PU!FBED BLOCK O

7-9
7.8 1 OOV RANGE
7 Jt1 iNTRODUCTION 1 OOV AMPUFIER
The 'lOV+lOOV+lOOOV DC ERROR' signal, generated by the (Circuit Diagram 430618 page 11.9-3)
+2 DC Error Buffer in the DC assembly, enters the Power The lOOV amplifier is in three stages:
Amplifier as for the lOVDC range; but the lOV Amplifier is
G2in Stage: this is similar to the first stage of the lOV
bypassed for the high voltage ranges.
amplifier, but with a different distribution of gain.
On the lOOV range, the signal is switched directly into the 100V
])rr!verr §t~ge: providing most of the gain, this stage runs
Amplifier, where it is scaled up a factor of -20, the a_rnplifier
from a regulated 400V supply.
output being delivered via the 'DC lOV+ 100V' line to the
PID(DCV) line on the DC assembly. Thereafter the output is Buffer Output Stage: complementary MOSFET circuits,
transferred to the instrument terminals as for the lOV range. located on the positive and negative heatsinks, provide a
single-ended output with the required voltage swing, at low
impedance.
7.8.2 100V RANGE POWER ROUTING
The voltage gain for the whole 100V amplifier is set at 100
7.8.2.1 DC Reference and Error Amplifier by the input resistors R74/R71 and the feedback resistor R88.
(Circuit diagram 4]0536 Page 11.5-1)
The 100V amplifier is also used for 1OOV AC outputs, and on the
The DC Ref signal is derived as for the l V range, entering the DC DC and AC 1000V ranges to drive the step-up transformer. For
assembly at the same pins: JS pins 1, 2, 3 and 4. Relay RLl 8 again this reason the following description is applicable to both DC and
connects the power and sense lines to the two star-points TP2 and AC signal processing, and will be referred to in the sub-sections
TP3, the latter being the signal Common-1 point. dealing with those functions and ranges.
On the lOOV range, RLl 6-8/9 connects the full DC Reference to
the non-inverting input of the Error Amplifier, which operates as 7.8.3.1 Input to Gain and Driver Stages
for the 1V range, except that the span of voltages is now the full (Circuit Diagram 430618 pages 11.9-2 and 11.9-3)
-20V to +20V. The DC ERROR signal enters the PA assembly at J9-40, passing
to the input of the lOOV Power Amplifier via.relays RL4-ll/13
and RL2-8/4. It is referred to common 2B by developing a
The Error Amplifier output is blocked from the 1V Buffer by the voltage across R72.
open contacts 10/11 of RLl 6. Instead, it is connected by RL6-6/
4 as input to Ml4.
For the lOV and lOOV ranges, Ml4 is connected as an inverting MlOis the DC offset integrator, with diode clamping. It provides
+2 line buffer by theun-energizedrelay RL6-6/4 and 11/13. For a DC input to the non-inverting input of the voltage gain amplifier
the lOOV range, Ml4 output passes to the Power Alnplifier M8, controlling its DC offset. This is similar to the arrangement
assembly via 15-73 and the Mother assembly. in the lOV Amplifier.

7.8.2.3 Powtn Amplmell' and Qi!,jjtp1Ut Ro1UJU1!11!;;1

(Circuit Diagram 430618 page 11.9-2 and 11.9-3;
and Circuit Diagram430536 page 11.5-1)
'DC Error' enters the Power Amplifier assembly at J9-40 (refer ID
page 11.9-2). Relay RL3 is un-energized, shorting the lOV
Amplifier input; and RL4 is un-energized, routing the DC Error
signal to the 100V Alnplifier as signal 'lOOV VP' (page 1109-3 ).
Energized relay contacts RL2-3/4 apply the signal to the Gain
Stage, which provides drive to the power 8!liTlplifiern in the
positive and negative heat sinks, via B-12 and B-11. The single-
ended output from the heatsinks at B-9 passes via R89, L 7 and
relay RL2-13/9 (RL2 energized), to RL3-6 (page 11.9-2 ), md
onto the 'DC lOV+lOOV' line via RL4-4/6, R174 mdl 19-19/20.
On the DC assembly (page 11.5-1), fue signal is muted to the
PHI(DCV) line as for the lOV range.

7-10
into a
AC signals to reach the -40{fV levels '"""'-''J'-"~v
driver ~/IOSFET ouiput c]xcuit Diodes D44~ D43 and D36
prevent negative latch-up.
Zener diodes D60 imd D61 divide the across C49 and
VoltageRegulatorM21 sets its 1 to+l2V. Common-eminer
buffer drives the capacitruice of source-gate from the
output ofM8, forming a CllScode crnment generator. The drah, of
p-channel MOSFET Q8 passes the signal current to the mirror The to be switched
Ql2/Ql 1 at voltages close to the negative 400V rail. off, D56 to assume forward bias, tlms connecting the
rail to ihe +38V This facility is rnade available to reduce
The cmrent-rcJrror output transistor Ql 1 is also i.-i GllScode with
ac:ross R65 and hence its continuous po1;ver
9
its 1JSsociated MOSFET Eminer resistor R53 defines the
a DC output of negative
currentinQ9, therntio R52/R53
is turned off for AC eRd DC outputs,
MOSFE'fs are inherently ca1oru;iti.ve so me:,isurns 8.Ye taken to the 'lPOSITfVIE' from the processor set to logic-1
nullify the effects, on slew rate, of fue ca1pa(;1t1.ve cunents ThusM16-·6 is isolatedfromM16-5, and the +400V :rnilom
between electrodes. 'Ine cascode arrangement eru;mes Lhat '""·"'':~1,uc,.,. For negative DC outputs, the
any source-gate and source-drain currents the cathode of !:he LED in M16 is to (the JPOSITIVE
main flow of source cur,ent imd have little effect on slew irate. set i:O -15V on l\/H6-3 - see page the LED
em.ics, and Ml6-6/5 shorts out D54
supply for mo1<acH., outputs is then limited to 438V.
,,~···~··--.,,,., AC currents between w«w.-'"''""''°
electrodes which nornwlly pass into the circuit. fa tl'lis At HF, inductor lL6 appears as a current source,'"'"·"·"'°'""' the
l.iiTiL]}c,Ol8!11C:e of drain load Vvitl1 frr-,,m,"""'' to comperi_,;ate for
bias of about 4 vohs
TI.aese n1easures rrILinimize theredu.ction

R5 l and D42 m.,=e,<m, bias, md D51 protects i:he

CT

bias circuit 'fhe hlgh-puwer resistor R49 ;refers fue bias circuit
to Com,,ion-2, and C26 stabilizes the base-emitter bias of
'fhe driver its whlch cm1 involve p:eak-
brna...k:down. of up to 600V, acmss the load :resistor R65.
Zener diode D41 is included to the ouiput in the event of
This is "".,'""'"'-'Y held below
At Full Scale on fue lOOV AC :rn.,'1ge, the oul.p:!.iit from !the driver
is 200V RlwS. This drain ro
voltage swing approaching 600 Volts, as !there is no CU.This
in !the heatsink power "°'"'f'"UKS,Mo 'flne
provides current fuerefore needs special ''"''""u'""'
The ±400 volt supply is at this urnre;;~;imne;;,u, so can contain
via ro a low i.rntpt,at111u;e;; pDh,t in the Negative Heatsink
line ripple md level variations, this noise level being critici.ll to ru;sembly which follows !the driver ouiput voltage swing.
ili.e output perfomumce, To define a stable supply voltage, a DC
restoration circuit is employed as a trough detector, maintlii.iuning
a level about SV below fue most negative excursions of the ripple.
1Jt4 100V POWER AMPUFiER
(Circuit Diagrams 430637 page 11 .13-1 and Circuit Diagram, 430539 page 11.13-2)
The 1OOV powe:r amplifier stage is split between the Positive and to four points of application to the heatsink. The gates and
Negative Heatsink assemblies. The driver output voltage is Q2 receive their drive from ihe output line, obtained via the
connected into the Positive assembly, and the frequency divider RHi/R22/R23/Rl5. Capocitors ClO and C13 decouple
compensation feedback is de:rived in the Negative assembly. any noise on the 400V rail; Cll and Cl2 correct any lag which
may be generated by ClO and C13. CS and C6 control ihe
TI1e whole circuit is a complementary, single-ended push-pull
division ratio at HF, swamping any stray capacitance.
amplifier wiLh unity voltage gain. 1'0 achieve the full 300V peak
voltage output, two MOSFET source-followers are connected in 'fhe drains of Q3 and Q4 are shorted together, and connected via
cascode, for each pofa.rity, in a totempole arrangement H-5 by a 1OnF capacitor to the corresponding point in theNegative
Heatsink, completing an AC bootstrap (BS). The gates ofQ3/Q4
To obtain the required peak current levels, each source-follower
(Jl -1) and Q l/Q2 (Jl-4) are similarly linked to their corresponding
consists of two MOSFETs in parallel. In all, therefore, eight
points in the negative heatsink. This ensures that AC swings in
MOSFET devices are used.
both polarities are identical.
On 100V ranges, the output currents are such as to bias the
The combined output from the Positive and Negative Heatsinks
amplifier in class A, but on 1000V ranges the output currents
is transmitted back to the Power Amplifier assembly via the
inlpose class AB conditons. Crossover distortion is minimized
screen of the input connection.
by a regulated bias, generated by a V gs multiplier (Ml in the
Positive Heatsink assembly).
70804.2 Negative Heatsink Assembly
Power for the amplifier is provided by the same ±400V supply (Circuit Diagram 430539 Page 11.13-2)
that serves the driver circuit. To minimize internal temperature
by improving efficiency, overall power loss is reduced by This is virtually a mirror image of the Positive Heatsink circuit.
regulation only where required. Thus only the driver stage is However, because the P-channel MOSFETs are operating closer
regulated, allowing the power amplifier to take power directly to their maximum voltage rating, they are further protected by
from the unregulated supply. Being source-followers, the ripple Zener diodes which linlit their drain-gate potentials.
on their 400V rail is not transmitted. The HF swamp capacitors are not required, as the whole circuit
is AC~bootstrapped to corresponding points in the Positive
1 ~8)jt 1 Pos~thre Heats~rn~ /ll\"'"""'"rm, Heatsink assembly, via Cl, C2 and C4.
(Circuit Diagro_m 430637 Page 11.13-1) HF compensation for the driver and output stages is derived at
N-channel MOSFETs Ql and Q2 are connected in parallel, as irre low impedance from the junction of R2 2!11d D12. it feeds back
Q3 and Q4. All devices are matched for power dissipation md via J2-7 to the driver output circuit, Cl2 in the Power
threshold voltage for an even dissipation of approximately 400W Amplifier assembly, to avoid capacitively loading the driver
between the two heatsinks. All gate-source potentials are limited output line.
by lOV zeners.
The input voltage from the driver is present at B-11 and B-12.
Most of the driver load current passes through the bias buffer Q8, The two NTC thermisi:Ors in each heatsink circuit are part of a
a..-1.d the voltage developed across Q8/R21 is applied to the birui bridge network which detects excessive temperatures on the
control RlO. The V gs multiplier Ml/Q8 octs as a high gain shunt heats inks. The action of the bridge is described in Section 7.12 .9.
regulator, generating a bias of between 5V and 9V, set by RlO.
The regulator's O'WTI bias chain of Q9, D8, and QS (which is 1,8o4lii!l 100V
connected as a diode) responds to the temperature of the heats ink
to compensate for the temperature coefficieni:s of the MOSFlETs. DANGER.!
lFORGl!JARDJINGIP'URPOSIES, TlH[lE01!.J1flf'1U1I'lFROM1fHlE
The 'DRIVE-' voltage at B-11 is traru;ferred directly to the
lH!lEATSINKS ][§ TRANSMITTED BACK TO JTJ-9 OJF THE
negative heatsink input via H-7 (Circuit Diagram, 430539 page
11.13-2).
JPOWER AMPJ!..J!FIER A§SEMB!LY ALONG TlH!E SCREEN
OJF THJE INJPUJI' CABJLJE, TlH!lE VOlLT AGES ON 'fffl§
The 'DRIVE+' voltage at B-12 is buffered by Q7 m1.d applied to SCREEN ARIE lP'OTENTlIALlLY LETIH!ALo ll.JTMOS'JI'
the gates ofQ3 and Q4. In the event of an output short-circuit, Q6 CAUTHON SHOULD BE EXERCISED WHEN WORKING
detects the output current as a voltage across R14, imposing a IN 'll'JH!E!R VICINIT'lt'o
hard limit of 1.5A by reducing the signal voltage at the input to
the MOSFET gates.
The series gate resistors R5 and R6, together with thei.Y associated The 100V Amplifier cm work whh the heatsinks removed,
drain-gate capacitances, form the dominant pole of the 11mplifier, because of the clmnp diode (D41 on page 11.9-3) in series with
Dmnping resistor R19 with fem~ bead JFB1, prevent local the driverload. H they !!le removed, however, B-9 imd 13-11 in
oscillatiom in emitter-follower Q7, the disconnected :rocket of J3 must be connected to~:ett1er, to
Q 1 imd Q2 act as buffers to provide a 'bootstrapped supply for the maintain the feedback. Jin fu.is coi1dl1tio11, the falls due to
output devices Q3 and Q4, splitting the overall power dissipation loading of the driver resistors in the DC or AC assembly.
 Zener Diode JD8 protects the soilloe-gate cITcuit of level-shifter
a cu:rrent of l .4n1.A.~ as
to the current-monito:r reference zener diode D7.

via D7 so
±38;\7 Comffimmolffi,,,2
for the lOV PovveI r!,J1nr.,rn.1<,> but also for
negative D C outputs i_r1 tl1e lOOV 1\:rnp1ifier driver~ this
1

held in com:luction R8, Rl2 and D2. The current is sensed by

supply is ""''"'"'·0 ~ 1-.Pn on the separate 38V Power Supply
the parallel combination of resistors Rl 7 and R32. Although the
assembly 430653 page
pea..ks of the cummt taken by tihe power runpHfier can reach 1.4A,
the supply circuit is situated cm t._he Mother i-'1.£,seimc;1v.
tl1e mean value is less than 0.5A. Ripple currents m2Llci..,g up the
±41l!DV ]P([!)wer difference are smoothed the main reservoir capacitors C31
TI,e 100V Power Amplifier used for the lOOV 2111d 1000V and C22 on the Power A,mpHfier assembly (page 11.9-3 ).
ranges, for both DC and AC outputs. The line traru;former
For mean currents more i:han mJJ:mJxht1a«olv 0.5A (in particular
secondary output is rectified and smoothed on the Mother
for oulput short-crrcuits); the sensed across R17/R32,
a_nd themainregulator circuitry for the driver stage
subsequently divided tl11.e attenuatm: R10/R9, exceeds the
is contained on the Power / Cu:rtent Heatsir>Jc. The
tl1reshold of conducts to pass current in.to R8,
lOOV Amplifierreceivesumegufated
gate, so the voltage at D5
rises to 56V, zener
D5 conducts base down, further reduci..,g the drive
to gate. Tius cumulative oction is slo1ved only by the ti..'T!e
constant of 111.e combination R34/C15, so that both @mi
The line current on the line 2:,re sunu1wneot1s1y closed dovvn.
4.01:JV overload, the crrcuit ca.u--iot reoover
±38V Power as1;en1bly This ~,~1~u,m.!ru from this "foldback'mode. However, lhe-40-0V
AC ou1:pnt for the 'Com.1-no11 Mode }foll' b°'f;·,.;;,,~i"G,_,; is moilltored. If U1e '-:{KllV n1onitor se:nses a faih.Jrre? a starus bit is
A single The CPU makes
m1d negative raw
the ±38V Power "'"''"'111u,,y The ±38V
described in Section 6.7, para 6.7 3 .4.

7JBU:5,~ ±~OOV Tli'©liru~-«©li'm@li!@ui/ ~®©~i~l©~U!@fit

U'-1).1'/f"OWI. 430604- ~ OOV C'-Jill'li'@lnlt
O~@NfiJJ!i$ [ii~t@©~©li'
The mains "'"'""'-'J!Ru,w.1 centre tap is :referred ID
Common-2 on i-J'r1e Mother assembly. The secomJla:ry is switched
with the seco1m1m fo:, t._he 38V to allow a lower
to drive the 8!mplifier for §ervicing puipo§es. Under A"1·nplit11d11; Control system
conditions Ln the 4708, I.his switch, which is situated in Section 9. However, as the 4COV pll!Ss the
prominently on the Mai.ins Transformer assembly, is set to the circuit for OC high ranges, it is mentioned at this point.
400V µuo><WJ'"-
The enter the Power Amplifier assembly from
A single bridge :rectifier on fue Mo.her assembly wes series the PS/][ Hearninl'\;: at .H-8/6 Bnd are filtered by U 11nd L2 before
diodes \to achieve the high peak inverse voltage~""'""'"'"~@'""" being applied across t,,vo m-;,uu""''"''" LlPl a.,d LP3. T'ae:re famps
required for the 400V supply. are visible from the top and :rem- of L!-ie instrument when the PA
board is e¼no·,~en !l]O!l:Callilg that a danger1Jm voltage is prnsent.
After smoothing, and part-loading by
bleeder :rnsistors also balance the volrages across the capacitors); lines pass on to power !he driver stage of I.he l OOV
the rectifier output is passed via J3 l, to provide both positive and amplifier, where the voltage is regulated as described in sect.
negative raw supplies for the foldback regulator in the PS/][ 7.83.4. The 400V(2)C lines supply tlie power amplifier in the
Heatsink: assembly. Positive and Negative Heatsinks.
On the AC l OOV range, the cu..nrent in each of these lines is used
as im. analog of tlie load placed on the amplifier. (On I.he lOOOV
(Circuit ranges, any overload is sensed by an AC o:r DC ove:rcurrent
When the400V supply is enabled, the LlEDs in opto-isolatorn Ml detector in the DC assembly.) On the AC 1000V Range, the
and M2 are conducting, allowing their opw-transistors to be voltage applied ltO the primary of the step-up transformer is fed
energized. As the circuits for both polarities wre otlierwise via aresis,or to tlie detector atM2-5/9. The '100V AC' line is set
symmetrical, only the positive circuit is described. to fogic-0 (-15V) only when the 100V AC range is selected.

7-13
 POWER AMPUF~ER MOt,HTORS
(Circuit Diagram 430618 Page 11.94)
All three power supply voltages: ±15V, ±38V, and ±400V; are
monitored using similar comparators to initiate individual 'FAIL'
The action is similar to the ±lSV moniror, but because of the
messages. In addition, if either the ±400V or the ±lSV monitor
higher voltage, the divider between the +38V and -38V lines is
circuit detects a low power supply voltage, the ±400V supply is
balanced by two lOW droppers in each line. Without Q5, the
disabled.
2.45V zener bias current would affect the sensing level. By
employing QS as a voltage follower, D25 bias current can pass
directly to the V- rail and still be referred to the R25/R26 junction.
To ensure that failure of eithe:r the±15V or the ±38V supply does The Vbedrops cmcel one another out, so the zener and the
not remove the power from the three comparators, these two sensor R25/R32 are referred to the same potential.
sources are 'OR'ed by D5, D6, D15 and D16 (the ±38V supply In normal operation the voltage across the 7150 of R25/R32 is
being ballasted by Rl and RlS) to provide the V + and V- supply approximately 2.62V, in excess of the 2.45V of D25.
to the Quad op-amp M3. In nine of the possible sixteen states of
failure of these two supplies, power will still be applied to the Ifthe76Vbetweenthe+38V and-38Vrails falls below71 V, the
comparators. The maximum values of V + and V- are limited to voltage at M3b-2 falls below that at M3b-3, and the output at
+16V and -16V by zener diodes D7 and D14. M3b-l changes state from -V to + V. The action of D22 and the
38V(2) FAIL line are the same as for the ±15V monitor.
7Jl6"2 ±15V Monitor
1J3.6.4 ±400V Monitor
Zener diode D29 is the 2.45V reference for the±15V comparator.
Itis ballasted by R27 to V+, and its +2.45V above the -15V rail The ±400V Monitor is in two mirrored halves, each dealing with
is applied to the non-inverting input of M3c. The+ 15V to -15V its own polarity of the supply, so only the positive half is
supply is divided by R29/R30/R33, generating a voltage +2.50V described.
above the -15V rail at the inverting input to M3c under normal Zener D9 provides the +2.45V reference on the non-inverting
operating conditions. Thus the output at M3c-7 remains at the input at M3d-12. The divided +400V is sensed across R16 at a
negative (V-) rail, holding D28 in forward bias, and the 15V(2) normal operating voltage of +3.27V (referred to common-2C)
FAIL line at 19-108 is held at JLogic-0 (-15V). and applied to the inverting input at M3d-13, thus setting the
If the voltage betv,een the ±15V supply rails falls to less than output at M3d-14 ro the -V rail voltage. D20 is reverse-biassed
29 .4 V, the voltage across R30/R33 falls to less than the reference so the 400V(2) FAIL voltage is pulled to logic-0 (-15V) by R7.
2.45V. Theoui:putatM3c-7 changes state to the V+rail,rnverse- the +400V supply fails by falling below +300V, the voltage
][f
biassing D28, so the 15V(2) FAIL line is pulled to logic-1 across R16 falls below the -:--2.45V reference and the M3d-14
byR28. output switches to the+V rail voltage. D20 conducts, pulling the
The logic levels on the 15V(2) FAfL line pass via the Mother 400V(2) FAl[L line at 19-106 to logic-1.
assembly to the Parallel/Serial status registers in the Reference In normal 400V operation R31 is shmted by the 400V/50V
Divider assembly (Ml8-5 on page 11.44). During each control switch on the Maim; (line) transformer, via the 'Lo SUPPLY A'
data transfer, the SSDA also passes the condition of the status and 'Lo SUPPLYB' Hnes. When the switch is set to 50V, the
registers back across guard to be read by the CPU. '\¥hen the Lo SUPPLY A line is connected to -15V, effectively disabling
15V(2) FAfL line switches to logic-1 due to a ±15V failure, this the monitor output by holding the 400V (2) FAfLline atlogic-0.
is detected by the CPU which produces the lFAIL 9 message on
it.he MODE display. The output line gives an input via D3 to the 400V enable logic
(described in Sub-section 7.125). Its effect is as for a ±15V
The ±15V monitor output line also gives an input to the 400V failure.
enable logic (Section 7.12.5). The effect of a±15V failure is to
disable the 400V(2)B :regulated supply via D26 conduction and
Jl-3 at logic-1.

7-14
7.9 1 OOOV RANGE
7 .9.1 INTRODUCTION
7.9.1.1 Power Signal Processing 7.9.1.2 Sense loop
Method Sense Attenlllation
The 1OOOV DC Range obtains its high voltages by using the 1OOV The sensed output voltage from the Hi and Lo terminals is
power amplifier to drive an AC signal into the primary of a step- reduced down to 'DC Ref levels by a guarded precision attenuator
up transformer. The AC signal is derived by modulating al 6kHz on the DC assembly, and then applied to the inverting input of the
reference with the DC ERROR signal. Error Amplifier:
Error Signal Conditioning The Lo terminal and Sense Attenuator Lo are both referred to
Common-1 (DC Ref Lo). The attenuator is dual-purpose,
The '1 OV + 1OOV + 1OOOV DC ERROR' signal is pre-conditioned
being used for both 100V and 1000V ranges. The Hi sense
by the VCA Drive circuitry in the DC assembly, before it enters
voltage is divided in the Sense Attenuators by 10 (100V
the Power Amplifier. The lOV Amplifier is bypassed.
Range) or 60 (1000V Range).
High AC Voltage Generation
The attenuated output is compared against DC Ref Hi in the
The modulated 16kHz signal is passed from the DC modulator Error Amplifier, modifying its output to the VCA Drive.
into the 100V Amplifier, where it is scaled up by afactorof-100,
The lOV Bootstrap, in addition to supplying the Error
the amplifier output being delivered via the 'OUTPUT' line to the
Amplifier, also buffers DC Ref Hi as reference for the VCA
HF Transformer assembly.
Drive circuit.
Rectification airnd Output
JEn-oli Conditioning
The stepped-up secondary voltage is rectified and filtered in the
The bipolar DC error voltage between the buffered DC Ref Hi
High Voltage assembly:
and the Error Amplifier output is converted by a switched
A constant-current source acts as a shunt to sustain the precision rectifier in the 'VCA Drive', to provide a suitable
current drawn from the high-voltage secondary winding unipolar control signal for the DC modulator. The buffered
through the bridge rectifier. Polarity is switched with respect output from the rectifier becomes the 'lOV+lOOV+lOOOV DC
to common-2 via the LC-filtered ±38V common-2 supplies. ERROR' signal which adjusts the amplitude of the 1000V Range
Positive polarity output is referred to -38V at zero output, to outputs.
overlap with negative polarity output referred to +38V. The
!Loo)Pl Attfollil ®lllidl Relfeirernrce StaUllilg
overlap allows digital calibration constants to be used to align
zero voltage output in both polarities to the same calibrated The Sense loop thus stabilizes the 1000V Range DC output to a
zero. value which is 60 times the DC Ref voltage, this value being
determined by the division ratio of the precision sense attenuator.
The main output filter is placed in the output line. This is a
The DC Ref voltage is scaled digitally so that Full Scale of 20V
low-pass filter with a high rejection at 16kHz, reducing the
corresponds to 11 OOV on the OUTPUT display and at the output
ripple voltage to within specification limits.
terminals.
The output voltage is fed out through the Range switch on the
DC assembly, where itis subject to Remote Sense and Output
On/Off switching, before being passed to the I+ terminal by
the same route as forlow voltage ranges. High voltage status
is detected on the DC assembly as described in para 7 3 .7.2
for the 1V Range.
The external current is sunk into common-2 via the overcurrent
detector, which warns the control processor when the output
current exceeds approximately28.5mA(seepara73.7.1). On
the l OOOV range the processor will switch the output off on
receipt of theovercurrentsignal from the overcurrent detector.

7-15
7.9.2 1000V RANGE POWER ROUTING
7.9.2.·1 DC Refere1ru::® and Ermll' 7.9.2.3 ° ROILBftii"llgJ
(Circuit diagro.,m 430536 Page 11.5-1) (Circuit Diagram 430537 page 11.14-1)
The DC Ref signal is derived as for lhe l V range, entering the DC The high voltage output from the secondary of the HF transformer
assembly at the same pins: JS pins 1, 2, 3 and 4. Relay RL18 again is input to the High Voltage assembly between J2-1/2 and J2-8/
connects the power lllld sense lines to the two star-points 'f P2 and 9. Afterrectification, polarir-y switching and filtering, the DC lkV
TP3, the latter being the signal Common-I point. signal is output via Jl-2/3 to pin Lon the Mother assembly,
where it is again filtered before passing to the DC assembly on JS-
On the 1000V range, RL16-8/9 connects the full DC Reference
33/34.
to the non-inverting input of the Error Amplifier, which operates
as for the 1V range, except that the span of voltages is now Lhe full
-20V to +20V. 7.9.2.4 DC Assembly O
Power amidl
Sense Routing
The Error Amplifier output is blocked from the 1V Buffer by the
(Circuit Diagram 430536 page 115-1)
open contacts 10/11 ofRL16. Instead, it passes as input to Ml 5-
5. The error signal is conditioned by the VCA DrivecircuitM15/ On the DC assembly, the DC lkV signallineisfusedat 1AbyF5,
Ml4 and passed to the line buffer atM14-5. For the lOOOVrange, and the signal is routed throughRL7-5/4. At this point the voltage
Ml4 is connected as a non-inverting line buffer by contacts 8/4 is also used to energize the attenuator guard network Rl5 etc. It
and 9/13 of energized relay RL6. M14-7 output passes to the is routed to the PHI(DCV) line through RL?-10/11, then out to
Power Amplifier assembly via J5-73 and the Mother assembly. the I+ terminal and back from the Hi terminal on the SHI(DCV)
line as for the 1V range. The current returning from the I-
7.9.2.2 !Poweir terminal is sunk into common-2 via the overcurrent detector R56
(see para
(Circuit Diagrams: 430618 pages .9-2 and
is range switched on to d1e HV ai.tcnmu.or Rl 7 etc. by
'DC Error' enters I.he Power Amplifier assernbly ~t J9-40 (refer to RIL7-8/9, 111<: reduced voltage being i.akcn off thrnugh RL9-10/11
page 11.9-2) . Refay RL3-9/l l/l3rem2Jinsun-cuc:rgized, shorting ~x1d to the inverting input of the JEnof .Arnplifier.
across the IOV .A.rnpliJierinput. TheDCJEnorsigna! is routed via
linkLK.W andTP14tothe lkV DC ModulatoratR78. Theroute
to the IOOV Amplifier input as signal '100V I/P' via RL4-ll/13
is blocked by the open contacts 8/4 of unenergized relay RL2
(page 11.9-3 ).
The output from the modulator is a 16kHz AC signal at 1'Pl5
whose amplitude is determined by the value of the DC Error
signal. With RU unenergized on the lkV DC this AC
signal passes via JRU-11/13 contacts i:o the '!kV ERROR 0/P'
line.
Contacts RL2-6/4 (page 11.9-3) apply the ro lhe Gain
Stage, which provides drive to the power arnplifiers in the
positiveandnegativeheatsinks, viaJ3-12 andJ3-11. Thesingle-
ended output from the heatsinks at B-9 passes via the OUTPUT
line to the lkV ENABLE relay contacts RL6-8/9 (page 11.9-2 ).
RL6 is energized, and RL7 is unenergized on the DC lkV Range,
so the OUTPUT line is connected to J5-3 (PA assembly) and oUI
as a direct link to ,he High Frequency Transformer a~sembly.

7-16
7.9.3 VCA DRIVE CIRCUITRY 7.9.4 DC MODULATOR
(Circuit Diagram 430536 page 11.5-1)
The attenuated sense signal is applied to the inverting input of the
7.9.4"1 16kHz Derivation
Error Amplifier via RL9-10/l L This bootstrapped, high gain
(Circuit Diagrams:43064-8 page 11.3-2; 430652
circuit compares the sense signal with DC Ref. When both are
page 11.4-5; 430618 pages 11.9-5 111.9-2)
equal; the output at M20-6, the bootstrap common BS at TPl, The 13-bit counter in the Analogue Interface generates 16k:Hz at
DC Ref Hi and the sense signal are all at the same level. Therefore pin 14 of Ml6 (page 11.3-2). This is transferred into guard
the differential input to the error buffer-comparator Ml5 is zero through opto-isolator M3 on the Reference Divider (page 11.4-
at Ml5-6/5. 5 ). The 16kHzsquare wave, switchingbetweenlogic-1 =0Vand
logic-0 = -15V, enters the Power Amplifier assembly on J9-61
The second Ml5 stage acts as a bipolar-unipolar switch which
(page 11.9-5 ).
adapts the bi-polar action of the Error Amplifier to the unipolar
sensitivity of the DC modulator: Providing the lkV range is selected, and the 'PA CLAMP' signal
is at logic-0 (-15V), the full 15V p-p squarewave passes viaM6-
With the front panel Output on+ LED lit, the POSIT1VE
4 and M9-l O to inverter Q4 l (page 11.9-2 ).
control signal is at logic-I (OV). PET Ql conducts, setting
the M15-3 non-bverting input to zero volts, so the amplifier
inverts the input at M15-2. 7o9.4.2 DC Error Signal Processing
(Circuit Diagram 430618 page 11.9-2)
Alternatively, if the Output on- LED is lit the POSITIVE
signal is atlogic-0(-15V), cutting offQ2. Ml5-3 follows the The modulator operates by alternately charging the low-pass
M15-7 voltage, so the amplifier acts as a voltage follower. filter formed by R83, C83 and C84 via the series switch Q39, and
discharging it through Q40.
The gain from Ml5-7 to the I+ terminal is approx. x2000. R87
and C40 at the Error Amplifier input; and R40, C21 on the first The l 6kHz MOD DRIVE squarewave alternates between logic-
stage of Ml4; provide frequency compensation for the overall 1 (OV) and logic-0 (-15V). After inversion in Q41, the signal at
loop. its collector switches between the+ 15V and -15V rails. Positive
half-cycles of the MOD DRIVE signal make Q41 conduct,
For the 1000V range, the secondM14 stage is connected as anon- switching Q40 off and Q39 on, so the DC Error voltage charges
inverting line buffer by contacts 8/4 and 9/13 of activated relay the filter. For negative half-cycles the conditions are reversed
RL6. The output from Ml4-7 passes to the Power Amplifier and the filter is discharged to Common-2.
assembly via J5-73 and the Mother assembly.
111.e DC Error signal is al ways positive, due to the polarity switch
on the DC assembly. Its mnplitude depends on the difference
7 .9.3.1 Act10111 off V/CA lOirive Clircultiry
between the conditioned output voltage and the DC Ref Value,
If a user increases a positive OUTPUT display value, the positive but is limited to + 12V by D75.
DC Ref Hi voltage will increase (this is a demand to increase a
The filter reduces the 32kHz and higher harmonic content of the
positive output voltage). The polarity switch inverts the positive
squarewave, while passing 16kHz with little distortion. Its
input from Ml5-7, so Ml5-1 feeds a negative output to Ml 4.
output is buffered by source-follower Q42, before being AC-
This is inverted at Ml4-l and then buffered by voltage follower
coupled to the l OOV Amplifier by a high pass fiiter (formed
action atM14-7. It is passed via the Mother assembly to the DC
mainly by C86 with the approx. 400Q input resistance of the
modulator on the Power Amplifier assembly as an increasing
amplifier).
positive DC signal.
The near-sinusoidal 16kHz signal input to the 100V Amplifier
In the case of an increasing negative OUTPUT display value, the
has an amplitude which is proportional to the value of the
negative DC Ref Hi value will increase negatively. But now the
DC Error signal, so it acts as an AC analog of the difference
POSIDVE signal is at logic-0 (-15V), so the output from Ml5-
between the normalized instrument DC output voltage and the
7 is not inverted and remains negative as for positive outputs. The
value of the DC Ref voltage. It is based on a mean ofOV, and is
action of M14 is not altered, so an increasing positive signal is
passed as the 'lkV ERROR 0/P' signal viaRLl-11/13 and RL2-
sent to the DC modulator as before.
6/4 into the Gain Stage of the 1OOV Amplifier (page 11.9-3 ).
In both of the above cases the signal sent to the DC modulator is
increasing positively, and this will result in an increasing 16k:Hz
amplitude input to the 1OOV Amplifier. All polarity information
is lost, so has to be re-inserted after rectification of the step-up
transformer output, by the polarity switch in the High Voltage
assembly.

7-17
 1 AMPUF~ER Lf/Hf TRANSFORMER
(Circuit Diagram 430618 page 1109-3 - For SELECTION
description refer to Subsections 7083 and 7,BA)
The two trnnsformern are separately located, their secondaries
This operates as for the 1OOV range, but in this case the DC path being connected into the High Voltage assembly. The HF
simply maintains the zero offset of the AC signal, which is transformer is selected when RL7 is unenergized, its prima_ry
amplified along the AC path. The output signal 'OUTPUT' is being returned to Common-2C. RL7 is energized to select the LF
fed fromJ3-9 to relay RL6 contacts (page 11.9-2) for application transformer.
to the step-up transformer.
For the 16kHz signal used with the 1000V DC Range, the HF
transformer is selected by RL7 being unenergized.
7n9J5 '1kV ENABLE' RIElAY Rl6
(Circuit Diagram 430618 page 1109-2)
HIGH VOlTAGE TRANSFORMER
Relay RL6 allows the OUTPUT signal from the 1OOV Amplifier
to energize the HF step-up transformer, providing the following
AND RECTIFIER
conditions are met (Circuit Diagram Noo 430537 page 11014-1 )0
For the 1OOOV DC Range, the HF transfonner gives a step up ratio
The lkV Signal is at Logk-0:
of 1:6.17. This ratio generates secondary voltage outputs large
This is a processoir-controlled signal, set to logic-0 when
enough to provide DC outputs from the instrument of 11 OOV o

the instrument output is switched on, in the 1OOOV range.

The AC relays RL2 and RL3 in the High Voltage assembly
'flhle Watdullog Jhlas NOT 'llllarkerll'. remain un-energized for the lOOOV DC range, but the DC relay
RL4 is energized, applying the HF transformer secondary voltage
Tlhle 'JlkV ENAJBLJE' SwiJclm S1 Ollll the Power Ampimer
tn fhc rectifier bridge via RL4-5/4 and RL4-2/'.:L
is !id t({]) 'lENABLlE'o
Sl is situated below the left-hand lever (viewed The rectifier uses two series diodec. in each arm. Each
from the front of the instrument), faci·.-,i the rear, It allows dioi:k is current-rated at lA, with a of L5kV..
the voltage to be switched off for ,·r,·,·v"·mo purposes.
NJ:L The inm..sfrmner secondary and rectifier are not
refo,n:d any common. This iillow:; thr; rectifier output
A red LEID glows when all other conditions me met
to float so that it may be used for either polarity.
When RL6 is closed, the OUTPUT signal from the lOOV
Amplifier is switched through to the contacts of RL7.

Itotal
mA J175 Vp limits
6
:~ : Idealized line
_____ -[- ___ _ _ ) . - -
1
of Ji75 switch
Si="'~-~~- I •

4.
Very approximate
0 final characteristic
0 / "

3
I ~
I O ••••

2 I : ·-·-··o-·-·~··=·~~9S.iStOf Chain
~
0000000000000000000 ----------°"slope due to
: --=·-·-·-=·-·=·--~ + Darlington
••••••• .; •••••••••••• ,r,. ..... - · ... · : ·

:
--c-"~------
: __..:-------
_:.----- resistor chain
b.a~:::;..--..;---,----.---,---,.---,---.------r--,---.---vout
:
200 400
66 (min) 66 li Vp (max)

!FUG. 7.::J AJCTffON 0/F

7-18
7.9.9 CONSTANT-CURRENT 7 .9.11 OUTPUT FilTERI NG
ASSEMBLY The high voltage output is filtered in three stages:
(Circuit Diagram430563 page 11.14-2).
a. L3, Rl, Cl and C2 together form a 2-pole low-pass filter,
7.9.9.1 Ccmstam1t-Cm1reS11t which attenuates 16kHz by approximately 30dB and 32kHz
by approximately 42dR
Ql-12 form a series Darlington chain, connected across the
bridge rectifier output as a constant-current source, havLng two l:J. L4, LS and their associated capacitors form a 5-pole filter
functions: with elliptical characteristics, attenuating by at least 60dB
above 16kHz.
It maintains conduction in diode bridge D56-D63 under no-
load conditions. c. The final stage is formed by RlO, with Cl, R84 and R85 on
the Mother assembly (Circuit Diagram 430604 page
At higher voltages, D15-Dl 7 limit Qll base voltage to
11.16-1 ). This provides further attenuation of approximately
+2.4V, limiting the series current i.n Rl 1, with Ql3 pinched
30dB at 16kHz and 36dB at 32kHz.
off. Atlowervoltages Ql3 conducts, shunting Rll with l 70-
180Q (RlO plus Ql3 'On' resistance which falls to approx
l 25Q ), and increasing the discharge current. The approxi.mate
shape of the overall characteristic is shown in Fig. 7.3.
The overcurrent detector on the DC assembly operates on the
NlPl: Note that Lhe minimum voltage applied across the constant- lOOOVRangeidentically asonlhe l VRm1ge. Refer topara7.3 .7.1.
current source is 38V. Even at zero output voltage and current,
the diode bridge generates 38V to back off the or
negative 38V con.nected to RL3. 71

Bolh output line

mi.d reduced to I OV Range levels in the s.s'.l:ne

driven from the

The
m1dR101 viaRL8-9/8 contacts, the corre:spond.1
to the Guard cl:urin via RLS-4/50
described in Section 7.12.
coro..rnon to both ranges, taken at the
1=.,-w,~H of RlOl. Thus the lOCOV DC
60:1, the lOOVDC

Vi/ith
unt-e,1ergi,,ed as shown the output filter is connected to of (he anenuator has its
and the -38V Common-2 supply is connected
to rectifier negative. zero calibration, the -38V is backed
off to give a trne zero output an output from the rectifier.
is controlled by theExclusive-NORgateM4-2, under
the influence of the CPU's 'POSITTVE' and 'PA CLA1vi!P ON' The Sense attenuator sinlrn into Conunon-1, the 'reference'
signals from the serial data-link output registers. When common to which i.he !Error A.11plifier and the lOV/1 V attenuator
negative outputs are selected, providing the PA is not '"'",,"IJ'"uc, are also referred. The guard attenuator sinks into Common-2, !he
RL5 is energized, the output filter is connected to rectifier genera.I power common.
negative, and the +38V Common-2 supply is connected to
rectifier positive. the +38V is bocked off an output
from the rectifier for all negative outputs, including zero.
The requirements which decide the use of the Exclusive-NOR
function are discussed in sub-section 7.12.4.

7-19
 10
Two main aspects of analog control functions ca.,1 be considered: For some relays it is necessary to hold the full actuating voltage
across the solenoid for the whole time that it is energized. But
21, The effects of the controls on the analog circuitry, which are
where periodic updating will not cause difficulties, a relay is held
discussed elsewhere in the description;; of the relevant circuits;
on between OV and-lSV, raising l'le OV side 1:o -:-15V to actuate
b, The methods of implementing the control which have it during an Such relays have a secure hold-on voltage
been developed to use the miinimum number of control of approximately 12V, but require 20V or more to pull them in.
signals. It is also required to dissipate as little energy as
At intervals of 40ms - depending on the priorities of the
possible inside the heat-shielding chassis assembly, to avoid
CPU's n-c,w-;r,am the CPU generates a data transfe, across the
temperature effects on the accuracy of the circuits
serial interface, and fill 'Update' signal is passed into guard by the
themselves.
CPU via an opto-isolator (M4 in tl1e Reference Divider - page
11.4-5). This serves two purposes:
It is mainly provided to ensure no delay in transferring
In general, the analog control logic operates between OV and - important status data back to tl1e CPU;
15V, with Logic-1 = OV, and Logic-0 = -15V. These levels are It is available when itis required to update lhe a,-rnJog state of
set originally at the serial/parallel control data latches in the the instrument functions, as demanded by reversionary modes
Reference Divider assembly as outputs from the serial data link, or user inputs.
and are accepted by the parallel/serial status data latches as inputs
to the link back to the CPU. Some special control signals are After passh1g into guard, the update signal is na.med 'UPD(IG)'
passed into guard viaopto-isolators, also in theReferenceDivider,
operating between -lOV and -15V. These are subsequently
adjusted to the normal control logic levels.

Two methods are used to ensure that tl1e energy dissipated by the
relays is rninintized:
Use of bistable latching relays.
Use of an 'Update' signal;

For some heat-sensitive environments withm the chassis assembly,

polarized bistable latching relays are used which only require
actuation, a,,d hold on without a solenoid supply. Where relays
need hold-on energization, tl1ey m·e usually tied to OV or+ 15V on
one side, and controlled on the other by tlie uncommitted collector
of an inverting Darlington driver. Thus when tl1e to the
driver is logic-1, the relay is held energized by its -15V output;
s.nd when the driver input is logic-0, itsoutputis highi.--npedance,
releasing the relay.
7.11 DC ASSEMBLY RELAY DRIVES AND LOGIC
7, 11, 1 INTRODUCTION 7.11,2 CLAMP ASSEMBLY
(Circuit Diagrams 430536 page 11.5-3 and 430668 (Circuit Diagrams 430536 page 11.5-3 and 430668
page 7-23). page 7-23).
The a.i,alog circuitry is mainly controlled by low-thermal relays, On the DC Relay Drive Logic circuit diagram(page 11.5-3) the
many contacts bei....g fitted back-to-back to further reduce Clamp assembly is shown in block form. Also, the pcb pin
temperature effects. For die fastest response, the output relay numbers correspond to the pin numbers of the buffer chips: J7, J8
RL15 is not latched, but can trip out quickly if the power supply and J9 being the connections to M 1, M2 and M3 respectively. For
fails, removing any output voltage from the ternrinals. signals crossing the block from left to right, the output of each
non-inverting buffer is drawn opposite its input, so the function
The rest of the relays are latched, allowing hold-on without
remains unchanged as h crosses the block. As a further aid to
power, to reduce the internal temperalure at their contacts. Az
identification, the pins of any one buffer are numbered so that the
they are polarized they require a bipolar actuating drive, which is
input and output numbers add up to 20.
provided by Tristate' relay drivers and a bias amplifier.

(Circuit 430536 page 11.5-3 ). .As the UPD(IG) signal is distributed as the enable to ma.i..y
As can be seen from the circuit diagram onpage 11.5 -3, the relays buffers, it is itself buffered before fanned out. So the four
are stn.1,'lg out between the output of their bfas amplifier UPD(IG) comections al: the top of the block are inputs to four
approx. 17-19 at -15V.
17-5 andJ7-

,,,,,u,-~1- The
at J7-17 eKnerges 2t J7-3 and is :recOJiJ].ected as the
9

f2.:irJ1e,.d-out euable the otl1eJ buffers Lh.e ··-·······,

the chosen state v1hen the d:d.ve:r

are oct;,,l
t,,,o inverted enable
Lnputs - half the - per enabling
ir1put).
'1Vhenever a con1r111and has been received, the CPU
performs a control data transfer and the UPD(l[G) line from JS-
104 is pulsed to -15V for 50ms.
The switching logic places a logic-1 (OV) on the input of selected
drivers, and logic-0 (-15V) on those whose function is not
selected. Because all the buffers are non-inverting, during fu.e
update pulse a driver selects its function by setting its output
voltage to OV, or deselects by plllling its output voltage to -15V.

7-21
Some versions of lhe 40244 octal buffer are protected against
SCR avalanche if the output voltage exceeds the rail voltage, but
some are not Each l:mfferdrives solem)ld, oU1d is switched 0.7\J 1
on and off by the update enable, Because the inducumce of the
relay coil ca_n generate a back EMF in excess of the rnil voltage,
Relay
a clamp circuit guards against lhe possibilir-y of SCR breakdown, S0le11oitl

On lche =D~U,c~,y Ql-Q4 fomi two power supplies, each c.-0-~,--+--<- -7.5V

delivering a regulated voltage of a ct1,icte:-ru·op less lchan the rail

voltage ('+VE CLAMP' and '-VE A diode connected
from the buffer outputto each of the damp lines allows the output -15\J
voltage to rise to, but not exceed, the rail voltage (see Fig, 75),
Where two parallel buffers drive the clamp diodes are
FIG. 1.5 TYPICAL CLAMPED BUFFER
omitted from one buffer output (e,g, M2-9 and M2- 7 are joined
on the DC assembly between J8-9 and J8-7, so both are clamped),

+11,SV, H the UPD(IG) pulse is not present, the voltage across

RU 5 falls through zero and RL15 is de-energized- Ifit is present,
The analog-control signals are transferred into on the 4,5V is connected across RL15, which is
Reference Divider assembly, a..nd latched as 'Q' outputs in the iri_sufficienl to hold the relay on, Under these conditions the
Serial/Parallel Data Converter, Offset positive logic is employed instrurnent te:rmh-rials we disconnected from the output
(Logic-0 = -15V, Logic-1 = OV) for the signals entering the DC Relays RUO and RL18 are selected when DC voltage has been
assembly via J5 from the Mother assembly, lFor general row.log commarided, providing that the has not barked, With
control. considerations refer to Sect, 7,10, DC Fl\TCT atlogic-1, M4-ll/13 are at logic-0, If the Watchdog
has not barked then BARK DEL is logic-0 at Ml4-12- As a
10 n o3Vil IR©lrii!;lJ® Swii©i'lllriig lig!;lli~ result of both these conditions, M4-10 is at logic-1 and both
are selected_ RU Oconnects the PHI(DCV)
Range control data is input as a 3-bit code on DCR0, DCRl and
and SIU(DCV) line to the PHI(V) lines respectively,
DCR2 lines, The bit-pattern is decoded by M4 to select Lhe
RL18 connects the DC Ref output from the Reference Divider to
correctrnngerelays- As the lOOµV, lmV, lOmV and lOOn1V
the DC Error P1snplJ.Wcr input,
ranges all use the S1Lme analog circuitry, only one bit-combination
(DCR2) is required for these four nu,ges, The resulting five Relay RLl l connects !he power imd sense Lo lines back to their
combinations are listed in Table 4-1, which shows the states of respective commons, Tims when RLlO and RL18 are selected
M6 'Q' output pins and ihe energized for each range, for DC voltage outputs, so is RLl l, But in Current Function it is
also to tie the Local Guard to Common-2, This also is
Note that deselection of DC function sets each ~•A~,~-"' to
logic-L The MIS 'Q' outputs all fall ID deselecting all done by selecting RU L With C1.1ITent selected, Lhe I FNCT
range relays except RL l, RL2, RL3 imd RL 16, which are selected is at so M3-B is ai: logic-I 1md RLll is selected-
by DCR2 being at The Remote Sense Relay RL14 is also selected by the I FNCT
signal, as well as by the front panel selection of remote sense,
TI1ese are combined at OR-gate Ml0-3, before selecting RL14
OutpUi: voltages pass through ,he DC assembly on all AC a,,d DC via its buffer, RL14 removes the local sense short
ranges, RL15 connects SHi, SLo, !?Hi and PLo to the instrument's between !he power aind sense lines at both Hi and Lo signal levels,
Hi, Lo, I+ and I- terminals, lFom signals control this relay: For Current Function this has negligible effect on the DC assembly,
bmtheREM SENSJE '+' and '- signals me also passed out to RU
0

OFF at logic-0 when Output is selected ON, on t.he Mother assembly (Circuit 430604 page 11,l 6-
BARK DEL at nnless the watchdog has tripped- Althoughremote sense is not selectable for DC or AC Current
AC FNCT at logic-0 if AC Function is selected, or :ranges, it is necessary to :route the current outpm to the I+ and I-
DC FUNCT at logic-1 if DC Fnnction is selected, temiinals on the front panel, RL1 on the Mother assembly is
energized to do this, (For Local Sense on voltage ranges, RLl
Under these conditions M4 pins 1 md 2 Me set to logic-1, M4-9
routes the power Hi line to the Hi. temrinal instead of I+), REM
is at logic-0; M4 pins 3, 4 .md 5 are at logic-0, M4-6 is at logic-
GU selects the Remote Guard relay RU 7 via its buffer,
1- So M2-2 is driven positive, and as M2-3 is biassed at about -
then M2-l goes to apJJroxirnai:elv -12V, During ilie The ffiGH XLIMIT and AC lkV RANGE signals are concerned
update pulse J7-9 goes to -15V, so M2-7 goes to +15V, RL15 is with ilie AC lkV Overcurrent Detector circuit, The signals
thus actuated some 27V, but after the UPD(][G) is directly !:h:rough their buffern,
terminated, M2- 7 returns to OV 1i111d RL15 is held on, J[f AC 1i111d Section 9 discusses their effects_ The effecw of control signals
DC are both deselected, or if the ousput is set to OFF, or if the 'lkVDC', 'WOVDC', 'DC FNCT' and 'IPOSIDVE" are discussed
barks; the -12V at M2-1 reverts to "'PJIY!UAnmi,,:;,:,1 in the descriptioru: of the ana1og circuitry at their destinations-

7-22
7.12 PA ASSEMBLY LOGIC AND RELAY DRIVES
(Circuit Diagrams430618 Pages 11.94 and 11.9-5)
The CMOS logic operates between the levels OV and-15V, with AC & DC :U»V R21ID1ge Logk
logic-1 = OV, and logic-0 = -15V. Relays me tied to +15V on
On the DC 10V Range only, the input to M6-1 is logic-0; and on
one side, and controlled on the other by the uncommitted collector
the AC lOV Range only, the input to M6-2 is logic-0. Logic-1
of an inverting Darlington driver. Thus when the input to the
occurs at M6-3 to operate relay RL3 only when either the AC or
driver is at logic-I, the relay is energized by 15V; and when it is
DC lOV range is commanded.
at logic-0, its output is high impedance, releasing the relay.
AC & DC :mov Range !Logk
701 DC RANGE The input to Ql2-8 is logic-1 only when the DC lOOV range is
(Page 11.9-5) selected, and the input to Ql2-9 is logic-1 only on the AC lOOV
The three inputs DCR0, DCRl and DCR2 carry the DC range range. Either input gives logic-1 at M12-10, so relay RL2
switching information, and are decoded by M7a as follows: operates only when the AC or DC 100V range is commanded.

M7a inputs M7a outputs AC 100V Range Logic

E B A Q2 01 00
Range A 'lOOV AC' signal is also passed to activate the 100V Current
Select DCR2 DCR1 DCR0 Sense circuit (seepage 11.9-6) , only on the AC 1OOV Range.
1000V 0 0 0 0 0 1
100V
DC 100V Range Logic
0 0 1 0 1 0
10V 0 1 0 1 0 0 The decoded DC l OOV Range signal at M7 a-5 is also connected
w 0 i 1 0 0 0 to the cathode of D3 l. On otherranges the diode conducts to pull
iOOmV 1 0 0 0 0 0 the DC INPUT CLAMP signal to logic-0 (Off), but on the DC
10mV 1 0 0 0 0 0
1mV
lOOV Range D31 releases the line so that the PA CLAMP ON
1 0 0 0 0 0
100µV i 0 0 0 0 0 signal can set it to logic-1 (On).
!Dese!ec[ IDC 1 1 1 0 0 0
AC & DC 1000V Range Logk

7o12o2 AC RANGE SW~TCHING The lkV signal enters the Power AmplifierntJ9-32. It is atlogic-
(Page 11.9-5) 0 only when AC or DC 1000V Range is commanded by the CPU,
with the OUTPUT set ON. 'BARK' enters at J9-66, and i<; at
The three inputs ACR0, ACRl and ACR2 carry the AC range
logic-0 only if the watchdog has not detected a failure (see Sect.
switching information, and irre decoded by M7b as follows:
6). With both inputs to M4-8/9 atlogic-0 the output atM4-10 i<;
M7b ini:nnts M7b IOILiipLiit$ logic-1 which lights the internal warning LED D70. Relay RL6
IE 1B f4. Q2 Cll1 (101 is energized if the internal lkV ENABLE switch on the PA
Range assembly is set to its normal operating position of ENABLE.
Select ACR2 ACRI ACRfal This allows the AC drive to be passed to the step-up transformers
(16kHz signal in the case of the DC lkV Range, to the HF
1000V 0 0 0 0 0 1
HIOV transformer).
0 0 1 0 1 0
rnv 0 1 0 1 0 0 For olher ranges, or if the watchdog barks, RL6 is de-energized,
1V fJ i 1 0 0 0 removing the AC drive to the step-up transformers. LED D70 is
100mV 1 0 0 0 0 0 also de-energized.
Him'\! 1 0 1 0 0 0
1mV 1 1 0 0 0 0
AC IOOOV Rimge Logic
The input to MB-3 is logic-I to energize relay RU only when
7"12.3 FUNCTION AND RANGE LOGIC the AC 1000Vrangeiscommanded. A 'AC lkV RANGE'signal
is also passed to the DC assembly to select !:he overload sense
DCV Logk
resistor.
When un-energized, relay RU selects the DC ERROR signal in
preference to the AC 1V signal, as input to the Power Amplifier DC :I.OOOV Range Logk
when DC Voltage function is selected. When un-energized,
Relay RL8 reduces the permissible overload on the output of the Although the combination of the universal lkV Range signal and
lOV Amplifier, also when DC Voltage is selected. the AC lkV signal is used to define the DC lkV circuitry, two
extra facilities are required for the DC lkV Range. The 16kHz
When 'DC' is selected on the front panel, both DC FNCT (J9-70) REF FREQ signal has to be switched to the DC modulator. For
and! FNCT (J9-72) signals are atlogic-1. Under these conditions negative outputs on the 100V Range the lOOV Amplifier positive
both inputs to NAND MIS-12/13 are at logic-1, so M6-ll is at rail is reduced to +38V instead of the +400V supply, so this has
logic-0 and both relays RL4 and RL8 are un-energized. For all i:O be restored to +400V for the AC signals on the lkV Range. For
other function selections DC FNCT is at logic-0, so MIS-11 is at these applications the decoded DC lk V signal at M7 a-4 is used
logic-1 to energize both relays. as input to M4-6 md M6-6.
(Ccm.tinued overleaf)
7-23
The REF FREQ signal enters at J9-61 and is enabled at M6-5
the lkV Ra.nge decode on M6-6. Provided that the PA CLltMP :!'l@i@©~@©l 'i"l(Q):!'li1lliJ'E 0
l"'&. u\it,1:,lil ~Llli u~@mnl1ai
ON signalisOff(ie. atlogic-0), the 16kHz'M0D DRIVE'signal C@murrn@uu@i1l C~fu'lil" :!a,rut@ ~,a~@
is passed to the lkV DC 1\/fodulator (seepage \QliN
The POSIDVE signal enteri_ng at J9-41 is input to M4-5 ~nd the o'\f(Eol/J/~ (l)ii\j 0 0 Energized -Ve
lkV Range decode is to M4-6. ff output on the .,VE 0/~ Off
0 0 1 0 Un-energized +ve
1OOV Range is cornma.,ded, are The ,,V ~ «'.ll/fl «:li~
0 0 0 +ve
out-put at M4-4 is and Ml5 causes i:he LED in Ml6 ID ,,VE ©/l" OIFF
0 1 -ve
conduct by pulling M16-3 to logic-0. The pnotcHl!·ansIBtor of The PA CLAlviP ON at also disables the 161',Hz
Ml 6 conducts a short circuit between MOD DRIVE signal to the DC Modulator.
the source and gate which turns off the +400V supply to
the 100V Amplifier driver stage. conduction causes D56 to
conduct, so for negative outputs on the l OOV Range !he
rail for the driver is sourced from the +38V supply. The '400V(2) OFF from U1.e CPU is uu'"""'-'Y at
On the DC lkV Ra.nge the +400V supply is required to dec>l with for voltage ra.'1ges; but after a 'Fp\JL 7' message indicates a 400V
the AC signal being amplified, so M4-6 at inhibits the supply failure, it is !hree times, au,em.pi.l11g to restore the
disabling Dl1ic1to,-nmri1er Ml3-15 01Y<::n-·1.:u.uo1:wn The
same inhibition results for outputs on the DC 100V 2llld the PSI OFF
Range (when the +400V is needed to power the driver 11.9-
M4-5 at logic-1.
collector output
B.llowsMl-2 to he
Ml-14. fa the lower chain. with four inversions, Ml-14- is also
PA CLAMP ON is before the lk.V DC control u1c"',-"cmc,,,vc11 if a400V or 15V fa.ilwe has
broken the lkV line, and released when the is restored. 1:he monitors.
It is also required on entry into B.nd exidm:m the 100V DC
Thus for normal onP.n,,,11111
Other w.nges s.re 'don't care' states.
'EN.ABLE400V-' li:ne from Ml-15 is held at
With the 'ENABLE 400V-:-' line it -u·,,,-~,-,,u
LEDs in the 400V power
,ii/hen the DC 1OOOV Range is selected~ set Off, the A failure of either t.1.e 400V or 15V
drive is removed from the input to i:he step-up transformer. The 1, ,ll,,uu=,6 the 400V
to
connects -38V to the base of the Consumt Current chain at Pin 2, current is cut off in any case, due to zene:r D24,
The other end of die chain is connected,
lines, to the head of the lkV seru;e attern.mtornn i:he DC ;;;;z;;:;~,~).:;J,v
The attenuator output is fd to the of d1.e Error
Amplifier.
On the lOOV or 1000V ranges, after xu,l:',.'vm.,, a 400V FAIL
Under these conditions, the Error """If''"""~' 'sees' a negative from the monitor, the CPU attempts three times to restore
voltage at the terminals, and would drive into fortl1e (h"'l
san1ration on ii:s positive side to correct the olllpuL This vvou1d i:he PS/][ heatsink) prevents reinstate'ment if an overload
occur regardless of !he size DC Thus it is necessary to remove i:he overload. if i:he
applied on its non-inverting restored. This is done by setting I.he EnAS OFF line to
reset to On, !he power circuitry could generate a massive off and vP.,nnm,w itk'ie output
which would result in catastrophic failure. A similar (but drive.
polarity-reversed) effect could be presentfomegative DC Output
The !hree attempts 11re made by toggling the 400V(2) OFF line
selections.
(described in sub-section 7.12.5). Each time the supply is
This excess loop gain is removed by reversing the position of the enabled, R6 and Cl hold the BIAS OFF signlil at logic-0 for
polarity switch during the time that the output is turned off, so !hat about lms to al.low i:he supply to build up before the load is
the Error Amplifier sees a positive voltage imd backs off toward reapplied.
zero. The logic to reverse the polarity is driven by i:he PA
After three unsuccessful attempts, the CPU assumes a permanent
CLAMP ON md POSITNJE signals, employing an eJtclusive-
hwrdwlllll"e fault and holds the 400V(2) OFF at logic-!.
NOR gate.
Jin !he Voltage assembly, M2-4 feeds the driver for lhe
polaritychangeove:rrelay RL5. atM4-51;J..ndM4-6 are
POSITIVE and PA CLAMP ON
7.12.7 'UM ST' LOGIC
This status signal is passed back to the CPU via the SSDA serial 1.12.1.2 'UM sr G~nemtioll1l
link to indicate that certain lfrnits have been exceeded. The
The latch MS a is set by logic-1 on pin 6, for as long as LIM DET
LLM ST signal entering the Reference DivideratJ4-76 (page 11 .4-
remains at logic-1. Its 'Q' output activates LIM ST via M4-3 to
4) can be activated to logic-0 by any one of nine detectors, as
informtheCPU. Italsoreinforcesandlatchesl[ L™ lOOV AMP.
illustrated in the simplified diagram of Fig. 7.6.
LIM ST is also activated if !he overload signal 1OV FLAG from
the lOV Amplifier is at logic-0 when in AC lOV Range.
7.12.7.1 'UM DIET'
Other detectors which can provide the LIM ST signal are:
The LIN! DET signal output from the Power Amplifier at I9-67
(page 11.9-5) can result from the LIM DET signal setting the Jl})C A§§emlMy (page 11.5-112)
latch M5a. LThi DET is associated with the high voltage ranges, DC Overcurrent Detector (1 V & 10V DC ranges)
and can be activated by:
Sine-Source Assembly (Constant Current Source)
DC Assembly (page 11.5-112) AC 1V Buffer Overcurrent Detector
AC lkV Overcurrent Detector
DC Overcurrent Detector (100V & 1000V DC ranges)
Current/Ohms Assembly
DC and AC Current ranges Overvoltage Detector
High Voltage Assembly (Constant Current Source)
DC lkV Overvoltage Detector 7.12.7.3 CPU Respons~
Power Amplifier Assembly
On receipt of the UM ST signal, the CPU initiates a series of
AC lOOV Overcurrent Detector
dock pulses on the 'I LThi RST' line via the SSDA and Reference
AC l OOOV Overvoltage Detector
Divider, so that M5a can be reset as soon as the LIM DET signal
(These two combine to generate the 100V FLAG, which is clears to logic-0, M5a 'D' input being strapped to logic-0 (-15V).
NORed with 'DC FNCT' before becoming LIM DET.) The CPU also di.splays the 'Error OL' message.
NOTJWOV FLAG is initiated by the AC lOOV Overload Detector ff the UM: DET line has cleared to logic-0, the HIDY Amplifier
or AC 1000V Overvoltage Detector (page 11.9-6), whenever the input is reinstated by M5a being reset Furthermore, if the
400V supply current peaks are excessive, or the AC lkV Range overload was temporary, the L™ DET line remains at logic-0,
drive voltage to the primary of the step-up transformer is excessive.
and normal operation resumes. The CPU is informed by UM: ST
The LIM DET logic-1 is immediately transferred via Ml2-3 as at logic- I, so the I JLil\1[ RST pulses are discontinued, and the
the signal 'I LIN! lOOV AMP' to the gate of Q14 (page 11.9-3 ). Error message is removed.
Ql4 conduction reduces the lOOV amplifier input to zero, so if
For a persistent overload, the detectors operate again-the cycle
the overload is external the LIM DET signal should revert to
repeating until user action fa taken to remove the overload.. The
logic-0.
Error message continues to be displayed. If the overload is an
internal fault, it is likely that another protection circuit will have
detected it Md taken its own action°

00 Si AC Curroll! l'i&r,g""
c,.,,,.11..llfll!!• h:l©teol"'

UM ST SIGNAL ORIGINS

7-25
 "1
These are signals used to control the gain and compensation of T,vo NTC thermistors situated in different positions on each PA
the AC lkV amplifiers, to section heatsink are pa_n of a bridge network which detects excessive
temperatures on the heatsinks.
The 'LF' signal is set to logic-I by the CPU via 1:he SSDA serial
link and Reference Divider latches, when the AC 1000V range The reference arm of the bridge is formed by R165 and Al"\J9-7 /
and 1:he 10GHz or lklI-J:z frequency nmges are selected. Xt is 10 in bol:h in series with AN9-6/l L
i...nverted as 'JLF' advBl-12, and I.hen inverted as buffered 'JLF' at The sense arm has four parallel sections, each consisting of one
Mll--10. section of A_N9 in series with one of the NTC thermistors. Four
'FREQ R0' is also CPU-controlled. It is set to logic--1 when null detectors are used (M22 and M23), each comparing the
eiLh.er 1:he lkI--llz or lOOld!z frequency range is selected. voltage at Lhe reference arm junction with that at the junction of
one of the sections (TEMP +R/-R/+F/-F).
'LF' a_nd 'FREQ R0' are combined at M6-10 to give the At 25°C each thermistor resistance is lOW. The bridge is
'lkV GAIN' signal, which is at logic-0 only when the lOOkHz unbalmced in favour of open-collector outputs from the four
range is selected. (The software prevents the 1MHz range being comparators, pulled up to Common-2 by AN2-3/4 and AN2-5/6.
selected on the 1000V nmge). Q36 is therefore cut off, and the 'OVERTEMP' signal atJ9-31 is
at
J[f one of the temperatures exceeds 100°C, its thermistor
resisumce falls to the extent that the bias on its null detector is
reversed. The null detector output is taken low to -15V,
conducts and Urie OVERTEMP signal goes to logic-1.
TI1e OVERTEMP status signal is passed to one of the Reference
Divider status 1P<""""~ where for safety reasons
it is pulled-up a lMQ section of AN2. 'fhe CPU reacts to the
signal by displaying the 'FAflL m,ossag,~, and forcing a
recovery sequence:
i(l)1U1flr11J1f i(l) lFlF
Reference Divider ramp to zero
Remote Sense OFF
Control 'OFF' bit set
Control 'lkV' line disabled
Display and Keybo211"d locked
After approximately 1 minute, the CPU defaults the instrument
1:0the normal 'OUTPUT OFF state in the selected ranges with
ouiput set to zem, The FAIL l message is removed, and the user
is at to try another ati:empt.
Under norm~J power-up conditions, with the Power Amplifier
assembly in and Q36 cut off, AN2-7/8 holds the line
more negative than -14V (logic-0). H the Power Amplifier is
removed, no over-temperature information is available from the
heatsinks. In this event, the OVER'flEMP signal rises to logic-1,
indicating failure.

7-26
SECT!

FREQUENCY sv1,rn~ESIZER
I in-Guard
~eforenc0 Frequ~ncy I =fa>
R~mot0 IEEE 488 worn Analog lnt~r'. ====="· VCO Fre,guency SYNlH
Frequency Digitol VCQ 1--~~>l R,inge ~~--0
0/P Dividers O/P
Selection lnterla~ 16kHz I

Frequency
Display
Selection vco
FRE03-0 Co-ntrol
Paral\01
CPU
'::· SSDA Data-Control Frequency
System
Regieters Range
FREOR2-0 Control
Frequency
Range
Se!ection
SINE-SOURCE ASSEMBLY

1
(Fig. 8.1)

Use:rs normally set !.he operating frequency a combination of After entering the Sine-Source assembly, FRE~_0 effectively
'FREQUENCY RANGE' and 'FREQUENCY' display selections. multiplies the 8kHz reference by a factor 'n' to determine the
These are memorized by fue CPU and translated into two binary frequency of a Voltage Controlled Oscillator (VCO). The VCO
control words: frequency (signal 'VCO 0/P') is input into a series of frequency
dividers, whose ratios are set by FREQ R2_0 • The division ratios
'JFREQRH).
are chosen so as to make the dividers generate the Frequency
A iliree-bit word, five of whose codes represent the five
Synthesizer output signal ('SYNTH 0/P') at the user-selected
frequency ranges.
frequency.
'FJREQ3_0/
The purpose of the synthesizer is to provide an accurate frequency
A nine-bit word whose value 'n' defines the chosen frequency
reference for the quadrature sinewave oscillator. The oscillator
with respect to the selected frequency range.
is approximately tuned by selection of circuit constants using the
Users can select a frequency by means other than pressing a combination of 'FREQ R:i.fll' md 'FRE~-11l·.
FREQUENCY RANGE key and setting a frequency on the
'SYNTH 0/P' sets as the reference in the phase comparator of a
display; for example by using 'Store' or the IBEE 488 digital
Phase-Locked Loop, controlling the frequency of the main
interface. But regardless of the selection method, the CPU will
Quadrature Sinewave Oscillator to an accuracy determined by
always compute the two binary words, which then synthesize the
!he crys ta! oscillator.
selected frequency in the Sine-Source Assembly.
Both words are passed into gum-d vi.a the SSDA, and latched&Uhe
outputs of I.he Reference Divider Pmallel Conttol registers. A
l 6k.Hz reference frequency is also taken into gururd, to be divided
by two to 8kHz in the Sine-Source assembly.

8-1
 VOlTAGE CONTROLLED OSCILLATOR

REFF REO
0
- 3kHz
Phase Low Pass Frequoncy-band
,-- ~
+2 ~
~ vco
16kHz ~
Comparator Filter

ill Iv
Capacitors 0/P

J..
I I
Currnnt-Mirror
B1Ji'i0r v .:::3kHz
J
v V

Bl<Hz 9-btt Fr€:quency Divider

(Divioo by 'n')
I
I
-,._ 'n' x 81<Hz

FREOe-e,
REFERENCE DIVIDER ('n')

Binary- oodod

.
Parallel
Frequ0n cy Data
0 -fa Analog
•"
Frnquency-band
Control •::.';•" o"

l
('n ') Control
Latches FRE0 8_0 FRE0 8_5

113-2,
430652 page 11.4-5 and 430446 page
The 16kHz (INT) signal originates at Ml6-14 in the Analog Consider C2 dischm:ged. is off; so all the 4.7mA from
Interface (page 11.3-2) ai,d is buffered as '16klHz(OG)' Q6 passes tluough QS. The collector voltage ofQ4 is close to the
11.3-1). On the Reference Divider atJ4-104, it passes into guard positive rail, buffered 1:md R9 to hold Q5 on. Also, as
via opto-isolator M3 (page 11.4-5 ), gating with is turned off Q4 collector is turned on by its
'DISABLE REF FREQUENCY' and 'BARK' inM24, filtered by emitter, passing 4.7mA into C2 and the current mirror M50.
R86/C38 to reduce harmonics from the transmission path, mi.dis
Ca:pacitor C2 charges until Q4 turns on. Cumulative Schmitt
sent via the Mother Assembly to J6-53 on the Sine-Source
action passes tl1e fall at Q4 collector to tl1e base of ensuring
Assembly (page 11.6-4 ).
a:rnpid transition between states; so the4.7mA is lnmsferredfrom
Schrnitt-trigger Ml4inverts tl1e 16kHz into a symmetrical Q5 to turns on, its emitter io cut off,
squarewave, which is then applied as clock to Ml3a, a bistable so the charging path to C2 etc. is interrupted.
cormected to two. The resulting 8klh squarewave is
M50 continues to discharge C2, whose falls until
taken as the reference frequency for comparator M12.
Q4 struts to cut off again. The cumulative action is :repeated to
Note that in this configuration the SIG input of Ml2 is med for
turn on, recharging C2. The cycle of charge ai,d discharge
the reference, and the divided VCO output §ignal is applied to the
continues, generating 'VCO 0/P' squarewaves at buffer Q12
REF input This is necessary to provide the correct sense in the
emitter.
phase conlTol elementM50, because of the inversion of integrator
Mll.

(Circuit Diagram430446Page 11.6-4, 8.2)

time, only one of the capacitors C3, C4, CS and C6 can be
The VCO is a discrete-component ECJL relrurn1tion osciHmor
connected in parallel with C2, by conduction of its associated
generating an output of frequency 'n' x §kHz. 11:S natural frequency
transistor. This splits the frequency range of the VCO into five
is dependent on:
bands, governed by the fou:rmost-significant bits of the frequency
the value of capadt01 C2 (or C2 plus one of C3 - C6), control word FREQ,,_lll acting on M8. The association is shown
in foble 8.1; note !:hat the VCO frequency bands quoted in the
1:he value of its continuous discharge cUITent fue
table are correct because the VCO is under ilie fme control
phase control element (current mirror M50), md
of comparator M12, within !:he phase-locked
the value of its charging current through Q2 on ahemare half
cycles (4.7mA).

8-2
 flU:Q"" M/8 OIL"'@ '\!'CO
b!ili,1 ll!il C2°C6 To prevent VCO oscillations appearing on the 15V power rails,
8 7 6 l'i l@!;]Ji© i 0
Seiial©ikwu which also supply the integrator Ml 1 and current mirror M50, the
rail is heavily decoupled, regulated by Q8, and all
0 0 0 0 10 to 3·1 C2& C6 80 to 248 devices whose currents are lL"icely to disturb the rails are supplied
V
0 0 0 0 32 lo 63 A1 C2& C5 256 to 504 through constarit current somces and Ql3).
0 0 0 0 64 to 127 C2 11 C4 512 io 1016
0 0 0 0 128 to 255 C2&C3 1024 to 2040
0 0 0 0 256 to 500 NONE C2 only 2048 to 4000 The VCO, Mll md M50 operate from the 15V supplies. Ml2,
M9 and the frequency dividers which follow the VCO, all operate
from the in-guard logic supplies of +OV and -15V. The VCO
output from Q12 emitter is therefore limited by DI to logic
supply levels. Are-conversion back to 15V levels is accomplished
at the input to the integrator Ml 1, as 'f P31 pulses are negative at
(Circuit Diagram4304-46Page 11.64, and Fig. 8.2) Mll input.
fu the following description, capacitors C3, C4-, C5 and C6 are Dl is a Schottky hot carrier diode of reverse capacitance approx.
ignored, but references to C2 should be read as including the 2pF. This avoids distorting the high frequency outputsquarewaves
appropriate additional capacitor. (for 1MHz output, the VCO oscillates at 4MHz).
The VCO output is fed back toM12 phasecomp~.ratorviaM9 and The output is fed through Rl2 to avoid loading the VCO, and as
Ml3b, which are connected to act as a 9-bit frequency divider. 'VCO 0/P' to the frequency dividers at M5-9 (page 11.6-5 ).
Because the divider is controlled by FRE~-0' the VCO output
frequency is always divided by 'n' before being applied l:O the
REF input of the comparator. The output from ,he comparator
will only be zero if the frequency fed back to Ml2-6 is 8ld-Kz (Fig 83)
the VCO frequency is n x 8kHz), md in phase with ilie 8kHz As mentioned ell.r lier in para 8 .1.1, ilie purpose of the synthesizer
REF FREQ at M12-3 (TP14). is i:O provide m accurate frequency reference for the quadrature
sinewave oscillator. The VCO frequency (signal 'VCO 0/P') is
The output from Ml2 is integrated by Ml l to drive a DC current
input to a series of frequmcy dividers, whose ratios are set by
into the current mirror M50, which has a of two, its output
current being drawn from the charge on C2. During the half- 'FREQ Rui"• so as to make the dividers generate the selected
frequency as 'SYNTH 0/P'. FREQ R 2_0 is a three-bit word, five
cycles of the VCO oscillation when C2 is being charged, the
of whose codes represent the five frequency ranges.
mirror obtains its current from Q2 conduction.
The phase control loop seeks to phase-lock the two inputs to the
A second purpose is to clock the Quasi-Sinewave Generator in
synchronism with the synthesizer oUiput (and hence with the
comparator. U they are in phase, the comparator output is at high
main quadrature sinewave oscillator output). The synthesizer
impedance ('TRISTATE'). In this condition the integrator
frequency is a multiple of the Quasi-Sine frequency, except on
capacitors Cl6 and C18 have no charge or discharge path, so
the lOOHz frequency range, where they are both at the same
Ml 1's extremely high gain maintains their charge, md thus the
frequency. Thus thedividerratios are also chosen to generate the
voltage at 'fP6. Mll supplies the input current for M50, the
correct frequencies for the quasi-sinewave clock, for each
mirror continues to draw the same discharge current from C2, so
the frequency of VCO oscillation remains constant. Thus the frequency rmge selected.
loop stabilizes only when the frequency divided by 'n' from tlle
VCO output is in phase with (and therefore at the same frequency e.1.3" 1 lO!'lflci®ll' Ratlc~
as) the reference 8kHz. (Circuit Diagram 4304-46 Page 11.6-5)
In stable operation, ilierefore, the loop maintains V CO oscillations Binary/l3CD Divider M5 is set for binary division by fixing M5-
at n x 8kHz, and the feedback dividers reduce this frequency by 2 and M5-10 at Logic-0. Conversely, Ml is set for decimal
a factor of 'n' to 8kHz. division by fixing M 1-2 and M 1-10 at Lo gic-1.

Any disturbance in the loop will generate corrections to restore BCD counter M2 is set to count up, by fixing M2-10 at Logic-L
zero phase difference at the inputs ofM12. Frequency deviations Its CARRY OUT signal at M2- 7 is at 1/10 ofits clock frequency,
are therefore detected at an early stage as phase changes, giving anditsQl outputonM2-6 is at half its dock frequency. Flip-flop
a measure of 'phase advance' correction. M4a is connected to divide its clocks by two.
Multiplexer M6 selects the appropriate source frequency to clock
lhe Quasi-Sinewave generator. Jrn particular, on the lOOHz
The VCO can be switched off by a logic-1 of OV at the base of Range it selects the CARRY OUT fromM2, which is subsequently
Ql 1 (INHIBIT signal). This originates in the CPU system, divided by 10 in the quasi-sinewave cm.mter, and returned via
setting FREQ R 2_0 oode to 111 (anon-existent 'R 7' range) when J6-'.H to be used as SYNTIHI 0/P.
AC functions are deselected. It also· resets the +2 flip-flop Ml3a,
so that no reference frequency is passed into the phase comparal:Or.
8-3
a, 1,3,2 Ratio Sele©\tion
(Fig. 8.3 and Table 8.2)
The frequency range selection word FREQ R 2 _ia, is decoded by Table 8.2 shows how frequency range switching derives the
M29 into five range lines R 4_0 • These lines perform the following synthesizernutput frequencies by selecting !the appropriate outputs
functioru;: from the dividers. Note that except for the 1MHz Range R 4 , the
ratios of individual dividers are not altered.
ru, Switch ranges in the quadrature sinew ave oscillator by relays
RL1-RL8 selection of integrator capacitors (page On the lOOHz RffiTige R 0 !:he overall division ratio of 8000 is
achieved as for the lk__lf:l[z Range, but with a further division by 10
b, Switch ranges in the Cosine Sqmrreroutput filter (page 11.6-
in the quasi-sinewave counter M11 on the AC Assembly.
2 );
On the 1MHz Range, R 4, the division ratio of MS is changed from
re, Adjust the division ratios of Frequency Range Dividers M5
8 to 4. 'fheDPA inputsM5-5 andMS-6 irreprimed to Logic-1 and
and Ml (page 11.6-5) for range R4 Range),
Logic-0 respeclively, whereas on all other ranges the priming is
!ll, Select appropriate outputs from the Frequency Range Dividers reversed. Range R~ also alters the division ratio of Ml from 10
and to 25, changing its priming bit-pattern, to couect the quru;i-
e. The INHIBIT line turns off ilie VCO for non-AC functions. sinewave frequency; but as the synthesizer output is taken
tlrroughMl0-4/3 from MS output, the adjusltment to Ml does not
Functions (a) and (b) are described later in Section 8.2. fu this affect the SYNTH 0/P frequencyo
description we are concerned with functions (c) and

(f1) (12) (13) (i5) (16)

c,B +10 <2 / ->4 / +10 _,_ 'IO Quasi-Sil'!Gweve

VCO OIP
(n x Sl1Ha) Oi------- (s-4 on (-:-25cn -n (Solecied i---- (Quasi-Sin2 --o-----.- ------0
1MHz Range) 1MHz Range) by "n') Ccunier) Frequsney

(M)

R0 100H?

FREOR2 PJ 1 ·Jt·\HZ

Froq1.,'0ncy R 210:tH~
FREOR1 Rim~
D0ooclcr
Rs 100kHz

FREOR 0 c_.,_,,,..,,./1
R 4 1MHz

SVNTI-IO/P
---~-~ ---0
INHIBIT 0-------~
 FREQ. FAEQUIENCY VCO OUTPUT OVEAAll RIELIEVANT DMDEl'l QUASI-SINE SYNTHESIZER
RANGE DISPLAY In~ BkHzl DIVISION RATIOS CLOCK OUTPUT
RATIO FREQUENCIES

1\/16 i\/11 M2 M11°

Hz kHz !AC PCB) !J6-15CW 1.115-52)

Hz Hz
100Hz 10-63 80-504 !l 10 10 10 100-630 10-153
IROI 64-127 512-1018 6000 B 10 10 10 640-1270 64-127
120-330 1024·2640 B 10 10 10 1280-3300 128-330

kHz Hz
lkHz 0.30k-0.63k 240-504 B 10 10 1.5-3.15 300-630
(RH 0.64k-1.27k 512-1016 BOO B 10 10 1.6-3175 640-1270
1.2Bk·3.30k 1024·2640 8 10 10 1.28-3.3 1280-3300

kHz kHz
lOkHz 3.0k-6.Jk 240-504 8 10 1.5-3.15 3.0-6.3
IR21 6.4k-12. 7k 512·1016 B 10 1.6-3.175 6.4-12.7
80 12.8-33.0
12.Bk-33.0k 1024-2640 B 10 128-3.3

kH, kH, '

l
100i<.Hz 30k-63k 240-504 8 15·3.15 30-63
IR31 64k-127k 512-1016 tl 1.6-3.175 64-127
12Bk-330k 1024-2640 8 El 1.28·3.J 12€1-330
I

1MHz kHz kHz

!R4l 0.301\11·101)1\11 1200-4000 4 4 1.2-4.0 300-1000

• Quasi-sine counter M11 on the AC Assembly divides VCO

output at all frequencies, but contributes to SYNTH 0/P only
on the 100Hz Frequency Range.

8-5
 8.1.3.3 Frequency Synthesis for the Quaslra
Sinewave Generator
(Fig. 8.3 and Table 8.3)
The l OOHz frequency range uses the quasi-sinew ave counter as To ensure that the Divide-by-2 outputs ofM2 andM4a are locked
a divider in deriving its SYNTH 0/P frequency. Although not a into the correct phase for quasi-sinewave generation, a
direct component of the frequency of the SYNTH 0/P signal on synchronizing signal 'CHOP LOCK' is derived from the quasi-
otherranges, the quasi-sinew ave frequency is deliberately derived sinewave counter·~· output, entering at J6-75. Following DC-
in the synthesizer, so that the zero-crossings of its waveform can restoration from 8V supplies to the normal OV/- l 5V logic supplies
be synchronized at a time when the main sinewave is also by C20/D3/Rl5/M7, the signal is applied to M4a SET input, and
crossing zero. (The main sinewave, of course, can be at a high M2 RESET input.
multiple of the quasi-sinewave frequency.)
For all frequency ranges, the '100-5kHz' quasi-sinew ave generator
The quasi-sinewave frequency is held to a maximum of 330Hz clock is passed to the AC Assembly via J6-50 and the Mother
(400Hz on the lMHzrange ), to limit errors due to high harmonics. Assembly. This output is level-shifted by Q42, to the 8V supplies
The 1MHz frequency range contains only one frequency band, which are used in the quasi-sinew ave generator circuitry.
but the other four ranges are each divided into three bands,
The quasi-sinewave generator reset signal 'SYNC0 (IG)' (which
corresponding to the three most significant bits of the frequency
was transferred into Guard by M2 on the Reference Divider), is
word FREQ80 •
input to the Sine-Source AssemblyonJ6-48 to be similarly level-
Table 8.3 illustrates the way that the three bands affect thequasi- shifted by M43, before being passed to the AC Assembly via J6-
sine frequencies. Note that division ratios of 2, 4or 10, by M2 and 49. This signal, however, is not used on this instrument.
M4a, are selected by FREQ6 , FREQ7 and FREQ8 at M6 pins 11,
For other details of the quasi-sinew ave generator refer to Section
10 and 9 respectively. Frequency range R0 atM7-2 ensures that
6.6.
on the lOOHz range, the divide-by-10 output of M2 is always
selected, regardless of the state of these three bits.
-~--,.--

FREQUIENCIES SYNTHESIZED IN SINE-SOURCE ASS1EMl3LY

' FREQ. HlEOUHl!CY DIVIDER RATIOS lo, OVIERAll OUASI-SINIE QUASI-SINE

RANGE DUSPU:W VCO OUTPUT OUASI-SINIE\1\/AVE DIVISION ClOC:( l"AIEQUENCV OUTPUT
In x B~H,l M5 Ml M2 l\/l4a RATIO FRIEClUENCY I& J7-51l HlEOUENCV
H, l<H, (J7-501 H, Hz

H,
100H, 10-63 B0-504 !) 10 10 - l'lOO 100-630 10-63 10-63
IAWI 64-127 512-1016 0 10 10 - BOO 540-1270 64-127 64-127
126-330 1024-2640 l'l 10 10 - SOO 1260-3300 120-330 120-330

kH,
l~H, 0.30!<-0.63k 240-504 0 10 2 - 160 1.5-3.15 150-315 0.30l<-0.1'33k
IA1l 0.64k-1.27k 512-10115 0 10 2 2 320 1.6-3.17!5 160-317.5 0.641<-1.27~
1.2B~-3.30l< 1024-2640 l!l 10 10 - BOO 1.20-3.3 129-330 1.Wk-3.30!<

kHz
101<H, 3.0l<-6.3k 240-504 B 10 2 - 160 1.5-3.15 150-315 3.0!t-6.3~
(R2l 6.41<-12. 7k 512-1016 B 10 2 2 320 1.6-3.175 160-317.5 6.41<-12.7~
12.8~-33.0k 1024-2640 8 10 10 - BOO UB-3.3 128-330 12.Bk-33.0I<

~H,
100kH, 30k-63k 240-504 B 10 2 - 160 1.5-3.15 150-315 30k-63k
(R3) 64k-127k 512-1016 B 10 2 2 320 1.6-3.175 160-317.!5 64k-127k
12Sk-330i< 1024-2640 8 10 10 - 800 1.28-3.3 128-330 128k-330I<

1MHz kHz
!R41 0.30M-1.00M 1200-4000 4 25 10 - 1000 1.2-4.0 120-400 0.30M-1.00M

TABLE 803 QUASl~SINEWAVE !FREQUENCY DERIVATION IN FREQUENCY SYNTHESIZER

8-6
 8.1.3.4 Synthesizer Frequency Analysis
Table 8.4 is provided to allow a complete analysis of fue
frequencies to be found in the divider circuitry. In part, it
duplicates figures from tables 8 .2 and 8 3.

FREQ. FREQUENCY VCO f1 f2 f3 f4 f5" f6

RANGE
(NOMI
DISPLAY

Hz
DIVISOR

'n'
VCO OUTPUT
{n x
kHz
Bk Hz)
M5 OUTPUT
lf1-81
kHz
I M1 OUTPUT
{f2-10)
kHz
M2 OUTPUT
{f3-10)
Hz
I M6 OUTPUT IM6-3i
Hz
J6-51 INPUT
{f5-10)
Hz
M6 Input Channels and Division Ratios

Xi 113-21 x, {f3-41 X 2 _7 (f3-101

100Hz 10-63 10-63 80-504 10-63 1.0-6.3 100-630 100-630 C 10-63 ::J
IRlill 64-127 64-127 512-1016 64-127 6.4-12. 7 640-1270 640-1270 C 64-127 ::J
128-330 128-330 1024-2640 128-330 12.8-33:o 1280-3300 1280-3300 Li28-330:J I
lkHz 0.30k-0,63k 30-63 240-504 30-63 3.0-63 [ 100-630 ] 1500-3150 150-315
IR11 0,64k-1.27k 64-127 512-1016 64-127 6.4-12. 7 [ 640-1270] 1600-3175 160-317.5
1.28k-3.30k 128-330 1024-2640 128-330 12.8-33.0 [1280-3300] 1280-3300 128-330

I 10kHz
(R21 I 3.0k-6.3k
6.4k-12. 7k
30-63
64-127
240-504
512-1016
30-63
64-127 I [ 3.06.3 ]
[ 6412 7]
100-630
640·1270
1500-3150
1600·3175
150-315
160-317.5
12.Bk-33.0k 128-330 1024-2640 128-330 [12.8-33 O] 1280-3300 1280-3300 128-330

I I
100kHz
IR31
30k-63k
64k-127k
128k-330k
30-63
64-127
128-330
240-504
512-1016
1024-2640
[ 30-63 ]
[ 64-127]
[128-330]
i
I
3,0-6.3
6.4-12.7
12,8-33.0
100-630
640-1270
1280-3300
1500-3150
1600 3175
1280-3300
150-315
160-317.5
128-330

L
I
II 'n'
111-41 112-251 I 113-10)
Hz kHz kHz kH1 I
Hz Hz

L
11MHz
(R4) 0.30M-1.00M 150-500 1200-4000 [ 300-1000] 12-40
I
1200-4000 1200-4000 120400

ANALYSIS

8-7
 Page 8-8 is deliberately left blank

8-8
8.2 QUADRATURE SINEWAVE OSCILLATOR

FREQUENCY CONTROL LOOP OUTPUT AMPUTUDE CONTROL LOOP

Sv nth@sized Ouadrnn.m1 Outi:,ui

H
Frequency Phase Sinewave
Comp, Osci!lawr Conditioning

01.itpllt Voilue
local or
Mean-Squa,rn
Remote
Error
Sensing

Hi
§9Y%)8
C(QH'1<efri10onOr;ig

The purpose of the oscillator is t0 define the am1pli1ru1fo-ststbilliiy, As the pu,_'ity and a.mplitude-stability of fue output sinewave
purity and frequency of Lh.e sinusoidal output of the i.'i'J.Strument on depend substantially upon its source, a hlgh quality oscillator iB
all ranges. Its output is of sufficient constant -··r··--·- to drive necessary. A 'quadrature' (dual-integrator) circuit iB chosen for
fue subsequent signal-conditioning two main reasons:
After originating in fue oscillator, fue sinewave 1i111r11plltuQle is 'This arnmgement allows extensive phase 001d amplitude
accurately defined in two oul-put- sense loops, using a low- controls to be applied, to establish the required high
distortion VCA as control element The sinewave is se! close to specification.
its demanded value by analog conditioning in the output circuits.
Its natural frequency can be easily programmed by electrical
'fheoutputvoltage is sensed, attenuated to its l V Ra.ngeequivalent, selection of its component values.
then its mean-square value is compared against fuat of the quasi-
The oscillator fa: approximately runed selection of circuit
sinewave reference. The difference is convened into a DC error
coostants using the two CPU-derived binary words 'FREQ R2_11/
voltage which corrects the output adjusting the VCA gain.
and 'FREOii_12/. These also accurately define the crystal-sourced
frequency of the Digitru Frequency Synthesizer output, to which
ilieoscillatoris phase-locked. Thus iheoutputsinewave frequency
accuracy is held to l OOppm.

8-9
8.2.2 SIMPLE QUADRATURE OSCILLATOR

8.2.2.1 Basic Clrrcuit 8.2.2.2 Inadequacies of the Basic Circuit

(Fig. 8.5) (Figs. 8.5 and 8.6)
The circuit consists of two RC integrators and an inverter, For an unrefmed practical implementation of the basic circuit, the
connected in a positive feedback loop. The nominal phase-shift loop gain and phase response would be as shown in Fig. 8.6.
around the loop is 360° (acrually 720°: 270° in each integrator,
The two main conditions for stable oscillation at constant
180° in i:he inverter).
amplitude are: exactly unity loop gain, and exactly 360° (or
Assuming perfect integrators, matched components and an inverter multiple of 360°) of loop phase-shift; so the circuit of Fig. 85
gain of exactly -1, this circuit will undergo stable oscillation at a clearly does not satisfy these conditions. Without some attempt
frequency given by: to control gain and phase, the loop would be either over- orunder-
damped, so oscillations would either die away or increase in
w = 1/R.C
amplitude until limited by i:he supply rails.

R C C

GAH\l(dB)
Inverter Integrator lniogrator
0 1-------~------
-Acoswi

FffG. 8.5 BASIC QUAJ!JRA Tl!JRE OSCfflfLA TOR

I.
I
PHASE 360 0

FffG. l:Ui GAIN AND PHASE RESPONSE

OF PRACTICAL CIRCUIT

PRACTICAL QUADRATURE OSCILLATOR

(Fig. 8.7)
The method chosen to refine lhe simple circuit corrects the loop amplitude, so i:he mnplitude of stable oscillation is defined.
phase-shift to exactly 360° using a feedback signal. Furthermore, lfn Fig. 8.7 the correction circuit is added.
it is arranged that tthis signal i£ correct only at a given ou!:put

8.2.3.1 Phase Correction

The loop phase is corrected by introducing a small cosine term
(B.cosrot) to be summed with the sine feedback (A.sinrot) at the
input to the inverter. The resultant output of the inverter is thus
given by: Hence $ ... tan· 1 (BIA).
and for B«A: $ = BIA ------ 2
V(t) ... -(A.sinrot + B.cosw!)
.. M.sin(rot + $) •••••• 1 The $ ter:m represents an additional phase shift in the inverter,
where M • '4(A2 + which by suitable scaling cm be made equal to the phase error in
and sinqi .. B/M; the basic oscillator loop. Scaling is achieved by multiplying
COS$ "' AIM. A.oosrot by the DC amplitude error (A2-1m,), asdescribedopposite.
8.2.3.2 Constant Ampllti.JJde Contml
The above method of phase correction plays its paxt in controlling The difference current 'A2- ~ ' is taken as the amplitude error,
the output amplitude. With both sine and cosine terms available, which defines the fraction 'B' of the cosine term to be fed back to
a DC analog of the sinusoidal output amplitude can be obtained the inverter as 'B .coswt'.
utilizing the identity:
Jin a perfect oscillator, this 'cos' feedback would be driven to zero.
sin 2rot + cos2rot "" 1. But in any practical crrcuit, some small remnant of B.coswt
Equal-amplitude sine and cosine outputs are squared in 4-quad- persists at the correct loop phase-shift, correcting !the loop gain to
rant multipliers. Their squares aire summed w generate ampli- within the stability specification.
tude feedback in the form: Acting thus together, the combined feedbacks correct both loop
A2.sin 2 rot + A2 .cos2 rot gain and phase simultaneously. The method of amplitude
correction prevents the appearance of AC components in the
A2(sin 2 rot + cos2 rot) amplitude error signal, thus avoiding unacceptable levels of
= A2. harmonic distortion due to !:he cosine multiplier.
This method therefore expresses the square of the output amplitude
as a DC current analog, from which is subtracted a constant DC
reference current 'IRE!;.

A.cosw!

[l)iH!m;m,iai
4-0l!.l~drnnt M!.ll,ipliers

A.sinwt

-A.sinwt

Amplitude
Detect«:J1

8-11
8.2.4 FREQUENCY CONTROL
Section 8.1 describes frequency generation in the Frequency a phase-locked loop, and division ratios in subsequent frequency
Synthesizer. Binary control words computed by the CPU represent dividers, to set the Synthesizer output signal 'SYNTH 0/P' to the
user-selections of FREQUENCY RANGE and FREQUENCY. selected frequency. Stability and accuracy are assured by a
These adjust frequency division ratios in the feedback circuit of crystal-sourced reference of 16kHz.

The Sinewave Oscillator is already approximately tuned to the lit can be shown !hat the actual operating frequency is a function
selected frequency by the two binary control words, which select of the inverter gain. In the frequency domain, the oscillator loop
from weighted values of integration capacitance and resistance: transfer function is given by:
Frequency ranges are selected by control word FREQ R 2 _0 , G x (ro/s) x (ro/s)
which controls relays to change the values of integrator
where G is the inverter gain,
capacitance.
ro, is the unity-gain frequency
Frequencies within a range are selected by the control word s == j.ro, where ro is the actual frequency of operation.
FREQ 8_0 , which controls FETs to change the values of
For stable oscillation, the loop transfer function must equal 119.
integrator resistance.
Hence G.ro//s 2 1 L9
8.2.4.2: Fine Adjustment Therefore G.ro,/
(Fig. 8.8)
and ro -ro$.G 112
The oscillator's output is converted into a squarewave and applied
as 'signal' to the phase comparator of a second phase-locked loop. Thus by adjusting the gain of the inverter, the phase error signal
The Synthesizer output signal 'SYNTH 0/P' is input as reference from ihe comparator exerts fine control of the oscillator frequency.
frequency to the same comparator. The difference is integrated 'This phase-locks the oscillator to the Frequency Synthesizer.
to produce a DC phase error signal, which is applied to control the
gain of the inverter stage of the oscillator.

Sine to
Square

Coarse
A.sinw!
Control

Fine Frequency
Control Voltage Integrators
SYNTH 0/P "------'

B_coswt
-A.coswt A.sinwt

Amplitude and Phase

Control Circuitry

FIG. 8.8 FINE FREQUENCY CONTROL

8.2.5 OSCILLATOR OUTPUT

The A.sinrot signal is inverted and b1!.lffered out to provide the
drive to theoutputloop VCA. The bufferfeedbackmsistors are
positive TC thermistors which compensate for the TC of the
VCA input FlETs (refer to section 9).

8-12
 The inverter ""''"tJ"""""" the feedback of Lhe basic
The cascaded L,tegratorn consist of M 19 and M30 ·m,~p,·nrc,.,. with oscillator. The very high bandwidth device used for Ml5 is
their input resistors and feedback ca1c:ia(;mxs Both circuits are C27, ru,d its T08 case is ,,,,n,cu,u,,u.
identical i.i."1. difference§ ]n
A.s n1entioned eBxlier, its DC offset is by R49 to
null the sine DC:'. offs'3L
th11e coI1stomts.

The inverter has t.hree inputs:

m. A.,,mmt from the second integrator, the basic oscillator
a frequency ra.nge. feedb9.ck
are fixed, one other set being added in parallel when its range is
h. TI:llorn§mtt from the Amplitude correction
selected. RU to RL8 perform the
JEJRROll'?.', a DC current which ahe:;:s the inverter's
hence its gain) FET

are surmned as cuITents

word ~OOO!JOH~.~~ of ti"'le B.cosrot signal is
loop, described
i,, sections 8.2.8 cmd 8.2.9.
control
fue highest-value resistors at the base of the ladder. ,..,fhe rnost-
a,,;rn,m,o""" bits? v,1hich represent control
the lowest-value 1esistorn at the top. Yvhose the source-drain.resistance is altered
ERl~Oll' curre:nt via current-rnhTors NI16 ind
Mm.
Two FE'fs in series the amplitude levels reached
of both integrators. R41 is selected to account for differing 'on' resistances
of different batches of FETs. This a scaled-down
version of that Rn1n1101,,p.r; for the VCA in the main output
details of which appear in Section 9. A de.sci:iptio,n of the action
of the tre:qu1en.cv follows at para 8.2.7.2.

82.4.2, !he oscillator's output is to i.he

The Syntihesizer ouiput is
The phase-

The amplitude detector circuit squares the outputs from both which is applied i:O control
integrators. bis ?h'''""'°'"" u:np1ortaI1lt inverter stage of i.he oscillator. This exerts fine control of the
are not included in the squaring crnm11=.ut1J.tum. oscillator frequency, i.he yrn,.uoe;M,.'-! frequency.
The 'Cosine' offset is removed by adjustment of R50 at the l!lon-
inverting input of M30, and the 'Sine' offset by R49 at the input
of inverter Ml5. This latter adjustment removes the combined
offsets of M15 md M19. (At manufacture, md after imy
replacement of major board componeni:s, the controls are
iteratively adjusted for minimum AC fondamental component in
the DC amplirude control signal 'V 0 ' at link 'lPl'.)
 The overall action is for a lagging oscillator (frequency lower
(Circuit Diagram 430844 Page 11.7-6) than the synthesizer) to increase the DC current flowing into the
two c111,ent mirrors, md vice-versa if t_he oscillator leads. 'fhe
After buffering 1J11dinvertion by M47 on the Sine-source Assembly
two inputs to lie comparator are in phase when the sinewave
(page 1106-1 ), the oscillator Asinwt output is passed to the AC
output from the oscillator is at the synthesizer frequency.
Assembly via J6-45 and 17-450
Any disturbance in the loop will generate correctioru to :restore
On the AC Assembly, thesinewaveisconvertedinto asquarewave
zero phase difference at the inputs of M30o Frequency deviatio11_s
by Schmitt bistable Q32/Q33, a.nd level-shifted to logic supply
are therefore detected at an early stage as phase changes, giving
levels of OV and -15V by D25/Q2!t Q28 provides a current-
a measure of 'phase advance' correctiono
limited load for maximum gain, while D24 and D25 prevent
voltage saluration of Q32o Q23 buffers the resulting square wave
into the phase comparator input at M30-60 SINEWAVE AMPUTUDE
The slower zero-crossings at the lowest frequencies could be DETECTOR
susceptible to HF noise, so this is filtered, on the 1OOHz frequency
The method of amplitude measurement relies on the identity
range only, by Q27 aDod C48.
'sin2wt+cos2 wt = l' to convert AC output signals from the
The 'SYNTH 0/P' squarewave, at the demanded frequency, is oscillator into a representative DC signal.
transmitted from the Sine-source Assembly at low (1 V Full
Squaring Asinwt and Acoswt:
Range) leveL This holds the maximum slew rate to a value which
A2 sin 2 wt
avoids inducing interference in other internal circuits. Q20 and
A2 cos2 wt "' +
Q21 amplify the signal to the CMOS logic levels ofOV and-15V
required by the comparator input at M30-30 The AC waveforms of A 2cos2wt and A2 sin2wt are inverted
versions of each other, at twice the original frequency, and both
Note that current steering is used between Q32 and and
a:re syminetrical about the DC mem1 value of A2/20
between Q20 and Also, a com:tlmt current source Q22
provides emitter currenL These measures prevent the fast By summing the two, the AC waveforms are eliminated, leaving
switching edges in the sclnnitt and runplifier circuits from injecting DC A2, representing the squa:(e of the amplitudeo
spikes into tl1e supply rails. fu the An1plitm:ie
Phase-comparator outputM30-5 consists (OV) electronicru.ly and summed 21s a differential
when the oscillator lags the synthesizer, or negative when a const:a.nt DC reference cmTent
the oscillator leadso When both are in phase, M30-5 is at 1i,= to generai:e the error current (I2-
irnpedance. m1 amplitude 'o 'fhis

At integrator M3 l input, zener diode D30 holds the non-iI1verting

input at -604V; so for in-phase sigmils into 1:I1e compm:ator, the VG is driven to zero the action of the amplitude control
inverting input seeks the same level. The integrator tends to hold sothatP-~ = 0, andthusP= ~o

its voltage level (with very drift due to capacitor when the two Bxe and at a consta.11.t
but limited to -9JJV by D32/D33). V\Then fue oscillator output
lags the synthesizer ou1put,
are integrated to drive M31-6 slowly more
phase of the oscillator leads, the integrator output becomes more
positive.
The phase control seeks to phase-lock the two
comparatOL ff they are in phase, the r-n= ,~v·~frw
7

impedance (TIR1STA1'lE'). lin this condition lhe u"'"""'"u'

capacitors C53 and C56 have no or rn,,rn~v,,,. so
M31 's extremely high gain maintains a consumt charge on the
capacitorso The constmt voltage on base maintains a
constant 'FREQ JERROR' currenL
Q37 appears to be an open-collector runplifier. However, its
collector current passes via J7 -44 and J6-44, into the two current-
mirrors at the input to the oscillator inverter on the Sine-source
Assembly (page and thence to the -15V rail.
With constant input current, fue mirrors continue i:o draw lie
same output current from fue Al'\J4 bias network for Q29, so the
frequency of lie dual-integrator oscillator remains constant.
Thus the loop stabilizes OJnJy when the oscillator frequency is in
phase with (and therefore at the smne frequency as) the Frequency
Synthesizer output
FBG. 8.9
1UJff,~11Moffwlfs A•sln,wt with A•co~wl
8-14
 (Circuit 430446 currents from bnth Sine and Cosine
V cos and V sin are squared independently ii, of differential The voltages developed
four-Quadrant multipliers, each with two identical differential across the loads will theireforealsodiffer by &"l amountp:mportional
inputs.
receives Vsh,tvi from ihe §second m,·.~CTMi·,vc
IVI30 ___ ,_____ ,, a:{ld -Vshilvvt frorD. the n11.ain in_verte:r
1).
A:,, +V cos wt is the cosine output from the oscillator,
= K\12
the-V coswtsignal is derived byinversioninM31. These aYe both where 'K' is a constant at constant temperature, dependent upon
fed as inputs to the Cosi.v1e identical ci.vcuit values h1 boi:h squarnrs, a."!.d 'V' is the amplitude
of both sine ID<l cosine outpui:S from the oscillaror.
However, a reference currecnt Il§ superimposed. The DC current
11.6-2) is drawn the lkohrn load p\I\flS by M40 (pin 2),
Isolating the Cosine circuit alone as a.n example, there are two to with
differential inputs. One is 13 amd 16, md respect to TlP'lO. (111e reference current is established at a value
Lhe oLher across pins 6 and 10. which includes a'1d R91. The value
of R9 l for correct oscillator is determined at
M34 i::; OOTI!"lected as a diode ID compensate for
temperature drift.
and its erniner-collector current:
ofM35a, the
][~ is nn~n,w,11cm
";]
SO \ uc IB conrmon irnode present at its
difference between lhe CUffeni:s in M3~.- )_ aJ\d M34- l t, refol'.l'ed ID common 2A. At this

the oscillator outpul:S to drive the error

action t.he also drives '\l1 to 'VFIBF"

increase current.
Therefore the differential bases due to
Because components cannot be matched some small
Q55 emitter cu:rrents is I,:;;::::;:::l:1:::.1:;:
differences can exist between 1.he sL,.2 a,nd cos 2 terms. Such

The difference bei:ween the currents h, M34-9 ai,d M34-7 of the oscillator tre,au.encv filtering in the
collectors is also ,.v,uM~rl'mvrn to Vcoswt to other filter formed by M35b and its associated crrcuit
M34 emitter resistors But each collector current !LS It would be w set 21. single '"'"'-'""'"" bandwidth for all
divided between the two halves of the duS>J [cl':msistor in its ranges, but as this would need to filter down to 20Hz for the
lOOHz rnnge, it would S!lso im;rn1v,oru1eri1tlv settling
times for the tirf,q11e111cvrn.nges. 'Hie'"''"'-'""''~ bandwidth
The combined effect of tl'fiese two facwrs is similar to l:he of the filter is tl'lerefore swhched behveen ffe:qu:encv ramges
mathematical operation rm,n,~,,,,m~ by logarithms: a the R4.0 signals decoded from FREQ R2 _0 in the synthesizer(page
term is pn,011cect in each Q56 ;md collector current, 11.6-5).
proportional to the linear of the two input voltages. The uco4w,,"'Y :range signals select the apprnpriate feedback
By cross coup!m.gthe collectors iJTidQ57 as showT!, other components, conduction one FlET from Q47-Q52 per
constant terms are suppressed, 1111d the difference between the range. (Q48 is not used).
currents drawn from AN15-7/8 and ANl 6-9/10 is proportional The filter output is the oscillator amplitude DC error signal 'V0 ',
to: limited to amaximum of approximately 6V by the action ofback-
Vcoswt x Vcoswt to-back clamp diodes D24 and D25. VO passes via link :B to the
'Amplirude Control' circuitry (seepage 11.6-1 ). The value ofV 0
The inputs are equal, so the differential output current is determines the fraction, and its polarity ilie ph11Se, of the V.ooswt
proportional to V2cos 2wt signal which is to be added ro V.sinwt at M15 input.

SqtUJall'®lf'
The Si.ne Squllll'er behaves in the :sm:ne way, producing a differential
current in its collector foadls proporti\onru ro Vlsi.n2wt.

8-15
 (Circuit Diagram 430446 Page 11.6-1)
Before describing the control circuitry, it is useful to review the
various controls imposed on the oscillator (see Figs. 8 .4 and 8 .7):
M23 is connected as a summing VCA, with a fixed feedback
21, Frequency control by phase-locked loop to the frequency of resistor R53. Vcosrot and-Vcosrot are applied to opposite ends
the synthesizer output (albeit with a constant phase lag). This of its balanced inputresistorchainR71, R65, R64 andR70. 'fhe
is effected by controlling the gain of the inverter stage of the center of the chain is the virtual ground of M23, so if the 'on'
oscillator. (Input resistance ofM15 is changed by adjusting resistances of Q4l and Q41, are equal, the balance is not
0

the conduction of FE'fs Q29.) disturbed and M23 output voltage is zero.
b, Phase control to establish exactly 360° loop phase-shift by When the Loop-gain Error is zero (V O =OV), the static conditions
injecting a small amountofV cosrotinto the oscillator inverter set approx. -3V bias on both FETs (depletion mode) to reduce
input (via R29). crossover distortion. The PET gates are also bootstrapped by
c, Amplitude control by adjusting ihe sense and amplitude of M24 and M25 to half the AC voltage between source and drain.
V.cosrot added to V.sinrot, so that the loop gain is exactly The DC conditions are:
unity at 360° loop phase-shift, at a constant output amplitude,
Q41. Q46 emitter - -0.75V
and at the synthesizer frequency. (M23 gain is adjusted by
M261lll - 150µA
varying the attenuation of its input signal, using FETs Q41a
M26I out - 300µA
and Q4lb.)
Q41 vg£ 0
- -l.5V
l\mplitude error is corrected a controlled fraction of
either V cosrot or - Vcosmt to the V sinrot feedback applied Q4lb M32-6 - ov
emitter -0.75V
to the main inverter M 15. A push-pull conttol circuit is employed
in order to adjust both amplitude and sense. V cosrot is input from M27][m
M27I out - 300µA
Q31 emitter to R71, and its inverse is input to R70 from the our_put
of M31, (which also provides the -Vcosrot input for the cosine Q4lb vgs - -1.SV
squarer). Amplitude Error:
M23-6 - zero

The .Amplirude Error the 'on' ""''"'''''rn-"

u111t:1tuui:iuv, due to the il,verter M32 in the side
In the case of a about 0.5V:
-0.25V
- SOµA

M32-6 - -0.SV
emitter -1.25V

The outpui at M23-6 is in the smne as Vcosrot,

m~.n,c0u.," with larger amplitude enor.

For a negative V0 , M23-6 output voltage assumes

as tl1e -Vcosrot signal, increasing wiu'l larger amplitude error.
Transistors Q45 and act as 011.ai,;e-ro-,;urren converters to
drive the 'x2' current mirrors M27 and M26. Voltage reference
diodes D20 a,,d D22 provide the crossover bias. D21 imd D23
provide damping when Q45 and bases are driven positive,
preventing V00 breakdown.
M23 output (now recognized as 'B.cosrot') is summed with the
basic oscillator feedback (Vsinrot) at the main inverter input
(Ml5-5). When the amplitude is correct, and the loop phase is
exactly 360°, M23 output is zero and does not inject any 'cos'
component into the loop.
li 1:he loop gain or phase is in error, then the squarers' output
current is not equal to the reference current, VG is not zero, :md
a small anJ.ountofcos component is fed into the loop. This adjusts
the phase and to correct the oscillator amplitude.

8-16
The External Frequency Lock allows m,:tn,rri,=t be The main use envisaged for this facility is for a user to improve
synchronized with a,, external reference frequency of either on 1:he±l OOppm frequency accuracy of the instrument, by locking
1MHz or 10MHz (a tolerance of ±1 % on these treqw!ncws rn 1:he h,,,nrn,ITTr"' synithesizer to a customer's own frequency
specified). standard.

M34

D0tsci:
1MHz/10MHz
Input 'EXT FREQ SEL
DC lsolalion

Rear Panel Js~, / " '16hHz(INT)'

lnpul - Fe 04 ~ ,-c)-jjf!-..
(1 MHz/ o---o3 SELECT ' '16kHz(OG)'
INT/ ----0
11-·

1OMhz) J53·2 Pulse EXT

Transfomier

~Fe,~2.5/
Fe+625
'161\Hz(EXT)'

(Circuit nm,u,i,n.,·.· 430830 Page 11.17-2;

The output sinew ave frequency is synthesized in the Sine-Source
assembly, normally synchronized to an 430604 Page 11.16-4; 430648 Page
reference frequency of 16kHz. T'o lock the output tom external The !External Reference of 1MHz or 10MHz enters the
reference, it is necessary only to divide 1:he frequency of the l (Hi) 1:md2 (Lo)ofRear-Paneloonnector J53
reference do'Jlm to 16ld1z and use this instead of ihe internal on the Interconnection assembly (page 11.17-2 ). It is transferred
reference. The circuitry described in ihis sub-section is shown in via Jl8 and J3 on the Mother assembly 11.16-4) to the
block form in 8.10 md carries out the functions: buffer input circuit on the Analog Interface assembly (page 113-
4 ).
Isolates, limits and buffers the input reference signal to TIL
levels. C59 and Rl remove any DC components of the signal; and Rl5,
Dl and D2 limit its excursions to approximately ±0.7V before it
Divides ihe input 'Fe' by 5 and then by 10
is applied to ihe pulse trnnsfonner T'l.
The output from T'l drives line receiver M9, C62 setting the DC
Detects whether the Fe is 1MHz or 10MHz; from this it sets
offset to zero, and Rl6 providing some noise-immunity.
the selector to choose either its +5 or +50 input, to give an
output of 200kHz. The detector sets the status 'EXT'
REF ST to Logic-1 whenever either of the two signals is
present.
Divides the selector output by HI, then multiplies by 8 in a
phase-lockedl loop, finally dividing by 10 again ro 16kHz to
give the signal '16kHz(EXT)'.
Selects either '16kHz([NT)' or '16kHz(EXT)' in response to
the position of the Rem: Panel switch S53, and to the presence
of a 1MHz or 10MHz External Reference signal. The
selected signal '16kHz(OG)' is trransferred into guard by
opto-isolator M3 on the Reference Divi.dler assembly, and
thence as 'RElF FREQ' to the digitru frequency synthesizer on
the Sine Source assembly.

8-17
The line receiver output at TP24 clocks the +5 section of Ml 1 The state of iheother to Ml8 atM18-14 'A' depends on the
counter. Its frequency is reduced to either 200kHz (for 1MHz frequency of the external reference signal at TP24, which is used
input) or 2MHz (10MHz input), and this signal is used to clock to clock Ml0-2 'B'. Each positive-going edge triggers the first
the second (+ 10) section ofM 11. This section (and the other two monostable, initially setting Ml0-13 to Logic-1 (Fig.
+ 10 counters M28) is connected as a divider to 8.11).
establish a symmetrical mark/space ratio. The frequency at Ml 1-
ff the frequency is lMHz,Ml0-13 times out and returns to Logic-
13 is either 20kHz (for 1MHz input) or 200kHz (10MHz
0 before the next 1MHz trigger arrives, thus providing a train of
The outputs from both counters are fed to the dual 4 iu.to 1 line
negative-going triggers for the second (5.7µs) monostable at
selector M18, which :always chooses the 200:kHz signal.
Ml0-9. The first negative-going edge sets Ml0-12 to Logic-0,
but in this case each succeeding retrigger arrives before ihe
8.3.3.2 'EXT FREQ SEl' monostable has timed out, and so Ml0-12 remains at Logic-0.
When S53 on the rear panel is closed to select External Reference, The output from Ml0-12 drives Ml8 control inputM18-14 (A).
+5V from S53 enters the Digital assembly at J2-25 (page 11.2-2 ), If lne frequency is 10MHz, Ml0-13 (330ns) cannot time out
setting line D2 on the Data bus to Logic-I each time that M36 is before the next reLrigger a_rrives at M 10-2, so it remains at Logic-
enabled by my IRQ every 8ms in response to the Lntemal 1. No negative edges appear at Ml0-9 to trigger Ml0-12 to
signal RTC The CPU passes the information Logic-0, so Lh_e oontml input to M18-14 remains at Logic-1 as
to the External Reference Buffer on the Analog Interface assembly shown in 8.11.
via the Precision Divider Input Data Latches. The state of S53 is
repeated at M34-4 (page and to l.VJ:18-2 (B) to set
M18 outputs.

e> <>-101J;rn

M10-13: Q
Mi0-9 !\ input

111110-4: 0
M46-8

Mi0-12 0
M46-9 / Mrn-·14

M46-10 Mi/6-10
'EXT REF ST' 'EXT REF ST'
............ ··········
The input sources to M18-10/ll/12/13 are sv,itched to M18-9

u~}tf L:~!EQ S~l~ ·J /"J QILlc,~[-J;,;; [}®i:Gt'.:t

ITtrJ"U®a.2 DJ~"~ g~ LI t1,

M18-13

0 ov ov

0 0 MHl-i i ov ov

B,33,:3L5 f!Ul~nu®rr [J)hfi~n@rri @rr llitus Oa,JJi[Ql!JJI

The 200kHz output from M18-9 is divided a further + 12.5
before it becomes the signal '16kHz JEX"T'. This is achieved in
If no external reference sig,w.l is present, both M 10 monos tables
three stages:
remain ,.,,,.,..m~n,Pcn in their refaxed tmlled--out) state. Thus
+].l[D Ml0-4 andM10-12are atLogic-1, botl1inputs toNAl'-IDM46 are
so its output REF is at Logic-0. For signal
'HiexlOdividers
,,~;,~u.,vH.,.,, of H/i!Hz or 10MHz one of the to M46 is at
the orn=-,n•--·- squarewave.
so EXT REF ST goes to Logic- I.
M46 returned to the CPU, being sensed on the data bus
line D4 at each RTC IRQ (M37-13 page 11.2-2), so the CPU
The Phase-Locked knows whe1J1er an external reference signal is present or not. It
oscillates at a frequency which when divided 8 also lmows ·when S53 is selected, and issues the 'Error EF
phase-locks to the 20kHz present at TP25. At this 'i-rP.<m,eo.m"' rnessage on the MODE if S53 is selected but no external
the error voltage across C30 is a very low ampliiude reference is present. 'Ibis warns the user that with the
ripple balanced about OV DC.
exterrrnJ reference selected, the VCO in the Reference
Buffer is free-running in the absence of a signal, and is
VCO, described in para 8.1.2.4. The VCO output is low-pass still the reference for synthesis of the instrument output frequency.
filtered, then buffered and which drives the final tl'lus unlocked boili from the useI's sync source and
+ 10 counter. from the internal oscillator. This is normally because no
external. reference has been coimected to J53 on l!:he rear panel!

The l 6kHz (E:iIT) sig,wJ output from M28-13 is a syrmnettical

squarewave phase-locked w the External Reference frequency at
'flP'27. Itis passed into the sm1e selector (M18) which carries out
the lMHz/10MHz and ]NT/EJIT selection of the divided signal
input The 16kHz (fl\IT) signal is also applied to M 18. ][n this case
the other half of the dluru selector is employed.
The 16kHz(EJIT)RlEF signal. from TJF27 is input viaMHl-3 md
Ml8-4, while the 16kHz(Il\IT) signal.goes ro M18-5 imdM18-6.
Switching between 1MHzmd 10MHz(Ml8-14)hrurnoeffect, as
the output atMHl-7 selects shorted input lines. The l!Nf/lEXT
switching by EXT FRlEQ SIEL (M18-2) selects between the two
ofshorted inputs to give i:he 16kHz (OG) output from MUl-
7. This is buffered viaMS-6, .if3-104 (page 11 3-1) md the Moi:heir
assembly to the Sine Source ruisembly at 16-53 (page 11.6-4 ).
--~
This complex system generates the whole range of AC Thus 1:he
of that
reference.

Cons\i:Ein'R:-Amp!i'itucie Conditioned
Sineweiva Output to Load

I
I
I
Gailln Ermr R@n9e
S1PJi~chin9
I
!via SSDl\i
I
I
I
lieClm
Fi@forentG
i
Di,u~der)
Comparnioir
i
Uuosi-Sirna
Fl1es12 Svnc.
Seviusnc:0 Sync
I
S1ne/l!J.!J<El£fi-Si~s
11
Oua@i-sinG'if\1@11'0
Mealfi<'SQU8N
SoQ,,m::~

i
Comparn'i!'Crr

i
111'1''"'"· 11>~m FS
Flesoh.n:iori

Aeie:[email protected] Qq,1151~i-Sinew~ Sffl$00 Sin®lMiW® Seli"issd Sinewwe

1111-l'lmQ:® RMS l°"""•I !1V-l'l•"!J"' 1'11\/lS lwslsl IOu1,:,u1 1.,,,.,101

FIG. 9, 11 OUTPUT AMPLITUDE CONTROL SYSTEM

Feature of Output Controlling Element Controlling Input to Loop

lFreqil.llelDltey: Frequency Synthesizer (Crystal-Sourced) Const!IIJlt-11mpHtude sinewave from Quadrature Oscillator
Siimewave lP'ruur[ty:
Quadrature Oscillator Constmt-lll.mpHrude sinewave
Voltage lR.2imge: Processor, via SSDA l!lld Control Latches Ranging
Coarse Amplim«lle: Reference Divider Accurate DC Reference Voltage
(Resolution redm;:ed to approx. l OOOppm JFS by 10-bit DAC)
Reference Divider mdl Quasi-sinewave Generator Quasi-sine RMS: value at resolution of approx. lppm FS

9-1
The system elements are described individually in the five sub- Because the coarse =,,p,nu= Lne error loop gain,
sections from 93 to 9.7. The system block diagrrun at 9.1 fu,d the error itself results from comparison with an a:mplil.,wle
throws clea:r of the handbook, so 1J1at it can be used for reference the
when readLng these descriptions.

The
:result is that the
linem·.)
Sinew ave sourcing is tl1e subject of sub-sections 8 .1 (Frequency
Synthesizer) and 8.2 (Quadrature Oscillator). The result is a Details of VCA """"'''"'inn and en-or compensation are described
high-purity sinewave of constant 1.9V amplitude, input to the Ln suh-sectior:. 9 3.
VCA.

ii1to guard via the serial dat2J.1in}.:: as described in sv.,b-·section 6.4.

The output mnplitude is controlled within the coarne inc;ements

by an 'error' loop. The output is seru;ed at the load for 4-wire
connections, or at an internal point in the forwmd path when 2-
.wire connection is selected (or imposed).
The sensed output is !'.educed to 1V Range RMS levels by the
Sense Conditioning circuitry ( as described in sub-sections 9 .4
and9.6), md ii:s mean-squm-e vitlue ill comp11red witll that of the
Reference Quasi-sinewave. The difference between ilie two
values is expiri~ssed as a DC eriror, !l.11ld fed to oontrol the of
the VCA,

9-2
 430446, page 11.6-3)

The circuits described in this section perform the

fonctions:

TI1e n1ain "VCJii,. rec,eives z"' cu11Stfu"1t air,plitude

fron1. O)scillato:r controlled
crnmp1a:r1:ng 1:he sensed
range. sinewave ou1:put of the ii"IBtrument with the reference quasi-
Provide smooth of within the coa:rse steps, sinewave.
in resporu;e to error signals from the The 1 Volt Buffer is included in the output signal path on all
Comp::rrator. voltage and current ra.'lges. It also acts as a VCA, since its input
Impose the settling rate of the true DC reference resistance is controlled by its 10-bitDigital-to-Analog Converter.
voltage on both the cmrrse gain adjustment and the mean- The DAC receives its binmy input from an imalog-to-Digital
square error (AC AlvI!PL '-"''''"'-.,''" scaling. Converter, whose numerical output tr;.i.cks the user's output
demand, in increments of size approximately n,vu,,J,_,u, of full
Seru;e excess currents in the output buffer, ,.,.,.,m,u11,n a
scale,
LltvI ST signal to i:he CPU via i:he control interface.
All the circuits described i..11 this section are located on the Sine

amplifiers are shown: Reference voltage. The filtered reference's time is thus
The 1 Volt Buffer (M45, ML:.6 and the discrete output m,.pu,~eu on the ADC digital outpul:, an.d hence on Lhe 1V Buffer
at'11plifier). fo; resistance is controlled 111.:: DAC
M43. For reasons in sub-section 9.1, it is also necessary to
The main whose input resistance 1s compensate the output error h,-,,,.,,~n,,h, with the
detemuned and coarse gain steps. The 1v,,~1·-i"IT .ADC therefore drives a second
DAC, which selects values of feedback resistor in the Error
For a general de,;cri1pti.on of the Control Amplifier. Tllli3 increments
refer to sub-sections 9.l and 9.2. modifying the AC AIV!PL !C,.,,,..,,..,n
mean-square comparator.
The AOC m1d its DACs ensure that i:he has the
time for any selected J:re,gu.encv

1V <aflge
Olp
~-NlAP-s0-h- - - -0

9-3
 coru;tant-current source Q94 and coru;rant-current sink
Q86 (140mA). to 93.
The VCA and 1V Buffer combine in cascade to modify the
amplitude of the sinewave output from the si.'le oscillator, With zero L'lput co:m:litioru: Q94 is saturated, limiting the quiescent
accurately covering Lli.e instrument's dyna_rriic range (see Section cur,ent at 70mA. the small bias current for Q92 flows in
9.1 and The eventual output from the 1V Buffer 1V Rl44, so the output volw.ge is just +Vb.
FR) forms the instrument's basic 1V AC rnnge.
xs the AC L6JYIPL ERROR'
1

scaled andM42. The coarse gain scaling of the 1Vbuffer

derives from the DC Reference 'Ref+'. conduction falls during positive half-
reducing conduction. The quiescent current
but pa.n is now diverted through the output
circuit via Rl44, Rl12 icmd L7.
The Sine Oscillator output from +2 buffer l\147 11.6-1) is
emitter-followed by Q75 to the VCA FET irrput chain
These dual FETs are enclosed ·with IV147 PTC
feedback resistms Rl36 &'ld R137, in a metal heatsink The
rnatched FETs fofi11 the vaxiabl0

foHovver 1Jvith
&td Ivl46 btllfer the Cl~_ss A power:
stage fi.'or:a t'he of the DP1.C. The first buffer
It'l45 h~ extremely high DC gain~ Jtollix1g off i.l BfF due to tl1e
feedback of C 108, It removes the input DC offsets of M46,
M46 controls the buffer's AC performmce; Cl 12 ensures that the
non-inverting input appears as a virtual AC groW1d at HF, 140mA
allowing source-follower Q74 to develop the AC across
R159.
class A current amplification,
inny cmss-over distortion at HF. Power
~u.1~,,~au~~"'-~"~,from

9-4
 'REF+' originater, in the Reference o;vidcer and is used to set the
peak valne of the quasi-si_newave in the AC ;;,ssernbly. lts value
Except for a small bias current, all output current from the ranges from +0.126V at 9% of Full Range, through +l.397V at
discrete buffer stage flows in Rl44, so the current level can be Full Range, to +2.794V at Full Scali:..
detecl.ed by ~ensing the differenti:d voltage across it. This sem;e
REF+ is input to Lhe Sine-Source assembly at J6-57 and 16-56,
voltage rides on the output voltage; thus to capture it, the current
then appJ.i.cd lo am.pl.tller MLi.lb, whkh is connected to r,~move
detector is bootstrapped to the AC 1V output.
any conunon mode presfont ~tit~ in;:mt. Thus at TP47, M41b
High-speed dual comparator M49 fonns the basis of the Cuuent output is referred to Common-2A. ,' '.
Detector circuiL Its supplies are bootstrapped via TP29 to the
juncl.ionofR144andRl J.2inthe 1 VHuffcrnutpm:.. andQ84
Capacitors C99, Cl30 md C131 filter any HF pick.up from the . II!I !i iIII
provide constant current drive to 6.2V Zeners D40 and D41, with
Q83 and Q85 providing the regulation for the bootstrapped rails
reference voltage, and M41 b scales up the DC voltage levels by
a factor of 2.43, to:
Fi~ed + 7V
Reference I
Vrei

__ j

l" '"'
~ - --- - --
Sw1tcl'led%
al TP35 and TP36. 9% of Full Range: -0.306V,
Full R:Jnge: -3.395'1.,
The comparator latching levels me set by dividers R15l/Ri52. Resistor '
Full Scale: -6.789V. ladder Increasing count
and Rl53/Rl54, their value3 allowing for bias current error in
R144. 'The comparator's output is open-mller:tor when the A fixed positive version of this Full Scale value is also generated '"""a""
voltage across R144 is less than 1l1e positive or negative latch (Q66/D30/D31) a,: a reference for the tracking ADC M38 at
level. Line drivers Q90 and Q91 a,c cut off, so the UM ST line M38-27.
alJ6-70 is pulled to+ 15V by AN2 in the 1Kde1cncc Divide, (puge UUT'I IVl3h, logic-'J - Count up

11.4-1 ). 9 3l}JI..~ fll'a(l",!d119 ,./\[)Jt"; Mlttl

(Figf).4)
When the levelisexceededineitherpol:rrity, then either M49am
M49b output goes negative. This turns and Q91 on, pulling
the LIM ST line to -15V (in-guardlogic-0). 'fhesignalispassed
l'/2138 is a 'System DAC' whic:1 can be ;::mploy:x! e~i:her in 'READ'
m 'VVRJl1E' mode. 'I.YRITE moce is not used for this function.
121<J~
to !he CPU via the seriru data link. In READ mode t'.le binarJ ca,Jnt cm be output cor:tinuous!y from M37b logic-1=Counl down
M41i'.J
This limit is set much lower thm the h131Yd cummt limit of the t.he ten pins DJB 9_0• NT! internal 10-bit counter is clocked at l 6kHz Oulpul
buffer .If exceeded, the instrument displays 'Error OL°, described into pin 9 via level shifters Q53 an.d Q54. The counter can be !negative) Rib

in Section2 (Fauh Diagnosis). ][n overload at 35-40mA, a built- controlled by two level-sensitiv1;; inputs: CONR 1 ar.d CONT 2
in margin of safety rulows the msh!]ment io meet most of im = +5V; ;ogi,:::-0 = as follows:
specifications. <CONT Jl CONT Z Efi'il'rcd: il])Jill Cm.mi
0 0 not used
0 1 Incremented

AE mentioned earlier, h i;; nece§smy to track the coarse

1 0 Decremented
l 1 Frozen
stepping rate to the settling time irn·::;cs;ed the DC Reference
filtering. A tracking Analog-to-Digital Converter (ADC) is used An intemru :l 2ill rnference resistor and switched resistor ladder
to synchronize stepping, ensuring the fastest poi;i;ible settling form a divider between pin 27 (V REF) i.md pin l (RFB). l'heir
time at the selected frequency. junction is pin 2(0UT 1). (SeeFigs.9.4
To set circuit conditions for the required output within a range, The ladder is i;w'.tched by the 10-bit counter. At zero count it is +7V 12k 12k 12k
:s
the gain of the main VCA set in response to fine amplitude open-cir:::uh; as the count i.s increased the ladder resistar,ce - --y\lV\,'lri~---,

information, in the form of an error signal from the Sine/Quasi- reduces in inverse proportion, until at full count of 2 11 - 1
24k
Sine comparator. For constant output amplitude gain, the (conespondh,g to the insi:rument Ful~ Scale output), it reaches its
error loop gain also needs to track the coarse amplitude stepping. minimum of 12W.
At Fllll Scale (FS) the M4lb outpunoltage is -6.789V, into l\B' S-3
For an outline of the Output Amplitude Coni:rol refer to
the descriptions i.n sub-sections 9 .1 and 9.2. and :he fixed reference into V RE? is the positive version of this
input, so at FS the OUT 1 voltage is balanced at zero. 11

6---1---1/l-----<I----Jl,.__ -
Use of 'REIF+' For instrument output values below FS, !he negative M4lb
(Circuit Diagram. 430446 page l l .6~..?) outpai v<J]tagc i,-; fo:,ea:rly reducr,d, _;o that the OUT 1 ·,o!tage
our 1
tends to im,-rease positively. By feeding an external r:omparntor
The ADC requires a vohagc input which Lrn.ch the value of
t t t
instrument AC output demanded by the user, with settling times
imposed by the Reference filter. The DC 'REF+' volt.age exhibits
!.hese chlltacteristics, so is UGOO in tins o;:;ircuh w determine the
numerical value of the ADC binary output.
whichdrivcstheCONT 1 andCONT2countercontrols, t.heOUT
1 voltag.., is used to provide a:.nomati;; control of i.he coum itself.
Ln th"o case of areduc ,d oatput demar:_d, a low;;;r coun, is required
to increa.se t.lie resistance of the ladder, resetting OUT 1 to the
--·i-·---1-·--1-----!'IIY-1
(MSR!
SIT-2 BIT-3
-L=~i.-J 11rr-10
llS'1!)
0
R,,.,><Jb•od,
zero balance,

- - - - - -- ---- -~-~----
95
9tJ.2 3 VU111ciO'lf.J C:;mJJiU(;;lt(.T'
rv~37 ii ah,1gh-:,;pe.'oddualcompilYawr, ·,1hJdrncceprnO Jf l l'I.S sts
irJput '.'oltsge, Ed o::onrroJ,: th,. M:33 c,)1m1nr via itc CONT 1 a:·d
CONT 2irn,:mts. The 'Counter Preeze' mndition ofM38, resulting
from both COJ,ff inputs bein.g Et logic-1, allows hysteres.is bias
io be z..pph:;d .he .:.:.imiiarmor ~o cr.:.at1;; a 'DeadBund' -,,in~ow.
Each of !I-,;;; tw..:• o .. q:mts oi M:S 7 r1c:ipo,,ds .;,;i il:l. h,i;,.:i! h, th'- Sf311I,e
wz.y: hig,·, iir;,pe1.:anc w\en its ..-i.m,-in,• c:rthg ~apl'C is m,,,.e
c.

po~ iti ve tlism its lnvenh1g i11put a11<:l pulled kwv when Lh~ h1verting
;nput is more positive (uncrnnmitted-collector).
M3'i a is oom1ec,ed :m a non-inverting device, but M37b inverts
its input. 0 ur
1 is inpat to born
circuits. Both inp.its are b:.asscd
by apprmdma~ely 151·1V to g:nerate \he :1ea :1-bn1.d hysteresis: 0
rr:1c.• !IJ.2; FillNJ.JCNI! COA:sPAfYH'0,-1 AC:TiON
..._=-====-=- -,,.5'.'l!!l!l" _, .'!1!!11111!1-,e ~ - - , ~ : ' " " . = ! ! ! ' -
I
,·JllllE" ,,,_..,_.,,_,,_.,.~l!!IEEr.:'T"',f

M37a by R96/R9S!, R3'/b by lUOO/R101

9.~t2.4 At~tion nu our ·i ~ J.:eiju

Because of Lhe bias, both M37 outputs are pulled low when the ~-~ . 2.6 1u~hlit r.;ighai .. tri1.. A.naioiJ Con\ierleirs
Vultage ll.L QUf J. ls ,..c.m. Tii.,; inverl.mg l::Vei-shiftern Qc7 !llnd M42 and M43 binary inputs are identically comected, so they
Q68 <}e i/)th i;Ui off by -157 OP thci·,r !;.211'.ef. SO C(1iJsJ'T ] 11!:;,d both behave i.1 fua: sa:-.1e vury.
CON'T' 'J., ~ve at logic-1. M38 i~ th•.•s p1•t in the °l1,e?,1,e' •xm,fai.f'n.,
so its 10-oit output value 1s held.
fu this condition, I,li.36-12 andM36-13 inputs are both at-I5V, so Cos.11nt rO t:itP ~
M36-10 is also -15V, R99 is therefore placed in pl!.Tallel with high '
RIOO, bcreasmg the bias on M37t. The bias on M37a is also V!rrii
increased by Q69 being cut off, placing ANH and R97 in parille1 l
with R96. The 'Freeze' wis.-,do-;v is fuerefoce widened, lo iim.prnve
'ow
LJJ C/~ Q
I.he comparator's noise rejection. (Refer to Fig. 9.6.)

F::,rlo'Ncounts the resistance between Vin mdO/P 1 is 1arge, an:Jl

When a.iser demands a new (greater) output from the instrument, small between Yi11 a.nd 0/F 2. The condition is incremerttal!y
REF+ increases as the Reference filter settles, and the OUT 1 reversed as the cou,,t increases to high vaiues.
voltage becomes ,norenegati,1e. The tias onfvI37biseroc,:,da,,d
M4l3
finally ex::eeded, so M3 7 -7 is placed at righ :,,tpetlance, pulled
A,;, 'Ne have seen; m increase i.1 user ,:iucputderr;.a.11dbc,eases the
up to Cornmon-2C by ANI3. Q67 conducts setting CONT l to
DC Referencs vo:tag~ REF+, so 3. higher ADC cou:1t results.
logic-0, which increments the count w step up the gain in ih1;o l V
This reduces !he resistance betweenM43 ::,fa 15 (Vi.,) and pin 1
Buffer.
(0/P' 1), and increESes the resistance between Yin mid 0/f' 2;
Sinul~aneously, M36-I2 is set to QV (:n g:iardlogic-1). l'Vi36-10 increaSing the gain of the 1 V Ruffer ar,,d thas increasing ti\e
rises ~:om -1:V to OY, switching R99 to shurt R101 instead C)f irstrrc-nent output. This i.;; tr,e stepped c::,arse gait, aijustmeni
shunting RlOO. Q69 conducts, switching Ri:::7 to shunt R92 referreC: to in sub-secti.on 9.2.
instead of shunting R96. The bias levels shif'c back tD 15mV,
M42
narrowing the hysteresis window.
M4 2 has a different function, The fine adjustment of output value
If the user had demanded a lower output, OUT 1 would have is bcorporated in the 'Gain Error Loop', b which the output
become more positive, exceeding M37a bias. CONT 2 would si.,ewave and quasi-sinewave are compared. lhis cc:11pariso:1
have fallen to logic-0, decren1enth1g thecounternndreduci.11g the generates the 'AC AMPL ERROR', to be used in controlling the
1 V Buffer gain, The effect cm the comparator bias would be the VCAgain.
same as fer the in:::renenting case.
The error loop thus also passes through the 1V Buffer, and the
ft~ the counter changes its numerical value, M38's internal effect of im inr:rea.se in ADC count wo-cild he to increase the err,,,r
resistance ladder is switched to back-off the OUT 1 voltage. loop gain, possibly overloading the VCA input FETs. This is
When REF+ finally settles, the OUT l voltage once again enters prevented by reducing the gain of the error amplifier M4la, using
(m1.d ,xi.dens) ,.he compari1tor':, der.d bcm.d, The countfreez,,s, and M42 :o track the <:tepr. of me coarse g3.in adjustm:c,1t.
the 1V B •.1ffer gain :remains cons•ant.
With a.nincre;;ise ofthc. ALlC 1.0ur•., M 0;.Iafeecfback is ii,cr.;;ased,
Thus the OUT i •mlt:1~e remains clos~ to :1:em ru; the cam:rarator as the resistance bct,pcen M42 p;ns '5 and 1 is r0duc,xJ.. This
and tracking ADC have a sensitive response to !he variations of reduces the error loop gain to compensate fo: the increase due to
R2F-:-; buLonce settled, !l-1c w;,Jer hysteresis wmdow p,e,1ents I.he M43. Thus the fine gam remains virtually constant over the fuil
cr;mrAral.rnr from cesf'._md;ng lo noise span uf coars'o ga.in adjustment.

------ --·-----· - -·--····---- - -·--··-·- -··--------------------

96
 E
The circuits described in this section Detect excess currents in i:he output circuit, providing a status
functions: signal to t.'le CPU via tJr1e Control Interface"
on i:he PHi (I+) output line, providing
a Stal.us signal to the CPU via the Analog Control faterfaceo
Switch the generated 10V range to the model 4600 a.,alog
control bus, as described h1 section 73Jl. For da_vity, lhese
cmmectioru, have been onntted from 9. 7
the :millivolt range outputs:
§lmV t!ll 1,i[J)l[)JmV on the AC Jll[)Jl[)JmV Rallllge The circuits in this section are located as follows:
i[J).9mV t!ll Z[lmV on the AC Jll[)JmV Millivolt attenuator & sensing: AC Assembly"
'9JOµV to 2mV on the AC llmV R2lfillge Power an1p11rncai:10111: Power Amplifier Assembly.
Output control: DC Assembly.
Sense the voltages at the output ter:minah; (or at the load in
'ferminalls: Mother Assembly and
Remote Seru;e) and scale the signal to the lV RMS Full-
Terminal Board"
Range level for comparison with the quasi-sinewave.
A sinlplifi.ed block diagrll.m of the low voltage ;mdrouting
Provide swilchlng of AC output,
Sense, under the control of signals from the Control
appe:irs in 9 .7"
mterfaceo

IA© 1@Vs;100\I

tlC iX: M@thl'M'

tli!Si!Si!M'iiu@/5f f!iiils@m/J/Jf /!J3oom/JIJ!
l!JiiJS®ffl@Oyf Ass®m/JJffJ!
10V
£©1\/ K+
Pioll(6\C\f) l"NIM i"i-11 i+

ml/ In Local Sense

2A ffirn:r~@i'il ©U!;>OJ! (2-wire ), only
fll'K@ir Hi 11 Lo used
-Ol'il<l~
!or Clulput

m)
SMl(A©II) ""11M i*ll m

to
Transfer S!.o(!ICV) S!.@M S!.o IL@
Switch
l.0ool/
Rigm@t©
Senea
SWliohln~

I-
l"L<>(l>CII) '°L@M I"!.@ 1.

9-7
The following description follows the 1V range path from the
VCA buffer to the Sine/Quasi-Sine Comparator (at the input of
the tra..,sfor switch The lOV a,,d millivolts outputs and
sense conditioning are included, the outputs also being sourced
from the 1V Buffer,
On the circuit diagrams, tlte contacts axe shovv:n in the u.n-
activated condition.
'\lifhen in Remote Se:r;u;e~ t_¾e po,;,;ver reti-1m line is
For High Voltage output and High Voltage sense attenuation
linked from J5-29s via lA fuses F4 and F3 RL14 and RL15
9
refer to Sections 95 and 9.6.
contacts to become at J5-23.
(For DC voltage outputs, tl1e four ACV lines at JS-25/26/29/30
are disconnected by the Range relays and the ACV relay RLl Oin
the AC assembly).
(Circuit diagram 430446 Page 11.6-3)
The 1V Buffer (page 11.6-3) is described in sub-section 93, as
(Section 7)
partoftl1eoutputrunplitudecontrolcircuitry. Itsoutputsinewave,
signal 'AC 1V' rangi,,g between 0.09V and 2V RlvlIS is fed out of The PHI(V) and PLO(V) lines 1'!1'e routed to the ll+ and I-
the Sine-Source assembly on J6-41, via the Mother assembly, terminals on t.he front panel exactly as for DC 1V outputs.
and input to the AC assembly on 17-41 (page 11.7-1). can be found in the
u,,M.:111.n,cm,sof tlte processing and
sub-sections of Section 7:
9il2,2 /AC /!)lOS,S<!Calf'(rj
Output On/Off: 73.6.2
(Circuit diagram 400844 Page Remote Sense: 73.63
With the l V selected, relays RL7 (1 V) and RL19 (lkV) Remote Guard: 73.6.4
are energized, but relays Rl4; 5, 6, 17, 18 and 20 are not. h,,snu,hcHJP Detection: 7 3 .7 2
Therefore the AC 1V signal is passed directly out of !he AC 73.8
assembly via RL7, fuse Fl, RL19 and fuse F2 to become the
Power-Hi signal at J7-27.
The power common
Common-2 supply at the siar -J:,OlllH-rn:rm1m1-.ct1
the energized contacts of AC Voltage The SHJ(V) and lines are routed from tl1e ]HI! m1d JLo
31. terminals on !he front pa,,el exactly as for DC 1V outputs.
uc;;;;~:,rn:~ and routing back to the DC assembly is described
PHI(ACV) travel vi.a Lh.ell/fother =·-~·••w.,, in Section 7, sub-sections 7 3 .9 .1 7 3 .9 3.
DC assembly at J5-25 and JS-29 :respectively

11
selected) ·with
RL14 and 15 Me

for Remote or Local Sense~ Rexnote or Local rGuaid~ and fron1c the Mother as1,e:rrm1,·, at }5-20~
On/Off. Rl.. 15 contacts~ TP9 and R98, to JS-26 as
ff 40 or 50 is fitted, the terminal lines are switched for
\ 7Vhen neither via RL15 contacts ax!.r.i JS-30 as

"Vilith Rem.ate Sense 1.1ot selected, ItL14 is ""'0 ' ' ' 00 ' '0; ' M A

This PCJB ,w"'·''"'"" direct co11.c.riections for the RL.14-9/2 short to the povver I-H oui}JTit
route to the instrument tennimi!s. RL14-2/3 short to tl1e i:::crvveT L0 ou~/??Jt 1PL0('.l).
axe ro11red from J5-26 and JS-30 via
the IVlioLlher
9J,4,::L2 /JM';
(Circuit diagram 430844 Page 1J .7-1) A discrete runplifier is used to provide the slew rate up
passes via the energized contact of i:he AC Voltage to 1MHz, all time set well above 1MHz, witJ1 the
selector relay RLlO, to be referred to the Sine/Quasi-Si.ne into its follower circuit
comparator transfer switch common 'SIG LO'.

With the
so SI-lI(ACV) appears at RL19-11 as 'SENSE Hi'. RL139 RL149 FL15
(Refer to the circuit cm2~1mH as sho·wn in the

With the 1V RL8 (1 is energized, i:hus

SENSE Hi is to the m:in-i.I1ve1tLng input of the Sense
Amplifier via Rl26. RJL14 is un-energized as shown, so the The
inverting input via Rl 15 is referred to Sm JLO. total input capacita.,ce is thus reduced to 1-1.SpF.
1'he differential input amplifier, dual FE1'
RJL3 (lOOV+lkV) is energized, v"'"''-"CIL'':t: ihe Sense
capacitance md low input current Q36 n1rcwu1,·.~ constant-
output to the Sine/Quasi-Sine comparator transfer switch M16-
current drive to 2ind the '""'·n<o'7c~,,,.., followers Q38/Q39.
ll (page ll .7-3 ). The ruu1J1u.,.c1
Rl07 permits initial DC input-offset cancellation. The stage gain
is low.
Emitter-followers Q34 IDd Q35 buffer the hlgh-impedancelow-
gain FE1' stage, a differential signal into ihe gain
The srune amplifier is used on the lOV, 1 V, lOOmV, lOmV and This a_nrangement has the advantage
lmV ACRanges. tobufferthe of placing an the gain 1.n one stage. The single-ended drive to Q3 l
providing a high impedance input, low DC offset aJ1d fiat frequency output stage is taken from Q30 collector.
response. Q24 and form a cmrent mirror to equallize the collector
On the AC l V and ,nillivolt ranges it is connected as a voltage- CU_11Yenm of Q29 md Q30, preventing injection into the
follower, sensing always carried out at ihe 1V level. The sense =,,..,,~,_~, power rails.
1V Ra.nge sense originates at the load in remote sense, or L6 and lL7 isolmte the ruuvuuc1 from tl1e 15V supply
in the DC assembly in local sense.
at HF. CSO is the main frequency-respollllSe compensation
For the nullivoli: ranges the 'AC 1V' drive signal to the millivolt c1:J1oa,:11.cir. ~,~A·,.;.,i;~ 0 smooth roll-off, with gain at around
attenuai:o:rs is sensed di.rectly (see sub-section 5MHz.
On the 1V Rmge, filie output from is returned at low
impedance, !iS lll>l1V-N>Ht,<J~UV ii.he amplifier input, via
!.he dosed contacts of RL12-8/l4.
Separate arrangement§ !illre made for attenuation and scaling 011.
the lOOV and lkV These1JJedescribedinSection.9.6.

9-9
The basic 1V inserting a s•.vitched,
attenuator netvvork. Th.e circuit com1e-cts t:he selected
millivolt output via RJL4-13/9 and RL19-ll/3 co Ll-ie
T'neAC lV contacts
line, not 'PHI'. Thus t.'1e two Sense
13/11 of U:iil-e:neJr,gizea RJL7, and
I-Ii and Lo terminals are used to connect to the load.
netv1ork.
The softvvare forces Re1note Sen_Be OFF ]n ir1e :a1illiv0It ranges.
The fixed chain (fonned Rl20 in series with the paxallel
Except for a series resistor on the lmV range, the AC l V
combination of Rl 12B m1d RllO) is perrmmently cmmected
signal is connected directly to the input of the Sem;e A:rnplifie:rvia
between RL?-11 imd ulie Common-2 star-point. Three levels of
RLl 1-4/5 atRL8-13. The amplifier circuit remains penna_nently
attenuation are achieved by switching Rl 12A and Rl 18. Relay
in its non-i.i-iverting configurntionfor all three millivolt ranges, so
RL5 is energized for the lOmV range only, RL6 for the lOOmV
local sensing is carried out at l V range levels.
range.
Thus the output value at the terminals depends on both the
The three =~ngements are shown in Fig. 9.8.
calibrated value of the AC lV signal and the division ratio oft._lm
attenuator. In addition to the 1V range calibration, each millivolt On the lmV range, the series resistor Rl54 is connected between
range is also' Autocalibrated' separately (refer to User's l-l and.book RL?-11 and the Sense ,-.,. 0 ,,,~,.-· input via RLll-5, but it is
Section 8). shorted on the 1Orn V and 1OOm V ranges by the closed contact§
of RL5 and RL6 respectively.
enerj.;ized on all millivolt :ranges. 'The arcenuator
"'"·JL.n···ur, and RLl 9-11/8 to the SHl(ACV)
filtering noise at HF.

f.lC1V
To Sense
Amphh;r
R15.0,
R120 100
10.0:,

R112S R110 R112A

'12.343 11111 100

OV{2}

To Sense

Fll20
10011

R1120
12.3116
 The AC path is blocked by the integrator M 17, but is applied to
the non-inverting of Ml9 through ithe coupling capacitor
C56. M19 operates in open applying its output to the
As noted inwJJ-section 9.4.1, the l V :Buffer is part of the povver
delivery system for all ranges. On the 1OV rai,ge its output discrete power amplifier (see 9.4.7.1
1V) passes viaJ6-41 from the Sine-Source assembly and into the
Power Jvnplifier assembly (PA) at J9-36 circuit time consta.,ts bei,,g selected to allow overall i111Stmment
the full frequency range of 1OHz to 1MHz.
The AClV signal is amplified by a factor of 10 in the inverting
lOV Power A..mplifier, whose output is on the 'AC
lOV+lOOV' line. This lOV ra,,ge retun1s to the AC
assembly at relay contacts RU 7-13/4. It passes through RL19- Ml 7 a,,dM19 aresuppliedfrom±15V common-2Arails, butthe
2/5 to the PHI(ACV) line at I7-27. discrete amplifier receives power from the ±38V supply.
The lOV range outputs then follow the same route (to and from
Lhe output terminals) as the 1V signals. Whether in Remote Sense
or not, the sensed voltages return via the SHI(ACV) line to the
same Sense A..mplifier used for 1V range signals. The lOV FLAG line, cmmected to TP12, is pulled up to OV (in-
guard logic-1) in the Reference Divider assembly (page 11.4-4)
With lOV range selected, ithe sense amplifier has an inverting Al"\J2-9/1 (lMQ). The Error OLmessageresults from this line
gain ofO.l, returning the signal to the 1V Range levels required being driven to logic-0.
by the 0u1c1'vucaJL&.,-0me;; comparator.
RU! is energized for the AC lOV Range, so overload detector
reaches Vbe threshold on output current when the
RMS value in Rl39/Rl 72 and Rl41 exceeds approximately
80mA. Similarly, detects peal\ currents in Rl47 and R149/
Rl73. fa eii:her case, the co1r1mKt1on pulls TP12 down to
The AC 1V signal enters the <JL~1,eu.m1.v at J9-36, passing to the
inputofthe lOV Amplifier via relays RL4-9/13 andRU-9/13. It -15.7V. The lOV FLAG line is driven ID logic-0, so the status
is referred to Co:mmon-2Ja "'"''1"'"i'"' across Rl24. message is returned to the CPU via the S SD A serial interface, and
the Error OL message is displayed.
The amplifier has already been described for Lh.e DC l OV
in this text, the effects on the 1OV AC Range of its sepa.rate DC This does not preclude further increase in output current, but the
and AC paths are considered be.low. accuracy specification is not guaranteed.

The DC path is blocked by C56; Ml 7 is the DC amplifier, If the RMS output Clli"'Tent increases to approximately 100-mA,
connected as an integrator with diode clamping. M 19 operates as the peaks of current cause the Vbe thireshold of Q28 or Q30 to be
an inverter in open so high DC gain ID the output exceeded, shunting the base current of the corresponding voltage
fromM17 onM19-2. amplifier. This hard-limits the output drive to the final stage.

The outpm from M19 drives both halves of the symmetrical,

inverting, discrete power amplifier through current-limiters Q21
and Q24, and is buffered by emitter-followers Q22 and Q23. The output current passes through the combination of Rl 44 and
Common-emitters Q27 and Q29 form a voltage amplifier, driving Lll. At low frequencies the inductor provides a low output
the complementary output stage Q32 and Q33. Input md impedance, whereas at high frequencies the resistor stabilizes the
feedback resistors Rl 19 a,,d R120 set the gain of the discrete amplifier when driving capacitive loads.
stages to approximately 4.5,
The forward amplification contains three inversions, DC negative
feedback being applied to Ml 7 inverting input by R122, defining
!l1!. overall gain of 10 in conjunction with input resistor R123.

The DC pai:h senses and corrects the DC offsets throughout the

whole AC amplifier, referring the output to Comrnon-2A at Ml 7-
3.

9-11
 (Circuit
9tl'U3, 1 G@u'llSl!i'all
A common sense amplifier is used for rhe lOV, lV, lOOmV, On the lOV RLlL!- and RL3 are both
1OrnV a,,d lmV Rangeso Its main purpose is to buffer the se:ru,e RL8, RLll, RL12, RL13, !tL15 and 1lL16 ren1ain un-
voltage, providing a high impeda..11ce i,,put, low DC offset a:nd f!at energized as sho';Nn in_ the
frequency :response.
Th.e 'SEJ:JSE I-IT 1
is :routed to the of the
The oneration of the
_;_ -- 1\mnlifier
- Sense -_,_ for
- theA.:.C 1-1/ ~nd
- -rni111volt
·--- the closed cont&cts ofRJ_,14 and resistor Rl 15.

The AC millivolt ranges' outputs are simply Lh.e AC l V :rm1ge T'ne output from is returned via Rl21 as feedback
after passive attenuation; tl1ese levels are not sensed directly The
O to the -~··r~.--· inpm, the contacts of RU 2-8/14 being openo
AC 1V signal is sensed before anenuationo
Thus the circuit is configured as a.n inverting amplifier, resistors
On Lhe lOV range an i,,verting configuration is errm1,=iv,ccL The Rl 15 and Rl21 scaling the sense down a factor of 100
circuit divides by 10, scaling the sense signal down to 1V :range Extensive screening is employed at the arnplifier's virtual ground,
levels, for input to the comparatoro bootstrapped buffers and lo follow the virtual-

Separate arrnngements axe made fm auenuation and scaling on corrunon potentiaL TI1i.s reduces the input ""ii-'"'"""·"'"~, which is
further compensated by feedback capacitor C60o
the lOOV and lkV ranges These are described in sub-section 9 060
O

The instrument includes two :rnngeso The 100V

rnnges extends from 9V to 200V full scale, the
90V to l lOOV full scaleo

'"~C ciicuit Bxra11gernent and

flow The <let~jls of ilie lOOV and 10DOV rn11ge3
O

are described in sub-sections 906 and 9]"

but the
necessary to generate differ from those LTl the lovv
voltage loops:
On the Jli!l!i[])V rnllJlge, the AC l V is switched
into the 1OOV ""'·u1-1u11c, vihere it is scaled up a fac~:or of
100, the ~••p~,,~, being delivered via ,J,e 'AC
li.,e on the AC cc;,,e,i.ucny

01 The em.qJ1u1•c;1 gain on the 1000V rai.1ge

is controlled by feedback from the trw1,fom1er sei;m1mrrv

into the of the 1000V Error Amplifier. The "AC lkV'
line trm1Sfers the transformer m.itput to the AC 1:2ssembly,
where it is switched onto the PHil(ACV) lineo

9-12
 !n\lJYROrDUCTiOLl'l!l
(Circuit Thel'1.C 1_,V atJ9-36,
,,~.,;<cnm,v 1:o the
The AC l V signal, generated by the 1VBufferin t.h.e Sine-Source via dosed relays RL4-9/13
assembly, enters the Power ~_u'"l-"rw,;, as fm the HlV range; but and RL2-8/4. It is referred to Cmrrrll.on-2B by a
Lhe lOV Amplifier is bypassed for the high rn,,ges. across R72.
On the 100V HL7lge, the signal is switched into the lOOV The 100 \1 .-'""""""'""· described hx. Section 7.8~ vvhich deals with
where his scaled up a factor of 10{), the ~"''~"~""" the lOOV DC ouiputs.
output delivered via the 'AC lOV+lOOV' lLne to the
The desCJ·iption is sub-divided as follows:
Pl--ll(ACV) line on the AC assembly. Thereafter the output is
trnnsferred to the insLroment tenninals as for the lOV range. 7JU
7.83.1
7.83.2
7.833
7.83.4 Driver Regulator
and llJJ-3; 7.835
7J3."5J
'AC 1 V' enters the Power Amplifier asse-mbly at J9-36 (page 7.8.4.1
11.9-2). Relay RL3 is u,,-energized, shorting the lOV fa\.rnplifier 7.8.4.2
input; andRL4 is energized, routing Lhe AC 1V 1OOV 7.8.43
1''Inplifier as '100V I/P' (page 11.9-3 ). 7.8.4.4
7.8.45 !-leoJsinkRenwval
Relay contacts RL2-8/4 apply the signal to the G.,in Stage, which
provides drive to the power amplifiers in the positive lilldnegative
heat sinks, viaJ3-12 andJ3-1 l. The single-ended output from the
heatsinks at B-9 passes via R89, L7 and relay Rl.2-13/9, 10 RL3-
6 (page 11.9-2), lilld onto the 'AC lOV+lOOV' line via RL4-4/8.
On the AC as,;en1bly the signal is routed to the
PHI(ACV) line as for the 10V ra,,ge.

9-13
TI1e power for the 100V P~m,pun,or am The 100V AC' line is set to
also described in Section 7.8. rmge is selected, Driver
vem,rww1c, the short fro1m R3 7 ~
The is sub-divided as follows:
to operate. fa normal use, links Uill andLKC are not connected.
7J3S Thell test purpose is to allovv the current r.a.irro:rs to be
7.8.5.1 the level-shifters a.-n.d
Most of 1he output current for the heatsinks passes
7.85.2
the series combination of R34 fu"l.d D27? the negative
7.853 400V Current Control
currents R9 and D4. As both and negative
7.85.4 100V Cv.rreni. Sense and lkV Ovavolts Detector
only the circuit is described.
AC
Curtent rnimir Q3 diverts approx. 1.8% of the supply
cuaent into t..he level-shifler Q4, R3 6 and inro tl1e common reistor
R37. Simil!rrly c1raws currentoutofR37. Under no termh,al
7oilo6 load conditions these two currents file balanced, even if Lhe
7.8.6.1 Proteciion output
7.8.6.2 ±15V Monitor
7.8.6.3 ±38V Jl;lonitor
7.8.6.4 ±400V Monitor
instantaneous current flowing i..11 R37 alternates in ~Y'"·"'u'""'''"
with fue output
§@£1;§1@ cur-tent increases, So the
430618 across R3 7 is an of the output load cmrent, and can be
T1ne a scaled reference
the PS/I Heatsink at Jl-8/6 m1d are filtered i\ \/VD.1.do\v cornparato:r is fonned f:rorn tl1.e ~:'"WO halves of M2 aI1d
LPl B.111.d LP3, 'These the to both halves. The outputs at
aTe visible froxn tl1e top a11d rear of the iIIBtrr1ment 'When the P Li'L
board is c"v,,~,,Vs c1<2u~:,auu1b ]s present the corJect
iI1 the reference zeners D9 and
lines contLn.ue on to po~ver fue d1iver stage of d1e in the 400V ]\;fonitor ci:rcuh. UrnJess
where fue is "'tsc,w.uc,·'" as described in R37 exceeds this level, both M2 outputs will he
para 7.83.4. R20.
The 100V FJLAG' line

the 100\1 r2u1ge, the c1trrent in each greater than 2.45\7 overcoxnes t.he bias on one half~
of these lines is used as &I]. of the load on the its output to fall to -15V, in the lOOV FLAG
fue 1000V rru---ige? @y overload is sensed a. This signal sets limit detector latch
series detector in the DC o,;,,,"''"""Y 7.12.7.1.

TheJ.\C 'V B-uffer h-i tl1.e Sine-Sou.rce is upto 1000V levels

asse.mbly~ enters the PcnNer L4mpHfier zw for the 10\1 rsi11ge; but by one of two (LF or HJF) !nmsforraers, whose seoondary voltage
the 10V Amplifier is bypassed for ihe high voltage ranges. is delivered villi the 'AC lkV'line to tlle PJI-Il(ACV) line on the AC
assembly, Thereafter the output is ttmsferred to the instrument
On tlle 1000V :r8-.J.'1lge, ,;he signal is switched via ithe lkV x2
terrrnnals as for the HIV range,
Amplifier and lkV Error Amplifier, before being applied to the
100V Amplifier.
9.7.2 1000V RANGE POWER ROUTING 9.7.3.1 Gain x2 Stage
(Circuit Diagrams: 430618 pages 11.9-2 and 11.9-3; (Circuit Diagram430618 page 11.9-2)
400844 page 11.7-1; 430537 page 11.14-1) The AC l V signal is muted via relay RLl-8/4 to be developed
'AC 1V' enters the Power Amplifier assembly atJ9-36 (page 11.9- acrossresistor R 160. It is filtered by R 162/C30 and applied to the
2 ). Relay RL3 is un-energized, shorting the lOV Amplifier input; non-inverting input of M15.
and RU is energized, routing the AC l V signal to the 1000V The feedback divider generates the x2 gain in Ml5; Rl59 and
Amplifier chain. C67 providing HF lift 1:0 compensate the step-up transformer
Energized relay contacts RLl-8/4 apply the signal to the Gain x2 responses. FET Q35 adds C68 on the 1OOHz and lkHz frequency
Stage, whose output is summed with error feedback, providing ranges, activated by the LF signal at logic-1, to boost the lift.
drive to the lkV Error Amplifier. Output from the x2 stage i£ applied to the lkV Error Amplifier via
The lkV Error Amplifier output is passed as 'lkV ERROR 0/P' its input resistors R156/R95.
via relay RLl-9/13 to the lOOV Amplifier (page 11.9-3 ). It iE
input through the contacts of un-energized relay RL2-6/4. 9.7.3.2 1kV Error Amplifier
The output from theheatsink atB-9 is transferred directly, as the The input resistance to M18a is split between R156 and R95 to
'OUTPUT' signal, to the 'lkV ENABLE' relay contacts RL6-8 allow the saturation detector to reduce the gain in the event of
and RL6-9 (page 11.9-2 ). Relay RL7 determines whether the LF transformer saturation.
or HF transformer assembly iE to be used, the OUTPUT signal
At the inverting input of Ml8a the signal input is summed with
being applied to the appropriate primary winding.
the AC lkV negative feedback signal, output from the selected
The secondaries of both transformers are connected into the High transformer secondary. The resulting error signal is amplified by
Voltage assembly (page 11.14-1 ). RL2 or RL3 selects the the two stages of M18.
appropriate output to be passed on to the AC assembly, via H-28
On the lOOkHz frequency range, the maximum voltage available
and Jl-22, as the AC lkV signal.
from the instrument is 750V. A tapping on the HF step-up
The AC lkV signal is also applied as the negative 'Error' feedback tnmsformer secondary reduces the maximum ou1put to this level.
to the 1000V !i!mplifiersystem. It passes throughR.138 andR155 The signal 'lkV GAIN' is thus set to logic-0 only on the lOOkHz
on the PA assembly (pages 11.9-1 and to be summed at range, cutti..,g off FET Q19 imd restoring adequate loop gain.
the inverting input of Ml!la-2. A single net inversion is present
The second stage, M18b, adjusts the bmdpass of the amplifier to
around this loop.
match the selected step-up trlllIBfonne:r:
On the AC assembly (page 11.7-1), the AC lkV signal is routed
]_OOlfb.: a!Dlrdl ].Jk!H[;i;: r2irng<Bs:
by the contacts of energized relay RL20, and through fuse F2 to
Q26 connects C58 and Rl26 across tl1e input :resistor R97;
the PHI(ACV) line at J7-27.
relay RL5 shorts R48, connecti.ng C34 and R93 directly
across the feedback resistor R92, also shorting C38 in the
output line.
rnwz ud ]_([))il])Jklfh ll'2lllllg®§:
Amplification to a maximum of 11 OOV is in four stages: Q26 connects C57 and Rl25 across the input resistor R97;
relay RL5 shorts R47, connecting C33 and R94 directly
JL G2tm x2 St2J.grB: the AC 1V signal is HF-boosted and across the feedback resistor R92, and leaves C38 dominant in
amplified. For the 1OOOV range the DC Reference iE scaled tli.e outp1.1t line.
in software, so that the AC lV signal Full Scale value
represents 11 OOV output. These measures give the necessary loop compensation for each
transformer.
:;t 1kVErrrnr Ampll.fier: fueGainx2 Stageoutputissummed
with error feedback from the secondary of the step-up When the 1000V range is selected the amplifier output drives the
transformer. lOOV Amplifier via RLl-9/13 ru; the 'lkV ERROR 0/P' signal.

J. 100V Amplifier: possessing a gain of 100, the output from

its heat.sinks drives one of two (LF or HF) step-up
transformers.
4. Step-up Tnrn.sformer: a ratio of 1:6.6 (LF) or 1:6.17 (HF)
allows sufficient gain in the system to provide a maximum
RMS output of 11 OOV.
The frequency response of the amplifier iE matched to the step-
up transformer in use. The 'LF signal into the amplifier is at
logic-1 (OV) only when the lkV range, and either the lOOHz or
the lkHz frequency range, is selected.

9-15
 1OOV AMPUFH:R
This operates as for the lOOVrange, butitsoutputsignal 'OUTPUT Relay RL7 is activated by the 'LF' signal, applying the 100V
is fed directly to relay RL6 contacts for application to the step-up runplifier output to fue HF step-up transformer for the 1OkHz and
transformer. l OOkHz frequency rnnges, and to fue LF transformer for the
lOOHz and lkHz ranges.
The l OOV Amplifieris described in Section 7.8, which deals with
the IOOV DC outputs. Tirie two lnmsformers are separately located, their secondaries
being connected into the High assembly. The HF
The description is sub-divided as follows: transformer is selected when RL7 is un-energized, its primary
7J33
being rerumed to Common-2C. RL7 is energized to select the LF
7.83.1 transformer, whose primary cu_ir:rent is sensed by the Sa1tu.ration
to Gain 0-YUJ Driver Stages
7.83.2 DC Offset Correction Detector.
7.833 Sign.a,! Processing
7.83 .4 Driver Regulator 9.7,5.3 Saturation Detector
7.835 Driver Output To obtain the required performance, the LF transformer core is
7.8.4 1 OOV Power Amplifier constructed from a material with high remanence. It is possible
7.8.4.1 Positive Heats ink Assembly for the lkV range to be deselected when the core is magnetized,
7.8.4.2 Negative HeatsinkAssembly and subsequently reselected in the same sense, with resultant
7.8.43 Over-Temperature Detection sanJiation.
7.8.4.4 lOOV Output Connection The Saturation Detector circuit is activated by sensing any excess
7.8.45 HeatsinkRemoval current in Rl 14, associated with the loss of reactance. It
progressively removes the signal input to Ml8b during half
cycles of the appropriate sense until the core recovers, then
automatically returns to its quiescent mode.
CIRCUITRY
The dual runplifier M20 is biassed by Rl 15-Rl 18 to approximately
1V on each input. Under normal operating conditions, the
Rl6
unsaturated oore reactance holds Rll4 current down, so the
Relay RL6 allows the OUTPUT signal from the 1OOV A__mplifier voltage developed across Rl 14 is insufficient to overcome the
to energize a step-up transformer, providing the following bias. The output from both amplifiers is of negative polarity, both
conditions are met: diodes D58 imd D59 are reverse-biassed, and FET Ql 8 is cut off
its gate being pulled down to -15V.
1'he :I.kV 1,igll:rn.D i1, &1t fogk-0:
This is a processor-oontmlledsigmil, set to logic-0when the When the core saturates, the current in Rl 14 rises rapidly and its
instrument AC output is switched on, in the 1OOOV range. voltage exceeds the bias on one of fue detector amplifiers. One
diode conducts, forcing Ql8 into conduction; ro the signal feed
'flhe w2tchdlog lbilll§ IIil@t •Bi:nr!tu,itil 'o to M18ais shorted, the current in the transformer core is reduced
On the l?A !ll§semlbiRy, the 'lkV ENAJBJLJE' !iWlittdbJ Sl!. fa 1,ett to zero, imd Ql!l is cut off again.
to 'ENABLE\ On the next half-cycle the curre:11tt is reversed, so saturation is
S l is situated below the left-hand ejector lever (viewed from reduced. H the core saturates on successive half-cycles, they
the front of the instrument), facing the rem- of the instrument. again activate the detector with further reduction. The process
It allows the high voltage to be switched off for servicing continues mtil the oo:re remains uru;atu.ral.ed over the full dynamic
purposes. A red LED glows when all oilier conditions are range of I.he primary current, when I.he detector becomes inactive.
met.
When RL6 is dosed, the OUTPUT signal from fue 1OOV Ampli-
fier is swii.ched through to the contacts of RL7.

9-16
9.7.6 POWER SUPPUES 9.1.6.2 AC 1kV Oveli'CiJWrent Detector
PROTECTION (Circuit Diagram 430536 Page 115-2)
For the AC 1OOOV range, so as to protect lhe step-up transformers,
The power supplies and protection for the 100V Amplifier are
overloads are detected directly in the output lines to lhe termmals.
described in Section 7.8.
For this range only, resistance is inserted in the PHI(ACV) line
The description is sub-divided as follows: in the DC assembly. The voltage across the resistance is rectified
and compared against a reference. li lhe voltage is excessive, lhe
7.85 P({}wey S'Upplies a111.d Pmteclti({}P1 ln!lir({}dl1ul!:ima
comparator generates a UM DET signal. At higher frequencies,
7.85.1 ±38V Supply (The 38V supply circuit is m.orefully
where the internal and external connections to lhe load will draw
described in Section 6.7, para 6.7.3.4.)
extra capacitive current, part of lhe resistance is short circuited.
7.85.2 ±400V Transformation and Rectification
7.853 400V Current Control The'AC lkV RANGE'signalentersatJ5-102(pagelJ 5-J). This
7.85.4 1OOV Current Sense and 1kV Overvolts Detector is at logic-1 to energize relay RL13, only if lhe 1000V range is
(This detector circuitry is 11.Sed only for AC High selected. RL13 removes the short from R107 and R108.
Voltage ranges, and is therefore described in sub-
The 'HIGH I LIMIT' signal enters atJS-98 (also on page 11.5-3).
sections 9.6.4.1, and 9.7.6.1 below).
When lhe 1OOOV range is selected, this is at logic-1 only for the
lOkHz and lOOkHz frequency ranges. It energizes relay RLl 2,
7.8.6 PA Power Supply Monit({}rs
shorting Rl08, so that higher currents are required to trip the
7.8.6.1 Comparator Supply Protection
LIM DET signal. As frequency mcreases, so do the currents
7.8.6.2 ±15V Monitor
taken by lhe capacitance of lhe internal tracking and wiring; Rl07
7.8.63 ±38V Monitor
is compensated by C45 and C49 to bypass this extra capacitive
7.8.6.4 ±400V Monitor
loading.
A diode-bridge rectifies the voltage developed across the selected
resistor(s). The voltage is limited to lOV by D31, and resistor
(Circuit diagram 430618 Page 11.9-6)
R84 sets the trip current level for the opto-isolator Ml 9.
On the 1OOOV Range theprirn.aryvoltage of the step-up trnnsformer
in use is fed as 'AC OYJERVOLTAGJE DRIVE' from RL6-4/13 The isolator operates from the 5 volts between -1 OV and-l 5V. fu
(page 11.9-2), viaRl 76 and a screened lead, totheM2comparntor normal operation Ml9 output at Ml9-6 is open-collector so Q4
input(page 11.9.6). (Theoperationofthecomparatoris described does not conduct. When the output current is sufficient to trip
for lhe 1OOV Current Sense application m.Section9.6,para 9.6.4 .) Ml 9, Q4 emitter is pulled low md so Q4 conducts, its collector
On lhe 1000V Range, Q6 shorts the 100V overcu:rrent sense current being drawn lhrough R79.
resistor R37; Q6 gate is driven by 100V AC at logic-1. M 18 is a switch which underno-ove:rloadconditions is biassed by
R79 to +15V; and wilh its output at -15V, itsnon-inverting mput
The HF (1:6.17) step-up transformer primary voltage is divided
is set to approx. -2V. When Q4 conducts, its collector is pulled
by Rl 76 and R180 (i.e. by 1/116), but for lhe LF (1:6.6)
down dose to the -15V rail voltage. This is applied to the
transformer RUH shunts R180 (increasing lhedivisionrntio to 1/
mverting mputofM18, whose output reverses to+ 15V providmg
124.5), activated by the l.F signal and Q43. The result is that
a positive trigger edge to Ml2-4.
overvoltage is detected on the HF transformer primary at
approximately 305V, but on the LF trm1Sformer prims.ry at For AC outputs the DC FNCT signal is inactive atlogic-1, M12-
approximately 285V. Taking the step-up ratios into account, the 3 at logic-1 removes the reset which is present for all DC voltlllge
lk V Overvolts Detector trips at LF or HF for the sairne secondary ranges. Monostable Ml2 is set to produce a logic-0 at its Q
voltage: approximately 1880V peak, 1330V RMS. T',rili; in I.um output (M12-6) unlle;m its A input at M12-4 is edge-triggered
activates lhe lOOV FLAG signal as on the lOOV Range. positively. lin normal conditions no trigger is given, so M12-6
remains at logic-0, D10 is unbiassed and lhe LIM DET line
remains at the logic-0 level of -15V.
WhenM18 output reverses to +15V, M12-6 produces a logic-1
(OV) pulse of lms duration, which forward-biasses Dl0, so the
LIM DET line transmits a logic-1 pulse of lms duration.
Successivepositiveornegativepeaksofovercurrentretriggerthe
monostable, maintaining its Q output (and thus the LIM DET
signal) at logic-l.

9-17
 uu,vr,iiffn400844 Pages 11.7-1 and 11.7-2)
The Slrll(ACV) signal, rei.umed from the terminals via the Relay RL13 is un-energized on this rnnge, so R124 acts alone as
Current and Output Control assemblies, enters the AC assembly the feedback resistor, producing an runplifier gain of 1/100. The
as for the 1OV range; but the 1V /1 OV Sense Amplifier is bypassed sense signals are thus reduced to 1V rmge levels. The ampmcu,,
for the high voltage ranges. out-put is routed through tli.e contacts of un-energized relay RL3
as the comparator 'SIG' input, Ito trl!JISfer switch M16-l l (page
On these ranges, the signal is switched Lnto one of two guwdled
attenuators, both housed in the Attenuator/Cage assembly plugged
directly into the AC assembly. Each attenuator is a separate
resistor chillll which acts as the input resistor to the inverting 1 SENSE
amplifier M32. The output of the amplifier is passed to the
Comparator Transfer switch. The Slrll(ACV) signal is blocked by the contacts ofun-energized
relay RL15, but RL16 is energized, applying SHI(ACV) as the
'lkV SENSE' signal via link LKl into the 1000V attenuator
9.8.1 100V SENSE AMPUFIER chain. The chain has ten 50W l % resistors in series, which
combine to form the input resistance for M32. The guards are
The SHI(ACV) signal passes through the contacts of energized
taken to equivalent voltage points on a chain of eight capacitors,
relays RL19 and RL15, and is applied via the four pins of J1 into
C70 to C77, again driven from the sense signal.
the l 00 V attenuator chain. The attenuator consists of four 25ill
0.1 % resistors in series. To eliminate leakage, each junction Relay RL13 is energized on the 1000V range, so Rl23 and R124
between the resistors is guarded, the guards being taken to act in p1rrallel as the feedback resistance, giving a gillll of 1/550.
equivalent voltage points on a chain of four capacitors, C64 to The sense signals are thusreduced to 1V rnngelevels (the 1000V
C67. The capacitive drain is also driven from the sense signal. ramge FS voltage is 1100V; the equivalent l V range FS voltage
The attenual:or acts as the input resistor for the 100V/1000V is 2V). The amplifier output passet. i:o !.he tr!llilBfer switch as on
Sense Amplifier M32. the l OOV range.
9.9 SINE/QUASIQSINE RMS COMPARATOR

Consirnnt-Ampliluc:le
Ou1pu1-0,iw Sin<!lwiw®
Sinew@ve (1\1-i'!i.nge RMS lewis)

Pllase Sync. RMS Outi:iu1·

!Em:,, Signal To ,emainde, oi l'!MS
Ou!pu! Control loop

wop G~in
Erro,
Compensaifion
Compa11rat!:i!Jl1
Quasi-Sima
Sequence Svroc.
Phase Sync.

Mas1er Aefa!!ence Sllu13/Qu~si-§On0

[.:h Quusi-sine\.:'J©U.;;J W10sn-squme
Sourcing Comp@IT'~ta:w

f~ccurnie
\'i~J1S Con~mi

Control
th.e 011tput value.
The main purpose of the comp9w.tot, m vvith the
IllVIS vclue to
track the value

also corrects output RMS

disturba_nces, within !:he instrument ~µc;;,,.;111·,.;~.'-''"'"·
The effects 2Te described in sub-sectiovi 9 .3 Q

lil. The reference quasi-sinew ave whose RMS value is set by the
value on the OUfPU'f Display, m.1.d is also modified by
stored calibration dat11. (sub-section 6.6).
lbl. The sensed and .conditioned output sinewave, which is
compared against the reference quasi-sinewarve (sub-sections
9.4 and 95).

9-19
Both inputs are scaled to 1V Range levels ru1d compared in an
(Figs, 9,10 and 9,11)
Integration/Sample-and-Hold system, They are sequentially The companitor is based on a ten-state recycling sequence of
steered through a common squaring circuit into separate 'REF' squaring, integration, sampling and subtraction, Operation and
(Reference2) and 'S:IG' (Reference2 minus Sense2 ) averaging accuracy rely heavily on synchrnnization between sine and
integrators, quasi-sine,
A capacitor and voltage follower samples and holds the settled At relevant points in fue following description, reference is made
REF integrator voltage, It generates a DC 'REF' signal which is to a specific output frequency of 500Hz (lkHz Range), as an
subtracted from the AC 'SIG2 ' signal, The result is applied to the example to clarify the following points:
SIG integrator, fuen another sample-and-hold circuit generates
illl, As the output sinewave frequency is varied, the quasi-
the 'AC ERROR' signal from the integrator's output
sinewave tracks an exact sub-multiple of its frequency;
'AC ERROR' is thus a DC analog of the difference between fue except on the lOOHz Range, where both are at the same
'mean-square' values of the two inputs, It is buffered and applied frequency, In our example at 500Hz, the quasi-sinew ave has
to the VCA via fue Error Amplifier, half the output frequency, The various relationships between
outputandquasi-sinewavefrequenciesfordifferentfrequency
ranges are detailed in Section 8, Table 83,
lb, The duration of each comparison cycle is always equal to ten
quasi-sinewave periods (here 40ms), and each of the 'C'
periods persists for one quasi-sinewave period (for 500Hz
output - 4ms), This effect can be observed using an
oscilloscope, say at TP46,
<e. Using this specific case also gives a point of reference for
examination of the circuit wavefonru; using an oscilloscope,

'Sense'
Sir.ewave

SIG 0-0
SIG
SWITCH
RMS H,
'Reference·
Oue,1s1-
S1newave

REF 0-0REF
SWITCH
-----
DC SUBTRACT

~IG llrefl'
9 SAMPLE

51G Lo
RMS Lo
\l2c

2C
Voltage-to-Current
Converter

FIG. 9.10 SINE/QUASl~SINE COMPARATOR w DIAGRAM

9-20
9.9.3.1 The Comparator Sequence
(Figs. 9.10 and 9.11)
COMPARATOR CYCLING PERIODS
The table in Fig. 9.11 shows the conduction patterns of the
·x· indicates that
5 clclcJclc
clclclcJc
switches in the block diagram of Fig. 9.10, within a complete
switch is closed 1 2 3 4 6 7 8 9 0
sequence cycle. The cycle is broadly divided into two similar
patterns ('REF and 'SIG'), each occupying five quasi-sinewave REFERENCE SENSE (SIG)
periods. The cycle repeats continuously. STATES PATIERN PATIERN

In the following analysis, the effects of the dosed switches are (a) Squarer inpui quasi-sine I zero sine I zero
described; all other switches are open.
(b) REF SWITCH X X X
lP'eirioe:ll§ Cl, C2 and C3 (c) REF INTEGRATE X X X X
a. REF SWITCH is closed to input the quasi-sinew ave to the
squarer. (d) REF SAMPLE X
b. REF INTEGRATE steers the squarer output current into the (e) SIG SWITCH X )( X
Reference Integrator.
c. DC SUBTRACT allows Irefl to be drawn from the summing (f) SIG INTEGRATE X X X X
junction.
(g) SIG SAMPLE X
dl. RMS Lo has been connected to common 2C since the start of
C0 in the previous period, in preparation for REF squaring. (h) DC SU8TRt1CT X X X X X

The quasi-sh1ewave is squared, and the result is output as a U) DC SUBTRACT X X )( X

current ( at twice the input frequency) into the summing junction.
The DC currentlref! is subtracted at the junction, a,,d Lhe residue (k) REF SWITCH ){ X
goes to charge the Reference (I) REF SW!TCH COMMON-2C
I SIGLO l2c
(1\Tote that every time that OUTPUT OFF is selected, REF and
SIG

when OUTPlTf ON- is next selected~ Iref2 remai,,_s at zero so the

lP,Ertcrll Ct2,
21, REF SW1TCH is fue input to the squarer.

a hard zero to the .squarero s1.ib'cractio:n current 1Ile new Iref2 is somced fron1 Com.rnon-2
[t REF II\JTECiRATE reraains closed~ and
JJileg1:mc1r to settle.
Co R~/IS Lo remain.s connected to Cornrr1on-2C until the

rernai.ns iI1 its integrnting condition 9.11, the closure pattern is repeated for
during C4, to ensure that any energy stored in the squarer SIG ;:,y,umrn1.;, witp,:nehnm and smnpling. The SIG circuit action
during CI to C3 is CNmirorl
DC subtraction during ge11er,are lli1 error~ as full @. the squarer is now the serrsed sinewave.
subtraction was period Cl. llll, the subtraction current has been set to a new value durmg
DC SUBTRACT is therefore turned off by trnnsferri.r1g the C5. does not change aga.in until period C5 offue
source of Iref2 from the summix1g junction to Common-2. next cycle.
«:. period C0, the 'AC ERROR' output from the SIG
JP'e)('i_m:il C5 srunple-and-hold follower is chsmged, updating the
21. RIEF Il\ITEGRATIE opens, stoppimg the integrator action. VCA gain via the Error Buffer and Error Amplifier.
I:;. Si-\lv'IPLIE closure forces the squarer output to a hard zero, to d, RMS Lo was switched from Common-2C to SIG Lo durmg
nullify any leakage effects in the integrator switch. period C5 in preparation for SIG squaring. It remains
c. RIEF SAMPLE doses, and current from the mtegrator op- connected to SIG Lo during the squaring periods C6, C7 and
amp charges the sampling capacitor 1:o the mtegrator capacitor C8, and also during period C9 for the Sig futegrator settling.
voltage. At Period C0 it is reconnected to Common-2C in preparation
[l!. RMS Lo is switched from the RefCommon-2C to the Sense for REF squirrmg.
SIG Lo m preparation for SIG squarmg.

9-21
 COMPAl'stlffill'l CYCLING PEfliO!:l C1 C2 C3 C4 C!i C@ c, CIEJ C® C®J C1

®1'.PM8: 4,(i)m.,

Ou.f:lsY-li.im~w~ (OO-l'C-00
~I 500Ha ©toi[OY!: ~4rns 9',j

(al S~ua-relf ilf'l(?.H.!li

A<>I/Sig

I 254.)Hz

(jl Soo,~

FIG. 9. 112 SINE/QUASl SINE COMPARATOR SEQUENCE TIMING

0 O

9-22
9.9.3.2 Comparator Action 9Jt4 COMPARATOR CONTROL
The sequence described in 9.9.3.1 is necessarily simplified. LOGIC
':'hen a new output demand changes the amplitude of Lhe quasi- (Circuit Diagram.400844 page 11.7-3)
smewave, a few sequence cycles are required to stabilize the
The Compmamr operating cycle originates atM 15, which is a 1O-
conditions of the Ref integrator, Sig Lntegrator, subtraction
bit sequencing counter, clocked at the quasi-sinewave frequency
current and AC ERROR output. The circuit must also respond 1:o
by the carry-out from M 11-12.
demands for reduced output in addition to those for increases.
The SYNC 0 input to Ml5 RESET is a decoded address, whose
Th~ comparator forms part of the output amplitude control loop,
functionatlogic-1 is todisablecountersMl 1 ondM15, inhibiting
ultrmately affecting tl1e output voltage and hence the sensed
operationoflhecomparatorandgenerationofthequasi-sinewave.
voltage input to the squarer as 'SIG'. As the sequence recycles,
In this instrument, SYNC 0 is held permanently at logic-0,
the mean-square value of the SIG input sinewave will approach
enabling bot_h quasi-sinewave and comparator for AC Voltage
that of the REF quasi-sinew ave, and as it does so the AC ERROR
and Current functions.
output must approach a steady-state value.
The clock continuously recycles M15 in ascending count through
The squarer output current has an AC component in its waveform,
~ to Q9 , ten clocks (ie ten quasi-sinewave periods) constituting
but Iref'2 being sub!:racted at the summing junction is a DC
one cycle of the comparator sequence. Only one 'Q' output is at
current. In the settled condition, Iref'2 is driven on successive
logic-1 (+8V) at a time, the remainder being at logic-0 (-8V).
cycles to balance the quasi-sinewave REP AC current (being
applied to its integrator) about zero. The fmal level ofiref2 is just With increase of frequency range, the difference between the
sufficient to be self-sustaining. frequencies of sensed sinewave and reference quasi-sinewave
increases in-decade steps.- AE the comparison: is performed ar -
Meanwhile, the sensed SIG2 current approaches the REP value,
mean-square levels, this frequency difference does not matter, so
and the same Irefl is a DC analog of the quasi-sinewave mean-
long as the sinew ave is at an exact multiple of the quasi-sinew ave
square voltage. In the output loop, the VCA is driven until !he
frequency. However, to optimize the operation of the Sense/
instrument output (and sensed SIG input) is at the correct level
Reference comparator, !he zero crossings of the quasi-sinewave
just to generate a self-sustaining 'AC ERROR'.
are synchronized to occur coincident wi!h a sinewave zero
In !he comparator, Iref2 is subtracted from both SIG2 and REP crossing, and all comparator state changes are also synchronized
currents. This mainto.ins the AC AMPL ERROR as an analoo of to sinewave zero-crossings.
the difference between the quasi-sinew ave and theoutputsinew:ve
Synchronization is achieved by clocking Ml7 so that all the
mean-square voltages (when the latter is reduced by sense
analog switching data changes simultaneously. Thus data is
conditioning to 1V Range levels). Thus when the sensed SIG
latched from Ml 7 'D' inputs to its permanently-enabled outputs,
input voltage approaches thequasi-sinewave REF voltage (mean-
one complete quasi-sinew ave period after it was clocked through
square values), the AC ERROR approaches stability and the
M15. This ensures that the transit times ofM15, M18 andM20
system settles.
do not affect synchronism wi!h the quasi-sinew ave zero-crossing.
A further complication: a bias is applied to the squaring circuit to
The data is thus stmbed through Ml5 and Ml 7, being delayed by
avoid distortion by maintaining permanent conduction. The bias
one clock period. This does not affect the operation of the
is controlled by the value of the positive reference voltage, and a
comparator, although it must be accounted for when observing
bias current is superimposed on the subtraction cu_rrent. These
waveforms on an oscilloscope.
factors will be discussed later during the circuit malysis.
The sequence, as described earlier in sub-section 9.93, begins
with REF SV\llTCH connecting the quasi-sinew ave to the squarer
input during period CL The logical origin of the comparator
switch state during Cl corresponds to Ml5-2 (Ql output) at
lo gic-1; but because of the data delay its actual timing is coincident
with the Q2 output of M 15-4 at logic-1.

9-23
 (Fig. 9.13)
The comparator timing waveforms for the sequence 1rre illustrated Sw!H~~i[FrJQJ
in Fig. 9.13. Tohighlightthedatadelay, the main waveforms are H>rnwfn,w.~ (f) and (h)]
grouped into two blocks: 'REF and 'SIG', each headed by the
At a.11.y instant, the comparator is either sampling or integrating.
states of the comparator cycle. Line shows which ofM15 (Q)
Thell\IT wave form is thus the inv erne of the SAMPLE waveform.
outputs is at logic-1 during each of the states. It ca_n be seen that
the effects of M15 output states Bie delayed by 1 clock period, in §AMIP'LJE
the trm1.slation to compani.tor states. M15 outputs andQ5 are 'OR' gated atM18-9 a.,d applied as
D3 input· to M 17. The result is to generate the SAivIPLE
Cf(;l)mmyir!$ lR,,,,,.,,,,.,,,"' wm;pf~Wm ( h) at l\JH 7-10.
['REF' and 'SlG'waveforms (d) and (k)] Therefore, for C0 and CS only, SAMPLE provides two enabling
Waveform(c)showsthevariationofM15-12(Cout). Waveforms inputs to AND gates M13 at M13-2 and M13-5. It also places a
( d) and ( k) are the direct results of Cout inputs to Ml 7 after the hard zero on the squarer output by M7-5 (page 11.7-4) when this
translation by one clock shift (note the inversion at M20-10). is disconnected from both integrator inputs. With both input and
output at zero volts, any offsei.s are removed in preparation forthe
During states C0 to C4, waveform (d) at logic-I connects the subsequent squaring and integration sequence.
squarer common (RMS Lo) to Common-2 at Ml6-4 for quasi-
sinewave squari..,g; whereas during states C5 to C9, waveform( k) JrNT
connects RMS Lo to SIG Lo at Ml6-8 for seru;ed sinewave The 'SAMPLE' output of M18-9 is inverted at M20-4, applying
squaring. Ln both cases, the appropriate common is connected logic-1 to the Dl input of Ml 7 for the whole of the cycle except
one period ahead of the squarer input, and disconnected at the end for C0 and CS. The U\IT output at M 17-5 is waveform(!), which
of the integrator settling time. enables Ml3-1 and M13-13.
REJF][N1'
Il\ITis 'J\J\TD-gated'with.REFwaveform( d) atM13-l l to generate
['REF SW' and 'SlGS'W' wa:vefonns (e) o.nd (l)J t_h.e 'REFII\IT' waveform (g), which is at logic-1 only during
periods Cl to C4. During this timeM7-12(page 11.7-4) atlogic-
Ml5 outputs Ql to Q3 are 'OR' gatedatM18-6 and applied as D2
1 connects the squarer output to the REF Integrator input.
inputto M 17. The result is to generate the REF SW wave/orm ( e)
atM17-7. §llG IN1!'
INTis 'AND-gated' with SIGwa:vejorm(k) atM13-l Oto generate
REF SVv connects the quasi-sinew ave as input to the squarer by
the 'SIG .!NT' waveform (m), which is at logic-1 only during
Ml6-13 only dming states Cl to C3.
periods C6 to C9. During this time M7-6 (page 11.7-4) at logic-
Similarly, SIG SW waveform (1), logically derived from M15 1 connects the squarer output to the SIG Integrator input.
outputs Q6 to Q8, is at logic-1 only during states C6 to C8,
REIF' §AM
inputting the sensed sinew ave as input to the squarer by M 16-12.
'SAJ\1IPLJE' is 'AND-gated' with SIG waveform (k) at Ml3-4 to
generate the 'REF SAM' waveform (j), which is at logic-1 only
during state C5. During this time driver M6-l at logic-1 causes
FET Q2 to conduct (page 11. 7-4 ), connecting the REF Integrator
output to the REF S:imple-and-Hold input.
§l!G SAM
'SAJ\1PLJE' is' with REF waveform ( d) at Ml3-3 to
generate the 'SIG SAM' waveform (n) which is at logic-1 only
during state C0. During this time driver M6-7 at logic l causes
FET Q3 w conduct (page 11 .7-4 ), connecting the SIG Integrator
output to the SIG Sample-a.nd-Hold input.

9-24
9.9.5.4 DC Subtr~ctlolril
['DC SUBTRACT OFF waveform (p)]
Subtraction is required only when either input is being applied to Sqiiillairew fop1!l!tt Slht!JJ1rt
the squarer. A--2, REF SW and SIG SW already exist, it remains When at logic-1 during C4-C5 and C9-C0, M7-13 places a hard
only to provide an OR function to join them. The analog circuits short between RMS Hi a_r1d RMS Lo; otherwise the short is
need an inverted waveform, so aN AND gate is used. For loading released.
purposes two elements of M20 are connected in parallel: REF
§uMJract!«:m C1!l!nent Cm11trnR
SW and SIG SW are combined as wavef"Orm (p) at M20-3 and During Cl to C3 and C6 to C8, DC SUBTRACT OFF at logic-
M20-ll. 0 cuts off D8 (page allowing Q6 to draw subtraction
current through D6, D5 and R54. When at logic-1, D8 conducts
and sets D5 and D6 in reverse bias, diverting the subtraction
current.

lal 1'1111-12 1\1115/1\1117 Clocks

{bf M15 output at logic-1 00 r o, 02 03 04 05 06 07 08 I 09 Of!i 01

lei M15-12 (Cou!I

Coo1s,,,,a<w l'lll:f CW©!@ C9 C/11 C1 C2 C3 C4 C5 C6 Cl CS C9 C(J]

ldl ~ REF Squarer Common = COMMON 2:C

le) 1\1117-7 (02) ~ Quasi-sine input to Squarer

Iii 1\1117-51011 ~ !NT INT IIIIT

lg) M13-11 REF INT

Ouasi-sine isqu21red} being integrated

lhl M17-10 1031 ~ ~ ~ ' - - - - - - - - - - - - - - - ' Squeirsr ' - - - - - - - - - - - - - - - - ' ~

0/P Zero 0/P Zero 0/P Zero

111 1\1113-4 REF SAM _ _ _ _ ___,j REF lnt.

_ _ _ _ _R_E_F_s_am_p_l•_-_an_d_-h_o_ld_in_p_u,_i_so_le_,oo l____R_E_F_••_m_p_le_-a_nd_-_ho_ld_i_np_u_,_is_ol_a,_ed_ __ I
00:ing sampled

c~rn~~@1 ~ c~ C9 C/11 Cl C2 C3 C4 C5 C6 Cl CB C9 Clli

11<1 l\/l17-12 (041 SIG Squarer Common = SIG lo

(I)
~ ~ 1 Sinewave input to squarer L ______
(I)
~ !!:!I IIIIT !NT INT

1ml M13-10 SIG !NT

Sinewarve (squ®red) Wing integreitOO

(hi
~ ~ Squarer ._I_ _ _ _ _ _ _ _ _ _ _ _ .....J Squarer ._I_ _ _ _ _ _ _ _ _ ~
0/P Zero 0/P Zero 0/P Zero
I
lnl M13-3 SIG SAM _ _ _ _ _ _ _S_IG_sa_m_;_p_le_-o_nd_-_ho_ld_in'-pu_t_is_ol_at_ed_~--------------------~
being sampled

Subtraction applied
(pi M20-3 OC SUBTRACT OFF j Squarer 1/P Zero Squarer 1/P Zero
Subtraction applied
Squarer 1/P Zero L

9-25
The basic action of t_h_e squaring circuitry is the same as is used Differential input v&riations betvveen the collectors of Ql 10
for sin2 and cos 2 ii, the Sinewave Oscillator amplitude but and due to 'SIG2" and 'REP' outputs from the Square
there are some differences h"l detail to sub-section 8 .2). Detector are translated to ended currents into mid out
'I11e current difference passes through
The Square detector is biassed h1 such a way that it is permai,ently
S:IG J!NT states, and to R149 durillg
lumed on, to improve bandwidth and permit control of gain
REF ThIT states,
scaling. Its differential outputvoltage at Ql09 andQl 10 collectors
is proportional to the squllre of its hrput voltage, divided by the At other times, when both of the integrator input switches
bias voltage. The bias is derived from the DC version of t.lie M7-8/9 and M7-ll/10 file open, the 'SA.MPLE' waveform
demanded signal level REF+ve, tl1e DC output from the reference closes M7-4J3 to pass any difference current to Common-2C.
divider, (During the SAMPLE periods, DC SUBTRACT OFF is
zeroillg the Square Detector illput RTvl[S Hi anyway, by
Thus the tra._nsfer proportionality of the signal magnitude is given
shorting to RMS Lo via M7 -2/1 - page 11,74,)
by:
Vout is proportional to Vill2 i Vbias Resistors Rl18, Rl48 and Rl49 are of very low value
compared with ilie output impedance at 1'P9, so the driver
but as Vbias is derived from REF+ve,
compliance is high,
Vill / Vbias is a constant: k,
ond the illstantaneous squarer gam is:

k V° 2
d( __1::_) On ilie lOOHz Frequency range the gain around the output
d(Vout) Vill amplitude loop needs to be less than on other ranges. This
2k
d(Vin) d(Vin) compensate for the longer integration times at lower
frequencies.
Thus the basic gain equation has no a._rnplitude or frequency
Adjustment is in two stages, using dual open-collector
components, so is constant over a wide ba_ndwidth and dynamic
comparator Ml05:
ra._nge, The squarer therefore has a fast response at all signal
levels. a, JF([)Jr 10ij!f-fa: §eRe.::Hmn
The 'lOOHz' logic signal illput to M105-2 is derived ii, the
The bias is applied as currents to and Ql 17 emitter circuit<;,
frequency systhesizer ruid is at logic-1 when lOOHz
The transistors ill the array of M22 are all used as current
range is selected. M105-l is pulled up by Rl 15 andQ108
generators.
conducts cormecting Rll6 across Rl13, reducing the
gain of the Ml03 voltage to current converter,
liJ, JFrnr freqp!!el!Jlcy selled!([l)l!Jl§ ilJJeli([j)W 31.Hz
The illput to Reference Amplifier M24 is the pos1uve DC The '>31Hz' signal illput to M21 is also generated ill the
REF +ve voltage, which varies belween approximately 0.14V Synthesizer,
and 2,8V, dependillg on the output value selection.
Similar comparator action provides further loop gaill
M24 output voltage rises until M22-9 pulls enough current reduction for frequencies of3 l Hz and below, Both Q 107
through R50 to reduce M24-3 to zero. The other transistors ill andQ108 are on to switchinbothR116 andR116 across
M22 act as current mirrors, so their collector currents are defined Rll3,
by the REF +ve voltage a..nd the resistance of R50.
Thus bias current is applied to Q 116 lli°'ld Q117 in direct proportion
to the REF +ve voltage, which is an accurate analog of the
demanded output value,

The 'SIG2' and 'REF' current outputs from the square detector
develop a differential voltage input between the collectors of
Q109 and QllO, to the current driver M103. This amplifier
generates a single-ended current drive to the illtegrators.
Ml03-7 drives current out through Rll3 and Rll8 to the
illtegrators while Ml 03-1 cupplies voltage feedback to maintain
TP9 node at very near common 2 potential while maintaining
high output impedance to the integrators.

9-26
9.9.7 GENERATION OF THE DC SUBTRACTION CURRENT

9.9.7.1 'REF' Integration 9.9.7.3 'REF' V to I Converter

The integrator circuit is very basic. Feedback for M 12 is by C25, ThecircuitofM19 andQ6 converts the DCvoltageoutputofM4
but the input resistance is formed by R149, R35 and the output into the subtraction current. A second function is to draw an extra
impedance of the Current Driver, which is heavily predominant. DC current which compensates for the bias control currents.
The current from the driver is virtually unaffected by R35 and
The DC 'REF ERROR' voltage from M4-6 is divided by R37/
Rl49.
R31 and applied to the non-inverting input of Ml 9. A second
M7 -11/10 conducts for periods Cl to C4 (REF INT). During Cl input results from the DC bias current drawn by M22-l 4, defined
to C3 the REF SW waveform inputs the quasi-sinewave to the by the 'REF+ve' voltage and the two resistors AN2-10/7 and
squarer, and during C4 the squarer settles to its zero input. Rl41.
The REP output from the driver is an AC current, which for a Ml9 drives FETQ6, which draws currentviaQl lOemitter, R54,
constantquasi-sinewave amplitude is integrally charge-balanced D5 and D6. The current is sunk into Common-2C via R47, R38
about zero due to the DC subtraction, at twice the quasi-sinew ave and AN2-12/5, and into the-15V supply via the M22-14/12 bias
frequency. C25 therefore receives equal positive and negative circuit.
charge during each cycle of quasi-sinew ave, so the mean voltage
Capacitor C34 filters out any HF transients remaining from the
at M 12-1 does not change.
switching edges of REF SAMPLE, and D7 protects against
AdischargepathforC25 isprovidedbyQ5/R30. The'INT HOLD' positive excursions of Q6 gate.
signalatJ7-46islogic-l whentheinstrumentisin 'OUTPUT OFF'
In the simplified diagram of Fig. 9.10, the subtraction current is
condition, discharging both REF andSIG integrators. For so long
shown as being sourced by the summing junction. In reality, it
as the output remains 'ON', the INT HOLD signal stays at logic-
is taken from Ql 10 emitter for three main reasons:
0, and the integrators are never discharged other than by the
action of their inputs. 21. The Current Driver input bias is removed, allowing a zero-
offset reference.
9.9.7.2 'REF' SamplEM'.md-Hold II:!. The control bias for the squarer is compensated at the earliest
Q2 conducts during each 'REF SAM' period, when the charge on opportunity, reducing the required dynamic range of the
C25 has settled for the cycle. Ml2 drives Cl2 to the voltage on driver.
C25, and the voltage follower M4 passes the same voltage as c. QllOemittervoltageremainsvirtuallyconstantforallsquarer
'REF ERROR' on to the REF V to I Converter. inputs.
Q2, Cl2 andM4 are low-leakage devices and M4 input circuit is Relocating the subtraction point does not affect the essential
screened, at low impedance, to the sampled voltage. Thus the action of the square detector and driver, because of the current-
'Droop' is specified as less than 20µ V during the 'Hold' part of the mirror action of the driver.
cycle when Q2 is not conducting.
Subtraction is valid only during times when a quasi-sinew ave or
sensed sinew ave is being input to the Square Detector. Thus for
periods Cl to C3 and C6 to C8, diode D8 is held in reverse bias
by the signal 'DC SUBTRACT OFF' at logic-0. During periods
C4, CS, C9 and C0, the signal is at logic-1, so D8 conducts and
reverse-biases D5 and D6. The subtraction current passed by Q6
is then diverted through D8 from M20-l l/3, the
'DC SUBTRACT OFF'parallelNORgates'outputbeingatlogic-
1 (page 11.7-3 ).
When an operator selects a different output value, the result is a
change in amplitude of the quasi-sinew ave. This unbalances the
integrator input, so C25 charges to a different mean voltage at the
output of M 12. The DC subtraction current change takes place
over a few comparator cycles until balance is restored, when C25
and Cl2 will have charged to a new voltage.

9-27
9.9.8 'AC ERROR' SIGNAL GENERATION

9.9.8.1 Integration and Sampling Circuit The (quasi-sinewave)2 current is integrated across C25, resulting
in a positive 'REF ERROR' voltage after period CS, and hence a
The SIGNAL Integration and Sample-and-Hold circuitry is positive subtraction current in R35. The effect of the current can
identical to the REF arrangement described in Section 9.9.7.
be seen in the TP9 voltage waveform: an increase of (quasi-
Moreover, the SIGNAL Integrator M12 is the other half of a
sinewave)2 amplitude is accompanied by a positive shift as its
matched pair with the REF Integrator.
mean value seeks coincidence with zero.
The difference lies in the ti.ming. Switch M7-6 allows current to
After a few comparator cycles the current in R35 becomes
pass into the SIG integrator only during periods C6 to C9, so it is
charge-balanced about zero, the DC subtraction current stabilizing
the SIGNAL (sensed sinewave)2 current minus the (DC REF)2
to a steady-state value.
subtraction current which is integrated.
Meanwhile, during the 'SIG' sections of the comparator cycle, the
The integrator voltage is sampled andoutputas the 'AC ERROR'
positive subtraction current is integrated across C26. A negative
DC voltage (subasections 9 .2 .4 and 9 .9 .2 ), into the output
'AC ERROR'voltageis generated, which increases the instrument
amplitude control loop.
output voltage via the VCA. This increase is detected by the
sense feedback circuits. After squaring, the result is an AC
9.9.8.2 Output Amplitude Loop Action current in R35, whose mean level begins to offset the effect of the
Consider the case of 'OUTPUT OFF' subtraction current on the SIG integrator.

a. The quasi-sinewave has an amplitude detem1ined by the After a few comparator cycles, the AC SIG2 mean current and the
'OUTPUT' display value: DC subtraction current are equal and opposite, so the current fed
through R35 into the integrator is charge-balanced about zero.
b. The quasi-sinewave is squared and appears as a current in The integrator capacitor C26 is thus being charged and discharged
R35 during periods C l-C4, but because Q5 is conducting, the by the same amount during each half-cycle of output (SIG2
REF integrator capacitor C25 is discharged. Thus the DC current being at twice the output frequency), so the AC ERROR
subtraction current is effectively zero (it is actually sufficient voltage stabilizes.
to cancel the DC current in R35 due to the squarer bias).
Fig. 9.14 illustrates three stages in the process of increasing
c. The AC ERROR signal voltage is zero, as Q4 conduction output from zero; observing the current in R35 (ie. the voltage at
prevents any charge on the SIG integrator capacitor C26. TP9), the 'AC ERROR' signal, and the output sinewave. The
Also, the output amplitude is zero, hence the sensed output waveforms are not to scale.
applied to the squarer is zero.
Stage 1.
Therefore during periods C6-C9 the current in R35 is zero. This is the first cycle that the quasi-sinew ave starts to charge C25.
Now consider the case when OUTPUT is switched ON, with the During period C6 anon-zero subtraction current is applied to the
OUTPUT display set to the minimum value of 9% of range: SIG integrator, resulting in a non-zero value of 'AC ERROR',
starting at C0 as the integrator voltage is sampled. This causes
As the quasi-sinewave is already present, it is squared into a
the instrument sinewave output to rise from zero.
negative-going waveform in R35.
Stage 2.
On the next cycle the subtraction current imposes a positive shift
Quasi-Sinewave Input on the R35 waveform during Cl-C3 and C6-C8. The squared
quasi-sinewave does nOl change in amplitude, but it is more
equally balanced about zero, so the next increase in subtraction
current will not be so great.
During C6-C8 the sinew ave is being applied to the squarer, so
TP9 exhibits its squared waveform shifted positively by the
During the first comparator cycle, this appears as a voltage at TP9 subtraction current. A smaller increase in 'AC ERROR' and
thus: output sinew ave results, as the AC input to the SIG integrator is
more equally balanced about zero.
(Quasi-Sinewave)2

Zero Reference . . WM. . Stage 3.

In this state the loop has stabilized. The squared quasi-sinewave
and sensed sinewave are both charge-balanced about zero, the
subtraction current and 'AC ERROR' have reached constant
values, and the instrument output is stable.
The standing bias on the Ref. V to I Converter has inlmediately
set the (quasi-sinewave)2 to an approximate zero mean.

9-28
9.9.8.3 'AC ERROR' V-tc.>nl Converter
(Circuit Diagra,,'! 400844 page 11.7-6)
To avoid noise pick-up, the AC ERR OR voltage is converted into The current in ANl -4/13 is mirrored by the current in ANl -11/
a current, for transmission to the Error Amplifier on the Sine- 6 (AC AMPL ERROR), which is sourced in the Sine-Source
Source Assembly. One half of M3 is used as a unity-gain Assembly by M4la, the Error Amplifi.er(CircuitDiagram430446
inverting buffer, and the other as a voltage-to-current converter. page 11.6-3).
The relay RLl is not fitted, so M3-7 is linked directly to the test
As the AC ERRORsignalDCvoltageisvariedbythecomparator,
switch Sl 'NORM' terminal.
the current in M4 la input resistance also varies, and is converted
At M3-7 the DC 'AC ERROR' voltage is inverted and used to into a varying voltage at M41a-1. This voltage is used to control
drive the current converter via ANl-3/12. the main voltage-controlled amplifier M48 via Q71.
For further information about the VCA, refer to Section 9.3.

I co Cl I C2 CJ I C4 C5 I C6 I C7 CB C9 co
Stage 1 F,rst Cycle

TP9
ov

AC El'IFIOR

ov

OUTPUT

-------------~

TP!il.
01/

0\/

OUTPUT:

TP9:

0\/ - - - - - ~ ·--·-··---------

AC ERROR:

0\/
Stable Value

OUTPUT:

FIG. 9.14 THREE STAGES OF OUTPUT BUILD-UP FROM ZERO

9-29
9.10 LOGIC CONTROL OF AC OUTPUTS
The general aspects of analog control functions are discussed 9.10.2 PA ASSEMBLY~ LOGIC AND
earlier in sub-section 7.10, subdivided as follows:
RELAY DRIVES
7.l(J.1 Logic Levels (Circuit Diagram 430618 Page 11.9-5)
7.10.2 Heat Reducti<m The extensive switching needed to control the many modes of
7.10.2.1 Update Considerations operation of the Power Amplifier assembly, is described earlier
The AC signals are routed through the DC assembly on their way in Section 7.12. The subjects are subdivided as listed below:
to the terminals and back; for the lOV, lOOV and 1000V ranges U2.1 DC Range Switching
they are amplified in the Power Amplifier assembly. The signals 7.122 AC Range Switching
are subject to digital controls incorporated in those assemblies. 7.12.3 Function and Ranging Logic
Descriptions of the controls in the DC and PA assemblies are 7.12.4 'PA CLAMP ON' Signal
indexed in sub-sections 9.10.1 and 9.10.2, below. 7.12.5 '400V ENABLE' Logic
7.12.6 'BIAS OFF' Logic

9.10.1 DC ASSEMBLY - LOGIC AND 7.12.7 'UM ST 'Logic

7.12.7.1 'LIM Dl!I''
RELAY DRIVES
7.12.7.2 'LIM ST' Generation
(Circuit Diagram 430536 Page 115-3)
7.12.7 3 CPU Response
The AC voltage output and sense signals pass through the DC
assembly, and are affected by the analog control signals present 7.12.8 'LF', 'LF·, and 'lkV GAIN'
there. 7.12.9 Thermistor Comparator

The effects of the control logic on the DC assembly are detailed

in Section 7, subdivided as indexed, except for the 'HIGH I
LIMIT' and 'AC lkV RANGE' Logic.
As these two signals are activated only on the AC lkV Range,
their effects are described in sub-section 9.7.6 (but reference is
also made to relays 12 and 13 in para 9 .4 .2 .3 ).
7.11.1 ln.trod1u:tion
7.11.1.1 Latched Bistable Relays
7.11.1.2 Tristate' Relay Drivers
7.11.2 Clamp Assembly
7.11.2.1 UPD(lG) Distribution
7.11.2.2 Buffer Clamping
7.11.3 DC Assembly Switching Logic
7.113 .1 DC Range Switching Logic
7.113 .2 Function and Output Switching Logic
9.10.3 AC ASSEMBLY LOGIC AND RElA Y DRIVES
(Circuit Diagrams 400844 Page 11.7-5) holding M25-l l 'D' input at logic-0, and energizing relays RL2
and RLlO. This connects the star-point at Common-2B to the
The analog control signals are transferred into guard on the
PLO(ACV) line (J7-31) andSIG LO to theSLO(ACV) line (17-
Reference Divider assembly, and latched as 'Q' outputs in the
32) (page 110 7-1 ). The bit-patterns controlling the voltage range
Serial/Parallel Data Converter. Offset positive logic is used:
switching are shown on Table 9 .1.
logic-0 = -15V, logic-1 = OV. I FNCT is at logic-0 only when Cu_rrent output is selected,
holding M25-l l 'D' input at logic-0, and energizing relays RL2
The signals enter the AC assembly via J7 from the Mother iindRL9. This connects theACI REF lines (J7-69 to J7-72)to the
assembly. ACV lines (page 11.7-1 ). The lOV range output is used as
reference for the 1OOmA, 1OmA and lmA Current ranges, but the
1V range output is used for the lOOµA and lA ranges. The bit-
M28 and M29 are inverting, open-collector Darlington drivers. patterns controlling the current range switching are also shown
The relay-drive logic places a logic-1 (OV) on the input of the on Table 9.1.
selected drivers ruid logic-0 (-15V) on those not required. A
selected driver operates its relay by pulling its output to -14V. TI1e signals AC FNCT and I FNCT are never at logic-0 at the
same time in normal operation. The only time they are at logic-
Whenever a switching command has been received, the CPU 1 together is when all outputs from the Control Data latches in the
performs a control-data transfer and the UPD(IG) line from J7- Reference Divider are Tristated'. 'DCI' ensures that RL2 and
53 is pulsed to logic-0 for 50ms. is turned on, applying RL9 cannot be energized selection of DC Current ranges.
+15V to the relays connected to its collector. The selected relays
are thus energized by 30V, but af1er the UPD(IG) pulse has ended
Ql9 turns off, and they are held on by the -12.6V between-l.4V
at the cathode ofD20 and -14 Vat the selected driver output. This For zero output, Lhe lines from the voltage generators to the I+ and
method reduces the heat, generated locally by energized relay I- terminals are disconnected by deselection ofthera.n.ges, and a
solenoids, in the relay contacts. hard short is placed across the omput lines by RL18.
'l,1,1 '. This setsM25-4 to logic-1 (energizing
FETs Q42 and daxnp the coils of RL12 and RL13; diodes relay amd all other M25 range outputs to logic-0 (the
D59 ai,d D60 isolate paxts of the printed circuit to these relays, resultant bit-pattern is shown in Table 9.1). Thus all ranges are
which are sensitive to power-com1non brealcthrough when they deselected, but relays RL2 (ACV and ACI), RL3 (AC Low
are deselected. D55 and D56 are overswing diodes. Voltage Output), RLlO (ACV) andRL19 (lkV)remainenergized.
Relay RL18 connects the PLO(ACV) star-point of Common-2B
si. ~ tt3J swrn«:;!1!u1Jgi to Lhe PI-ll(ACV) line.
(Page 11.7-5)
Range control data is input as a 3-bit code on ACR 1 and
ACR2 lines. The bit-pattern is decoded to 'I of M25, to The 'BARK' signal does not affect the AC assembly relays.
energize the correctrelays for the selected range. In this instrument However, if the Watchdog is activated, the CPU imposes
only eight of the M25 'Q' outputs are connected. The resulting OUTPUT OFF conditions and forces 111.e Precision DC Reference
variants are listed in Table 9.1 against range selections. to ramp down to zero, so the PHI REF voltage also falls to zero.
All outputs from the Control Data latches in the Reference
9,10,3,:2 AC fNC'f ~1'11d i fNCT lo~!«:; Divider (page 11.44) are Tristated' by the 'BARK DELAYED'
(Page 11.7-5)
signal. 'This allows the pull-up resistors (AN4 and ANS) to
In addition to its primary function of controlling AC Voltage become effective.
range switching, the AC assembly logic also needs to respond to
AC Current range selections if Option 40 is fated; because the The AC FNCT and I FNCT are pulled to logic-1, and the
AC voltage reference for the Current assembly is generated by AC~_0 codeis '1,1,l'. This imposes 'AC Zero' conditions on the
analog circuit, but RL2, RL9 and RLl Oare also de-energized. So
the Voltage circuitry. For this purpose the two signals AC FNCT
the DC precision reference is disconnected from the input to the
and I FNCT are used. quasi-sinewave generator; the ACI(REF) is disconnected from
AC FNCT is atlogic-0 only when AC Voltageoutputisselected, the input to the AC Current circuitry, and the Sense and Power Lo
lines are disconnected from the sense amplifiers.

9-31
Function Range Range Code M25 Output Relays Energized [° = Energlled]
at Log,c-1

N01e :1, ACR 2 0

ACR 2 ACR, ACR 0 ·o· Pin 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

AC
Valls
1000V 0 0 0 00 3 . 0

100V 0 0 1 01 14 . . . 0

IAC FNCT
at
10V 0 1 0 02 2 . . . 0

Log,c-0.
1V 0 1 1 03 15 0 . .
IFNCT 100rnV 1 0 0 04 1 . . 0

. .
at
Log,c-11 10mV 1 0 1 05 6 . 0
!

1mV 1 1 0 06 7 . . . .

Anv 1 1 1 07 4 0 . 0

AC
Current 100~A} 0 1 1 1)3 15 0 0 0 . 0
0

lA

~
at
Logic-1,

iJ!'NC'F
at
1mA
10mA
100mA
} 0 1 0 02 2 . . . . ' .
Logic-en

Note[1] in normal operation,unleu lhe SAFEt'\f

message is displayed; 11ither
but not both, will be 1111 logic-0.

SWITCHING LOGIC
SECTION 10 CURRENT OUTPUTS AND RESISTANCE
1 DC AND AC CURRENT
The circuits described in this sub-section perform the following CURRENT GENERATOR
functions:
(Circuit Diagrams 430614 Page 11.8-1 and
Divide the DC reference voltage by 10 to (-2V to +2V)o 430540 Page 1U3-3)
Generate a DC output current whose value varies directly as Because a return path is needed for the output current, a
the reduced value of the DC reference Voltage" 'compliance' signal voltage appears between the I+ and I- terminals"
Convert the ACI Reference Voltage into a_n AC reference The magnitude of this voltage is specified in the User's Handbook,
current, having a high-impedance source" and the specification is met by floating the input to Lhe output
Generate an output current whose value varies directly as th.e amplifier.
value of the AC reference current.
Provide switchii,g of the DC or AC Current Range and On the DC ranges the floating DC reference is input directly into
Output, under the control of the Analog Control Interface" the output amplifier, which therefore acts as a voltage to current
Sense excess output (compliance) voltage, providing a status converter in thestyleofFig.10.l" Resistors R44andR45provide
signal to the CPU via the Analog Control Interface" 10: 1 attenuation, to set the 'VRef to 1/10 of the reference value.

The voltage-to-current converter is located on the Current or For AC ranges the ACI Reference is buffered from the output
Current/Ohms assembly, providing five DC and five AC ranges amplifier in a two-stage circuit. A fixed voltage-to-current
of cunent output. The full range values are lA, lOOmA, lOmA, conversion stage is followed by a rnnge-switchable current
lmAand lOO~LA, extending to 100% ovemmge, for both DC and amplifier (lhe latter is the voltage-to-cunent converti;[ for DC
AC Cuffcnt The output is drawn from the instmment I+ and!- ranges). The combination is simplified at Figo 10.20
terminals; the Hi and Lo terminals not being used. In the figure, the AC Reference voltage is applied via two
resistors Rl andR3 to bolh inputs of the first stage" Itis arranged
for the resistor values to conform to:
R2 R4
RT = Jln·
Fig. 10.1 shows the basic arrangement. A DC or AC reference
so the output impedance of the stage is virtually infinite, and its
voltage is developed across Rl between the output and the
output 'floats'"
inverting input of the high-gain amplifieL Its output connects to
its other input by a 'shunt' network, part of which canies the The second stage is a current amplifier, receiving the output
output current. CTu"'Tent of the fixed stage to generate a voltage across R5" This
voltage is repeated across R6, whose value is ran.ge-switched"
The combined feedback forces the differential input to zero" Th.Ls
Any resistor Rs does not affect the output, carrying no currc:nL
adjusts the current in the positive feedback path until the full
The current amplifier supplies are bootstrapped to improve
value of the reference develops across !he path" For example in
common mode :rejection"
Fig lO.l no current flows inR2, so allofVRefis develops across
0

Rs" The values of VRef and 'shunt' Rs determine the current

flowing in the external circuit. Rs is switched to select the range,
ai,d VRef is varied to set the output current within the range.

ACV to ACI Current

Converter Amp11f1er
V Ref ------"'>!

R1

ov

R4 R6

[ R2 = R4l _ Floating
Rl R}j output
RL

FffG. 10.1 BASIC

VOl TAGE~ TO~CURRENT CONVERTER FIG. 10.2 AC CURRENT GENERATION

10-1
10.1.3 DC AND AC REFERENCE rn 10.1.6 RANGE SELECTION
SOURCING AND SCALING Fig.10 3 shows two Range configurations of the current amplifier.
The DC output curl!"enw are bipollll[, directly controlled within In each case V Ref is 10% of the reference voltage. The polarity
each range by the ±20V reference voltage (REF) from the of the solenoid current of bistable latching relay RLl determines
Reference Divider. On DC ranges, REF is divided by 10 in the which state is selected. Solenoid current is not required for hold-
input attenuator, For the lmA,lOmA and lOOmA ranges, the on, only to change state.
±2V full scale span is available across the selected range shunt. The voltage across the I+ and I- terminals is fully compliant up
To optimize component choice and minimize the relay oount, to 3V DC or RMS. Each range has resistance in series with the
software further divides the DC reference by 10 for the other two I+ terminal to enhance si:abilicy for reactive loads.
ranges. On the lA Range a full scale span of±200mV can be
applied across its O.lQ shunt, and for the lOOµA Range the 1O:i.6.1 1 A Range
±200mV can be applied across the combined shunt resistance of (Refer to Fig.103a)
lOOOQ assigned to the lmA Range. Relay RLl closes contacts 8/9, 11/10 and opens contacts 2/3.
The AC output currents are controlled within each range by the Relays RL2, 3, 4, and 5 are not energized. The only output current
value and frequency of the ACI(REF) voltage. This reference path passes through the O.Hl shunt R80. Thus in the positive
voltage is generated by the circuitry used for AC voltage ranges: feedback path all of VRef is developed across R80, and no current
the l OV Range for the lmA, l OmA and 1OOmA ranges; but the flows inR79, R8, R9 or RIO. As V Ref is scaled to lOOmV DC
1V Range for the l OOµA and lA ranges. Thus the same shunt or RMS full Range, the full range output current in R80 is:
values and switching relays can be used for both AC and DC lOOmV/0.lQ = lA.
current output;;. The highest frequency available is SkHz.
11'.tUt~ WOmA, WmA, and 1mA R8nge~
DC CURRENT REFERENCE '(REF)' (Refer to Fig. 103b)
(Circuit Diagn:mis 430652 P@ge 11.4-3 aml Relay RU is mctivatedoo that contaci: RLl-3/2 i.s dosed, contacts
430614 Page 11.8-1) lRLl-10/11 sm.d 8/9 ll!re open. One relay from RL2, 3 and 4 is
energized by range, RL5 is aloo energized on the lOmA and
The (REF) signal is the main DC reference for the whole
1OOnlA ranges for extrm HF filtering. All currents now avoid the
insl:rument It is sourced in the Reference Divider on J4-9/10/11/
O.LQ shi.mt, p!ll.Ssmg instead through fue lOQ shunt R19. R19 is
12 (page l'IB a 4-wire output, which enters the Current/
moiiIDiled with R.80 OIDl ll. ooplllrate he11tsink assembly, plugged into
Ohms Msembly from fue Mofueir assembly on JS-1/2/3/4
the main Current or Current/Ohms 11SsemMy (refer ilo the Ll!yout
11.8-1). Relay RL7 is activated for DC Current Rmges, so the
Drawing, page 11.8-1 for alternative versions).
PID(RIEF) md PLO(REF) levels are ;;ensed m TP3 md TP4
respectively. OIDl the lOOmA range, VRef is scaled to l V DC or RMS lFull
Range, oo the full. range current flowing tlrrough R.79 to the I+
(REF) is divided by R43/R44, so 1/Hl of (REF) ill developed
termmitlviaRL3-14/8is: lV/mg = lOOmA.
across R.43, sm.d applied between fue inverting input of the V -I
converter im.d the output of the Dm-lingtons on the J?S/_[ heat;;ink For the 1OJmA irmge, R8 '°'"''"'"''"" i.s included in fue current path,
at H9-7 (one of fue refay oontactli\ RLl-2/3 or RU-Hl/U is so the fuU rnnge output current is reduced to ll OmA. 900.00
always made). is added on the lmA range.

1tt 1 ,6,3 1OOµA Range

CURRENT REFERENCE (Refer to Fig.103b)
'PHI (ACI REF) 0
The hMdwm-e is switched ru, for the lmA nm.ge, bull either the DC
(Cilfcuit Diagrams 400844 P@ge 11.7-1.and
REF voltage is scaled in softw&e ro 1V Ml. range, or the ACI
430614 Page
REF volt~e is obtained, as for the lA nm.ge, from the AC lV
On the and 1A 1rnnges, fue AC 1V Range circuit provides range crrcwtry. Thus VRef is scaled w HIOmtV DC or RMS JFuU
the 2V RMS JFuHScllllerefere:rn::e; on the lmA, lOmAimd lOOmA Range, md the full range output current is lOOµA.
rmges the AC WV Range circwt mov1oes 20V RMS mt.FuH
Scrue. ,6.4 1OA Range
On the AC &ssembly (P01ge 11.7-1), for T function, RL9 is The 1OA rmge cm be selected oruy if mModel 4600 amplifier is
energized and RLl Ois not The reference voltage for the current connected to the instrument by the digital and mal.og control
generator iE derived from the PHI (ACV) and PLO (ACV) busses. The 4600 converts an input voltage to an output current,
signals; and sensed at the input to the Current or Current/Ohms so operation of the 4808 in 1OA range is more appropriate to the
assembly. The sensed ACI REF is returned to the appropriate discussion of DC and AC Voltage ( sectioM 6.1.9 am1 7 3 .8),
connectimw on the lV/lOV Sense Amplifier. The 4-wire
connectioru; am made via J7, pins 69 to 71, to the same pins of JS
on the Current/Ohm!! ru;gffll.bly.
The AC preamplifieir MS divides the reference volt~ by 10, oo
the RMS voltmge applioo w R43 is the sm1e !IS the DC vol~ge
applied for cmresponding 1nmge md output setting:..
 I Ref 2k 2k
I Ref

,01---·-··-·-··-··· \ 1 Ref ---·--·······----o• •a---·············· V Ref ················-~D·

10 11

RL1 (1A)

I+

___n
'07

--........::":o~
RL4 (1 mA) 8200

'-------4>---4____,,14~~1
RL5 (Filter) 47pF

@" 11 GOmA jg~',,,,"''"'

!FU':L 1l!JJJo3 C/JJ!PiR!EtVliT !RANG!E COuVFDGiL.,J/Rlli. 1'DONS

The value of the. REF h,put sets t11e output current value, sco1led
for range as described earlier. REF is coupled: Hi to the 1.l.8-1 or 401008
output, and Lo (TP4) to the input R44. ,n,,urnvw430540 Page
The conversion amplifier is in r-wo sec,ions:
on the Current assembly ( page 11.8-6) m Curren1:/0hms assembly The main current amplifier and temperature-sensing driver load
(page 11.8-1), and a puwer amplifier on the PS/I Heatsink are located on the PS/I HeatsLnk assembly. The quiescent
assembly (page 11.13-3). The laner is also drawn, for convenience, ' adjustment is situated on i:he Current or Current/
on page 11 J3-.l 1.l .8-6.
The whole amplifier is al.so used as the Current Arnplifier for AC
output currents. In that case it is preceded by the AC preM1plifier
M8 (sub-section Transistor Q7, thermally attached to the heatsink and in parallel
withR26, R23 and R28 on the Current or Current/Ohms assembly,
11:t1,1JJ V@!~@Qli!! IQl!"ieMS11Rf>Fr'
acts as the load for the preamp buffer. As the heats ink temperature
M3, M4 and Q6 form a high-gain, chopper-stabilized voltage increases, Q7 conduction increases, reducing the drive to the
amplifier. M3, itself a chopper-stabilized amplifier of high gain current amplifier. This compensates for increased intrinsic
and approximately 1OHz bandwidth, tri= the input offset of Q6, quiescent current in the two Darlington output devices.
which provides i:he bandwidth necessary to pass the signal
frequencies ru1d reject common-mode noise.
M4 contributes additional gain :md drives the high-current output FET Q9 acts as constant l.4mA ballast for the 3.3V zener diode
stage via link 'fLE. Its load, consisting of R26, R23 and R28 D6, which sets the voltage across R27 to approx. 2.6V. This
shunted by Q7 in i:he Heatsink assembly, is supplied with a establishes i:he collector current in Qll, generating a constant
constant current by Q9, D6 and Ql 1. Additional frequency current in the buffer load.
compensation is provided by C43 and R3 l. The voltage across the load is supplied to the PS/I heatsink as
The supplies to Q6 and M3 are bootstrapped by M7 for common- drive for the high-current amplifier. The tapping at J8-110 sets
mode rejection, also lineari.zing the preamplifie:r's dynamic the base conduction level of Q7 on i:he heatsink, which in turn sets
response. Extensive screening and filtering is employed to the level of its collector conduction, adjustabJ.e by R23. This
elinlinate the effects of the chopping spikes at the inputs and therefore adjusts the quiescent current in the output devices Ql
output of M3. andQ2.

10-3
10.1.7.5 Power Amplifier 10.1.9 OUTPUT PROTECTION
Darlington emitter-followers Ql and Q2 form t_h.e power output Diodes D18 and D19 are 5V, 5 Watt zeners, placing an absolute
amplifier, current-limited by Q5 and Q6. The bias is set to limit on the excursions of output voltage. The output compliance
provide some lOOmA of quiescent current, which reduces the specification is valid only up to 3V DC or RMS at the output
output resistance of the stage, improving the dynamic response of terminals. Nevertheless, occasions may arise when a user
the output current. This also suppresses any tendency for the overloads the circuit by attempting to drive current into open
drive from the prea..mp buffer to fluctuate for output currents circuit (e.g. by disconnecting from a load with OUTPUT ON). lln
around zero; as the drive voltage must slew through approximately this case D18 and D19 protect any voltage-sensitive load by
1.3V after switching one device off before the other is switched limiting the output voltage to 5V. But before the voltage reaches
on. The current shunts complete the feedback andoutputcircuits, this limit, the overvoltage protection circuit generates the LIM ST
the output current being fed to the I+ terminal via protection signal.
circuitry and output switching.
1CU.9.1 Guard Buffers
10.1.8 AC VOLTAGE TO~CURRENT 0
Ml guards out theleakageofD18 andD19 in normal operation,
CONVERSION and protects against other leakage, by maintaining the output
screens and shields around the output circuitry at the output
10.1.8. u AC Voltage-to-Current Converter MS potential. In addition to its bootstrap function, M7 also acts as a
buffer for guards around the amplifier input, thus preventing any
(Circuit Diagram 430614 Pagell .8-1 or 401008
common-mode disturbances from affecting the performance of
page 11.8-6)
the main amplifier.
The reference voltage PHI(AC][ REF) is applied to the inverting
input of M8 via resistor R45, with R.46 as feedback resistor.
Similarly R47 and R48 are connected on the non-inverting side.
The 18MQ resistors R82 and R83 shunt R47 to allow compliance The output guard buffer Ml drives the overvoltage detection
adjustment by R31. R86 refers the inputto Common-Il, the maLn circuit. M15 divides the output voltage by two and acts as an
'signal' common. inverting full-wave rectifier, accommodating AC and boih
polarities of DC. The full-wave rectified voltage atM15-14 thus
increases negatively as the output voltage increases, charging
C32 to its mean value at Ml5-10. Ml5-9 is biassed to -2.2V, so
The output AC current from the converter, through R48 l.Vll5-8 reverse biasses Dl0 unless 1:he terminal voltage exceeds
to restore l.Vl8 input virtual-com_mon, passes via R85 into the 4.8V Rl'vlIS, whenM15-8 swings to 1:he negative rail and pulls the
Current A...mplifier feedback resistor R43. It generates a reference
UM STline to -15V (logic-0).
AC voltage between tl1e output of the whole Current Amplifier
and its i.,,verting input. This is reflected on its non-inverting side The diode D10 is part of a diode-OR gate, linking UM ST to the
by the currentflowi.ng through therange-switchedorn:put 'shunts'. ill/! ST line, which enters lhe Reference Divider at J4-76. TI1e
The whole amplifier is also used as Lhe Voltage-to-Current CPU receives the UM S'f status signal via the SSDA serial
Converter for DC output currents (s1ib-section 10 .1.8). The interface, and if at logic-0 presents the 'Error OL' message on the
Prearnplifier and Outpm sections have the same operation as in MODE display. If in the lOOmA or IA range, the Output is
the DC case. turned off ;md the DC precision :reference is ramped to zero, to
limit the power developed as heat within the instrument. Oilier
sources and the effects of the LIM ST signal are described in :sub-
section 7.12.7.

10-4
10.2 RESISTANCE

Eight standard resistors are mounted on the Ohms or Current/ the resistor value a.nd setting the display to read that measured
Ohms Assembly, each, being part of a combination whose total value, without removing the instrument covers (refer to User's
resistance is factory-adjusted to a value close to nominal. They Handbook Section 8). The factor which corrects the nominal
are 4-wire connected 1:0 the instrument terminals by range- value to the measured value is stored in non-volatile RAJ\1 on the
selection relays. Nominal values are 10.Q, 100.Q, llill, lOk.Q, Digital assembly.
lOOk.Q, lMr.!, lOMQ and lOOMQ.
During recalibration, if a user enters a value on the OUTPUT
display which is outside the spa.'1 of the calibration memory, the
instru,-nent displays "Error 6". As my resistor drift is normally
just a fraction of the span, "Error 6" appears only when an
RESISTOR CIRClHTS erroneous value is entered, (eg. if a resistor's value has been
cha.,ged by the stress of an overload).
10.2.2.1 4~Wlre Connectioll11 Symmetry.
(Circuit Diagram No. 430614 Page 11.8-3 or
401047 page 11.8-8).
A severe overload can alter a resistor's value, possibly ta.king it
For a.,y given resistor combination, lhe connections on the Hi
out of its c1:1Jibration memory span. 'fo restore the value to one
side are made through contacts of the same relays used for the Lo
which can be entered from l:he front panel, each resistor
side, except for the 'Q OUTPUT' relays RL24 and RL25. This
combination includes an internal trimmer (para 10.2.2.2). A
ensures that both sides of each resistor connect to the front panel
procedure for adjustment of the trinuners is given in svh-section
terminals through the samenumberof similar thennaJ connections.
1.4, but this should be limited 1:0 values less than about 50ppm
To achieve the low leal<age required for the Megohm ranges, outside tolerance. ][fa resistor is fmmd to be more than ±50ppm
particularly for the lOOMQrange, afur,J1errelay RLl 7 is used to outside its tolerance, it is likely to be unserviceably damaged, so
isolate the parallel lea;kage paths of the lower range circuits. it is advisable to have such a resistor tested or replaced by an agent
of Datron Instruments.
The use of latching relays eliminates the heating effect from Lheir
solenoids. 13ut it is importmlt that all non-thermal relay contacts
are made back-to-back to cancel them1al effects. Thus only the
connections to non-latching relays RL24 and RL25
to be back-to-back, although most others are.
This symmetrical, 4-wire arrangement transfers the stabilir-y a.nd
accuracy of each resistor to the front panel terminals.
In Q function, selection of Remote Sen-5e mode LED lit)
displays the measured value for the 4-wire connection, but with
Lhe Remote Sense LED unlit, the 2-wire value is displayed.

R63, R64, R65 and R72 are 4-wire resistors, so for lOQ-lOKQ
selections the 4-wire junction is at the standard resistor itself.
These resistors areparallel-trirruned. R62,R74, R73 a.ndR71 are To avoid the intrusion of extra thermal voltages, no additional
two-wire resistors. For these higher resistance values, lOOKQ, switching is employed for selectionof2-wire connections. Users
lMQ, 1OMQ and 1OOMQ, series trimmi_ng is used and the 4-wire are recommended to connect only to the Hi/Lo terminals, so the
junctions enclose the series chain. 2-wire mode should be recalibrated at iliese terminals.

Trimming resistors are selected and adjusted in the factory, in ill

carefully-controlled environment, against traceable standards.

With Q function selected, pressing the zero key on the front pariel
1 METHODS closes the contacts of relay RL16. This provides a true 4-wire
short, the existing resistor remaining connected.
10.2.3.1 Routine Autocalibratlon ][f ilie Rem sense LED is lit, the displayed value is zero and cannot
be calibrated; but if unlit, the resistance of the short plus internal
The nominal value of each standard resistor is labelled below its
wiring can be measured imd entered on ilie display, using four-
RANGE key. When the key is pressed, the OUTPUT display
wire measurement at the Hi and Lo rerminals. Subsequently,
does not show nominal; but instead gives the value measured at
each time the 'Zero' key is pressed in 'Q' function with the Rem
its most recent calibration. This is the main criterion for many
oormse key LED unlit, this entered value will be displayed.
users, rather ilian having the resistor internally trimmed to
nominal.. So routine recalibration consists of accurately measuring

10-5
10.3 FUNCTION SWITCHING.
1 OUTPUT = FUNCTION
(Circuit Diagram430614 Pages 11.8-1 and 11.8-3 or 401008 page 11.8-6 or401047 page 11.8-8)

The PHI, PLO, SHI and SLO connections are routed via the Cl.lll!'JreIDlt Ol.lltjpl.lli!§
Current, Ohms or Current/Ohms assembly, and it is there that Relay RL23 contacts are latched open, and if Option 50 (Ohms
they are switched between functions. The outputs of the t.hree function) is fitted relays RL24 and RL25 are un-energized.
functions V, I and n are switched by separate relays onto the Relays RL8 and RL9 are energized to connect the output from the
terminallines (Fig 10.4 ): selected shunt to the PHI a.nd PLO lines only.
Voltage 01.l.tpum Resl:,tance
Relays RL8 and RL9 are de-energized as shown on pages Relay RL23 contacts are latched open, and if Option 40 (Current
11.8-1 or 11.8-6 as applicable. Relays RL24 and RL25 are de- function) is fitted relays RL8 and RL9 are un-energized. Relays
energized as shown on pages 11.8-3 or 11.8-8 as applicable.The RL24 and RL25 are energized to connect the selected standard
DC or AC Voltage Power imd Sense connections to the DC resistor to the four PHI, PLO, SHI and SLO lines, regardless of
assembly are routed out to the I+, I-, Hi a.11d Lo tenninals via the state of Remote/Local switching. To avoid the intrusion of
latching relay RL23 closed contacts. extra thermal voltages, no additional switching is employed for
selection of 2-wi:re connections.
NIB If neither Option 40 nor Option 50 is firced, t.he Current/
Ohms Linkpcb is fitted in its place to make dilectconnection
from the DC assembly to the terminals (Section 3 ).

DC or AC LINES to
VOLT AGE TERMINALS
JS-8/9
PHI

SHI

SLO

10-6
1

page 11.8-7 or401047 page

The a.nalog control are tra.cTIBferred i,-no on the

Reference Divider olli:,c:,.,rn., v arid latched as RL2, 3, 4 !l..!,d 5 are activated and held
Serial/Parallel Data Converter. Offset is used: OTI 15V.
logic-0 = -15V, =OV. Zs!V
Relays RL 8, 9, 24 and 25 aire 24V activated the
The signals enter t..h_e Current, Oh:rns or Current/Ohi'TIS assembly
via J8 from the Mother assembly. 50ms UPD(][G) approx. 30V, but held on by 15V.
!Pofa.faedl
RLl, 7, Hl, H, 12, 13, 14, Hi, 17, 18, 19, 20, 23 and 26
are activated by approx. 7.5V; betweenMl0-
13 at -7.5V and either OV or -15V from the drive output of the
strung out bei-v1een the.
are 3,i::tiv ated

.hJJ the latched

fitted back-to-back to reduce se:11.!Be: 'i)Vhen its dYiver ov.tput at
temperature effects. For d1e fastest re.spo:nse, th_e oulput I2~tches select llt§ non-ti.na.l fu.raction; for
RL8~ 9~ 24 and 25 are not latched~ but c21n the f1Jnction is deselected, For RI.J 7 fh.ese conditions are
power fails, 2tny sensitive reversed. In fbe
tenninals.

reiays, lA output
allowing hold-on wit.Ii.out p;:isNer, to mini.mize tl'le inten1al
temperature at t.heir contacts. t'ss need a
-,.u01uui; chive, which is ""'"'""''"'"'""1
liJJfD'(f@u"~
drivers ~nd a bias an:tPiifa,r 430669 11.8-5).
a,,d M3 on the Clamp a:re octal
Tristate' buffern. Each is served two inverted enable
1 and 19 buffers - half the chip - per enabling
& can be seen from lihe circuit diagra.,,1s, ,he relays are strung out
between the output of their bias amplifier (-7 .SV a.,d Whenever a switching commmd has been received, t..h.e CPU
the drive outputs from the Clamp assembly. performs a control data tr1mSfer and the UIP'D(IG) line from J8-60
The bias amplifier MlO is a frequency-compensated voltage is pulsed to -15V for 50ms.
follower, buffering the tapping of auem.1u1.tor AN5/R97. So one Generally, the switching logic places a logic-I (OV) on the input
side of each relay is held permanently at -7.SV. The relay drivers ofselected drivers, and fogic-0 (-1.SV) on those whose function
on the Clamp assembly cm provide ouilputs at OV or -15V when is not selected. Because all !the buffers are non-inverting, during
enabled by the UPD(IG) pulse, but return to Instate when disabled. the update pulse a dlriver selects its function by setting its output
A relay is therefore driven Ito one or ilie other of its bistable states voltage to OV, deselecting by pulling its output voltage to -15V.
during update, then magnetically latched in ilie chosen smte The driver serving RU 7 (M3-15/5) perform.sin reverse, J13-15
when the driver output returns to ooen--cu:cuu. being pulled w logic-0 w allow selection of the lower resistance
ranges.

10-7
 CLAMP ASSEMBl Y
(Circuit Diagrams 430614 Page 11.8-2
or401008 Page 11.8-7 or 401047 Page 11.8-9;
and 430669 Page 1 J .8-5 ).

On the Current, Ohms and Current/Ohms Relay Drive Logic

circuit diagrams the Clamp assembly is shown in block form
The function of M2 is to decode the octal Ohms Ranging signai
only. Also, the pcb pin numbers correspond to t_he pin numbers
RQ20 with the Q ZERO signal, providing switching information
of the buffer chips: Jl4 and Jl5 being the co11_nections to Ml and
for individual relays. To provide flexibility fornt.lier applications,
M3 respectively. For signals crossing the block from bottom to
and decoded outputs for M2 a:re taken out to pins of Jl 8,
top, the output of each non-inverting buffer i£; drawn opposite its
the outputs being linked back to selected pins of Jl3 and Jl4.
input, so the function remains unchanged as it crosses the block.
These cormections are shm'm on page 11.8-2 o..nd 11.8-9.
As a further aid to identification, Lhe pins of any one buffer are
numbered so that the input and output numbers add up to 20. Refer to sub-section 10 .4 .6 and Table 10 .3 for a discussion of the
M2 decode and resultant relay operation.

As the UPD(IG) signal i£; distributed as the 'enable' to 16 buffers,

it is itself buffered by M16 atM16-3 before being fan,,edout. So
the four UPD(IG) cmmections at the left of the block are inputs
to four sets of four buffers.

10,4L3L2 12li,1'rn~ir
(Circuit Diagram 430669 11.8-5 ).
The40244octalbuffercanbesourcedfromseveni!manufacrurern.
Some variants S:CR avafonche if the output
nw,tPri"p,rl
I
voltage were to exceed the rnil -voltage, but some are not. Each
buffer drives its omput into the solenoid of a and is
w
switched on and the update enable. The self iJiductanre of
the solenoid can generate back EMFs well in excess of the mi!
voltage, so to gm:rrd
it was decided to
cla.i,1p circuit
On the Clamp ,.=,,~""v_,, -15V
supplies, each deliverii,g :rni~ulat~,a c1m,filP.-,-1·mn less \
than the :rail voltage, called '+VE CLA1VIP' an.d '-VE CLAMiP'.
A diode connected from the buffer outptii: to each of !11e
lines allows the output to 1ise to the rail but not
to exceed it

10-8
The Function relays are located at top right of the circuit diagram The function selection logic is included later in the descriptions
on page 11.8-2, 11.8-7 and 11.8-9. ats11h-sections 10.4.5 and 10.4.6.
JRL8 and! RL!!)) on page 11.8-2 or 11.8-7, when energized, select
the Current function.
lRUAl 1.md RJLZS on page 11.8-2 or 11.8-9 select the Oh.rns (Circuit uuwro.u,. 430614 Page 11.8-2 or 401008
function. Page 11.8-7)

RlLZ3 connects the Voltage outputs to the instrument terminals.

For the analog connections refer to sub-section 10.3.
Whenever a switching comm.and has been received, the CPU
performs a control-data tra.-.sfer a.nd the UPD([G) line from J8-
60 is pulsed to for 50rns. and Q7 remain cut off until
Selection of the DC or AC Voltage function at the frontp1mel also the pulse arrives. The pulse tlli-ns a..11d on, applying +15V
deselects C1LTrent and Ohms functions in software. The XA\lCT to the connected to collector.
and Q FNCT signals are set to logic-1, and decoded Ml7-8, selected relays axe i:hu.s energized 30V, but after the
Ml6-10 and M16-ll to set the V OUTPUT signal to ==-=ccc-
UP D(J: G) ended
RL23,
output. 'This method reduces the local heat, c.pnp·a ,,,r1 0 energized
4-) output to solenoids, i..vi the contacts.
RL2, RL3 a.nd RU axe all
If 40 (Current function) is fitted 9 and OFF signals are decoded so that RUl 1md RL9
RL8 and RL9 are un-energized, dl!,ccmr1.e,:tn the current output are energized v;hen u'1e Current function has been selected
RLl is latchecl in the and is Oi\L
lA R80;
con.nects the 1OrnP\/1 OOmP\ filter.

'Tl-P_e I FI\J1CT ~ BARI{ a:nd D·C I crre decoded so thzit RL 7

a."lcl RL26 c&11 be eneri,u.ed
beeri selected and the ha;; >i"lOt ']8A.Rf( edo1

In the A.C \\J:nd.er fues(e condit!o:ris; if DC Current is chosen~ d1en the DC I

P.nP.-r•""'"'~ RI_,9, Tnis discor1nects the J.\,Ci REF Jines
from. the ACV lines. ~Chus the is "'""'·p,,,.,,,.,, and RL7 closes its
contacts
(1V18 on tl1e Current or Cu:crent/01lrrns o,,,,,,,,n.,,_y converter IT P:o.C Current 1s chosen; DC I is at
D so M9-9
a.,d so no current is generated. AC FNCT connects the and RL26 closes its contact. This connects the
ACV li.ries for ranges. to the input of its

RL8 RL24 RL26 RL9 RL10.

RL9 RL25 (Latching RL2 RL2
OFF BARK IFNCT D.FI\JCT DCI AC FNCT * = Pin 1 at Logic-1)

Del 0 0 0 1
AC! 0 IZJ 0 0 * *

DC'\! 0 0 0 i
IAC'IJ 0 0 0 0 *

Q 0 0 0

T~B!l!E [email protected]!

10-9
Ml2 is a Darlington open-collector inverting driver array. The DC Cl.!!nefilt Zell"@
relay drive logic places a logic-1 (OV) on the input of the selected The DC Current output can be continuously incremented between
drivers and logic-0 (-15V) on those not required. A selected its negative and positive Full-Scale outputs. Thus zero output can
driver operates its relay by pulling its output to -14V. be selected by operator-adjustment of the 'REF' value using the
'OUTPUT' keys, or pressing the 'Zero' key, which ramps REF to
The octal Current Rangh1g signal is decoded by M6 to
zero. Tne zero value is corrected during RoutLne Autocalibration.
provide four individual outputs for Range relays:
AC Ci!.llnent Zenll
Rafilge ~efonill!lce §orunrce
For AC zero output, as each range operates only between 9% and
DC AC
200% of nomin31, zero can_not be selected by adjustment of the
JlA Q2 RLl -2V to +2V lV Range OUTPUT keys. The AC zero is normally obtained by using the
JlOOl!llllA Q3 RL3 -20V to +20V lOV Range 'Zero' key which, through software, disconnects the lines from
HlmA Q4 RL2 -20V to +20V lOVRange the current generator to the I+ and I- terminals.
JlmA QS RL4 -20V to +20V lOVRange
The 'OFF signal is set to logic-1, and the IR2 _0 code is '0,0,0'.
100µA Q5 RL4 -2V to +2V lVRange
This sets all M6 outpui:S to logic-0, so the Cunent Range relays
The Q3 and Q4 decoded outputs for the 1OOmA and 1OmA ranges RL2,RL3 end RlA-, and the filter relay RLS, are all un-energized,
are ORed at Ml 7-6 to operate RLS, which introduces HF filter and RLl latches in the lA position is selected in preference
capacitor C49 on both Lhese ranges. to
RLl is a bistable with nn,e,-rn,im,o solenoid. RL8 a.,d RL9 are de-energized the OFF to
A logic-1 at pm 1 switches the lA range on, m<10 open-crrcuit theX+ andll- terminals, and short the current amplifier
switches it off. NormBJly 1 is on open collector, .so output to common-H. Vvhi1e setting OFF to logic-1, the CPU
the relay remains latched ixi. one bistable state with i!:S solenoid also forces the Precision DC Reference to rrunp down to zero, so
the 511:ru; UPD(l[G) also falls to zero~ fu"l.d the current
generator has no Thus the high current amplifier is not
state to to
ends.

f!Lllmi©Uli@ml ~©lliil!1Jl'!l <C@@G Ltq© ~flLID§ {i,©lfi'WSU®@

Q2 03 Q4 Q5 07 RU RU RL2 RL3 RL4 RL5 RLS

i+ ij- RL9
2 ·15 1 6 .I!. 12- 12+

'if@~Q i\J/A 1 1 1
--
1
. *
I
I
1 0 1
I 1 * * "
I
DCi 1mA 1 !Zl i 1 • . •
©r 10mA i 0 0 1 . . . .
AC! 100mA 0 1 1 i . . . .
1A 0 1 0 1 . .
ACiZl!:l?dO Any (ZJ 0 0 •

10-1()
10.4.6 RESISTANCE SWITCHING LOGIC
(Circuit Diagram No. 430614 Page 11.8-2 or 401047 Page 11.8-9).
10.4.6.1 Output Switching.
Whenever a switching conunand has been received, the CPU Relay RLI7 is activated to connect the lower Ohms (<lMQ)
performs a control-data transfer and the UPD(IG) line from JS- ranges to the output line only when the Megohm ranges are not
60 is pulsed to logic-0 for 50ms. Ql andQ7 remain cut off until activated. Thisreducestheparallelleakage(paral0.2.2.1). NOR
the pulse arrives. The pulse turns Ql and Q7 on, applying+ 15V gate Ml9-6 combines the signals which will activate RLl 7;
to the relays connected to Ql collector. bearing in mind that the polarized RLl 7 connections between its
driver and the -7 .SV rail are the reverse of all the other latching
Any selected relays are thus energized by 30V, but after the relays. Thus it closes its contacts when Ml9-6 is at logic-0
UPD(IG) pulse has ended they are held on by the 13 .3 V between (-15V), not logic-1 (OV).
-0. 7V at the cathode of D2 and -14V at the selected driver (M20)
output. This method reduces the local heat, generated by energized The signal states which cause RLl 7 to close its contacts are:
relay solenoids, in the relay contacts. QFNCT - logic- I (Ohms function not selected)
or QR2 - logic-0 (lOQ, lOOQ, lkn, or lOkQ
The Q FNCT, BARK and OFF signals are decoded so that RL24
and RL25 are energized only when the Ohms function has been selected)
or QZERO - logic-1 (Ohms Zero selected)
selected, Output is ON and the Watchdog has not barked.
or J18-l - logic-1 (Clamp assembly M2 Q4 at
(i.e. If M16-9 [OFF•Q FNCT•BARK] = logic-I, RL24 and
logic-1 - lOOkQ range selected)
RL25 are energized).

10.4.6.3 Ohms Zero.

10.4.6.2 Range Switching
Range control data is input as a 3-bit code on QR0' QR 1 and QR2 The Q FNCT and n ZERO signals are NORed by M19-10 and
. inverted by Ml7-12 so that RL16 is activated either when the
lines. The bit-pattern is decoded by M2 in the Clamp assembly
to activate the correct relay(s) for the selected range. The Ohms function has been selected and the Zero Key has been
resulting variants arelistedinTable 10.3 against range selections. pressed, or at times when the Ohms function is not selected.

IR:ange IF!,,mge C@ci® M2 'Q' Outpu~ fieiayw Acthra tedl

(QR,.J (Clamp Assembly) (All latching relays)
Qf\ QR, QR0

1(JQ 0 0 0 Q0 RL13)
100.Q 12) 0 1 01 RL10)
1kn 0 1 0 02 RL14)
10kQ 0 1 1 03 RL12) Each relay selects when
100kn 1 0 0 04 RL11 ) pin 1 = Logic-1 (OV)
1MQ 1 0 1 05 RL20)
10MQ 1 1 0 06 RL19)
100MQ 1 1 1 07 RL18)

QZero (All Range relays deselected) RL16 Relay selects when

pin 1 = Logic-1 (OV}

Flanges .::1MQ (excluding Q Zero) RL17 Relay selects when

pin 12 = Logic-1 (OV}

TAB/LE UJ.3 OHMS RANGiNG LOGIC

10-11
 DEFAUlT AND STATUS LOGIC

10.4.7"1 "OFF" The full effect of the default is that relays RL5, RL16, RLl 7 and
RL23 are activated, the remainder are not:
The OFF signal is combined with the I FNCT and Q FNCT
signals to ensure that when the instrument OUTPUT OFF key is The Current and Ohms ciicuits are disconnected from the
pressed, the selected function's circuitry is disconnected from the terminals, but relay RL23 connects the Power and Sense lines
terminals. For Currem: outputs, RL8 and RL9 disco1mect the from the DC assembly to the terminals. However, on the DC
terminals from the current output; and for Resistance, RL24 a.,d assembly the sarne default has disconnected the voltage
RL25 disconnect the standard resistor. output from the lines.
The Current ranges aie deselected, but relay RL5 holds the
10L4.7a2 'BARK' HF filter in circuit.

TheBARKsignaliscombinedwiththeQ FNCT and DC !signals All Ohms standard resistors are deselected as well as
to ensure that when the Watchdog barks, the selected function is disconnected from the terminals; the 4-wire Ohms-Zero
disabled. For DC Current outputs, RL7 disconnects the REF short is activated, but is also isolated from the instrument
signal from the High-current V-to-I converter; for AC Current terminals by RL24 and RL25.
outputs, RL26 disconnects the drive from the AC reference V-to- As the Watchdog detects cert.ain malfunctions in processor or
I converter to the High current runplifier; and for Resistance, Analog Control transfer operation, the default is a safe holding
RL24 and RL25 disconnect the standard resistor. state, and subsequent changes will depend on the reaction of the
CPU to the event. The Watchdog is described in sub-section
The effects of 'BARK DELAYED' follow after 47ms.
6.4.6.

rn.4l.7a3 'BARK DElAYIEID'

If the Watchdog is activated, 1:he BARK signal is generated, and
47ms later all outputs from the Control Data latches in the The I/Q S'T line atJS-98 is pulled down to -15V (logic-0) for as
Reference Divider are 'Tristated' by the 'BARK DELAYED' long as the Current/Ohms assembly is fitted in the instrument.
signal. On the Current, Ohms or Current/Ohms assembly, this This state is passed back via the Reference Divider (J4-68) and
allows the pull-up resistors (Al'<Tl) and pull-downresistors (AN3) the SSDA serial link to the CPU (Circuit Diagram 430652 page
to become effective. At lhe same time the BARK DELAY"ED 11.44). Thus the CPU recognizes thattheCunent/Ohms assembly
signal sets a -15V pulse on the UPD(IG) line for 1.5 seconds is fitted, and can operate the appropriate progrlliTIB.
(M41 on page 11.4-5), to ensure that the latching relays on the DC
and Current, Ohms or Current/Ohms assemblies will respond to
the default state.

10-12
 DATRON INSTRUMENTS FAILURE REPOR1.

Please complete all sections and return with your instrument

Company: .......................................................................................................................... ·
Division: .................................... Department/Mail Stop ..................................................... .
User, Name: ...................................... Telephone .................................... Ext ................... .
Serial number: ................................................................................................................... .
Datron Return Authorisation number ............................. Date of failure ............................ .

Brief description of fault .................................................................................................... .

. Fault det,lu!s;:
is the fault present on all ranges? Yes CJ No CJ Not Applicable [J
if no describe: .................................................................................................................... .
is the fault present on all "functions? Yes CJ No CJ Not Applicable [J
is the fault: Permanent CJ
intermittent CJ
if intermitkmt um.for what conditions, doe,:; tho fault re-appear.......... ...

Does the instrument pass 'self test?"

Any fail/ermr message displayed:
Now: Ves [~-1 No CJ if yes describe ................................................... .

At the time of fault Yes CJ No CJ

if yes describe ................................................................................................................... .

Prior to fault: Yes CJ No CJ

if yes describe ................................................................................................................... .

!s the instrument used on I.E.E.E 488 bus? Yes CJ No CJ

Is the instrument normally enclosed in a rack? Yes CJ No CJ
Approximate ambient temperature .................................................................................... .
 1. IJAi1,1AGE IlN TAANSil"
1. GENERAL Claims for damage in '(ransit or loss in delivery of the goods will only be considered
The acceptance of a quotation, oi any goods supplied, advice given or service if the carriers and ourselves receive notice of such damage within seven (7) days
rendered includes the acceptance of the following terms and conditions and no of delivery or in the event of loss of goods in transit within fourteen (14) days of
variation of or addition to the same shall be binding upon us unless expressly consignment.
agreed in writing by us. Any order shall be subject to our written acceptance.
fJ. TRANSFER OF PROPEmv & RISI{
2. QUOTATION Title and properly of the goods shall pass when lull payment has been received of
Unless previously withdrawn our quotation is open to acceptance in writing within all sums due to us whether in respect of the present transaction or not. The risk in
the period stated or where no period is stated within thirty (30) days after its date. the goods shall be deemed to have passed on delivery.
We reserve the right to correct any errors or omissions in our quotation. Unless
otherwise stated all quotations are firm and fixed. The prices quoted are based on 9. WARRANi'I'
manufacture of the quantity_and type ordered and are subject to revision when Weagreeto correct, either by repair.or at our election, by replacement, any defects
interruptions, engineering changes or changes in quantity are caused or requested of material or workmanship which develop within the warranty period specified in
by the customer_ the sales literature or quotation after deliveiy to the original purchaser. All items
claimed defective must be promptly returned to us carriage paid unless otherwise
arranged and will be returned to you free of charge. Unless otherwise agreed no
3. LIABILITY FOR DELAY
warranty is made concerning components or accessories not manufactured by us.
Any delivery times quoted are from the date of our written acceptance of any order
We will be released from all obligations under warranty in the event of repairs m
and on receipt of all information and drawings to enable us to put theworf, in hand,
modifications made by persons other than our own authorised service personnel
Where delivery is to take place by instalments each such instalment shall constitute
unless such repairs are made with our prior written consent
a separate contract. We will use our best endeavours to complete delivery of the
goods or services in the periocl stated but accept no liability in damages or
otherwise for failure to do so for any cause whatsoever. In all cases of delay the
·w. PATENT'>
We will indemnify you against any claim of infringement of Leiters Patent,
delivery time shall be extended by reasonable period having regard to the cause
Registered Design, Trade Mark or Copyright (published atthe date of the contract)
of delay_
by the use or sale of any goods supplied or service rendered by us 10 you and
against all costs and damages which you may incur and for which you may become
4. PAYMENT liable in any action for such infringement. Provided always that this indemnity shall
not apply to any infringement which is due to our having followed a design or
Payment shall be made net cash within thirty (30) days of delivery or in accordance instruction furnished or given by you or to the use of such goods or service in
with the payment terms set out in the quotation. Unless specifically stated to the association or combination with any other article, material or service not supplied
contrary payment shall be in pounds sterling. In the even! o! any payment to us by us. This indemnity is conditional on your giving to us the earliest possible notice
being overdue we may without prejudice to any other right suspend delivery to you in writing of any claim being made or action threa1ened or brought against you and
or terminate the contract and/or charge you simple interest on overdue amounts at on your permitting us at our own expense to conduct litigation that may ensue and
the rate of 2-5% above the ruling Bank of England Minimum lending Rate. No all negotiations !or a settlement of the claim or action_ You on your partwarranithat
payment to us shall in any circumstance be offset against any sum owing by us io any design or instruction furnished or given by you shall not cause us to infringe any
you whether in respect of the present transaction or otherwise. letter Patent, Registered Design, Trade Mark or Copyright in the execution of your
order.
5. INSPECTION & TEST
All goods are fully inspected at our worl{s and where practicable subjected to our
n [DIOCUME!\irtmON
All drawings, plans, designs, software specifications, manuals and technical
standard tests before despatch. II tests are required to be witnessed by your
documents and information supplied by us for your use or information shall remain
representative notice of this must be given at the time of placing the order and notice
at all times our exclusive property and must not be copied, reproduced, transmitted
of readiness will then be given to you seven (7) days in advance of such tests being
or communicated to a third party without our prior written consent
carried out In the event of of any delay on your part in attending such tests or in
carrying out inspection by you after seven (7) days notice of readiness the tests will
1::!. f~USli"lfil.T!ON
proceed in your absence and shall be deemed to have been made in your presence
Ii any contract or any part of ii shall become impossible of performance or otherwise
and the inspection deemed to have been made by you. In any event you shall be
frustrated we shall be entitled to a fair and reasonable proportion of the price in
required promptly after witnessing a test or receiving test results of witnessed or
respect of the worlt done up to the date thereof. For this purpose any monies
unwitnessed tests to notify us in writing of any claimed defects in the goods or of
previously paid by you shall be retained against the sum due to us under this
any respect in which it is claimed that the gooq_s do not conform with the contract.
provision. We may dispose of the goods as we think fit due allowance being made
Before you become entitled to reject any goods we are to be given reasonable time
to you for the net proceeds thereof.
and opportunity to rectify them. You assume the responsibility that the goods
stipulated by you are sufficient and suitable !or your purpose and take all steps lo
~ 3. ~ANi<i'l!Ull'urt::11'
ensure that tl1e goods will be safe and wi!hout risk to health when properly used.
If the purchaser shall become bankrupt or insolvent, or being a limited Company
Any additional certification demanded may incur extra cost for which a special
commence to be wound up or suffer a Receiver lo be appointed, we shall be at
quotation will be issued.
liberty to treat !he contract as terminated and be relieved of further obligations. This
shall be without prejudice lo our right to claim for damages for breach of contract.
8. DELIVERY AND PACi<ING
All shipments are, unless otherwise specifically provided, Ex-works which is the 141. l!::GAl iNTERPIU:TATION
address given on the invoice. An additional charge will be made for carriage and Any contract will be deemed to be made in England and shall be governed and
insurance as necessary with the provision that all shipments shall be insured and construed for all purposes and in all respects in accordance with English law and
this insurance expense shall be paid by the purchaser. Where special domestic or only the Courts of England shall have jurisdiction.
export packing is specified a charge will be made to cover the extra expense
involved.
 Sales arid Service

tJcJtrC!n
Datron Sales and Service Representatives Worldwide

COUNTRY and REPRESENTATIVE Telephone Telex Fax

AUSTRALIA
Scientific Devices Pty. Ltd
PO Box 63, 2 Jacks Road, 3 579 3622 AA32742 3 579 0971
South Oakleigh, Victoria 3167

BELGIUM
Air-Parts Internatim:1.a! B. V.
Avenue Huart-Hamoir, 1-Box 34, 2 241 6460 2 241 8130
1030 Bruxelles

BRAZIL
Sistrmllk!i hl.stru:mellltm:ao E Sistem:as Udl2
Av. Alfredo Egidio de Souza A__ranha 11 247558 57155 SNCS 11 5238457
75-3 & 4 Andares-Jd. Santo Antonio,
CEP 04726 Sao Paolo

CHINA
Tfanjilll Zhl[mg Hl.!liui. Sdentifk fostrum.erutll Corp.
No. 59 Zhao Jia Chang Street, Tianjin
Hong Qiao Section, Tianjin 753732 22252 625

DENMARK
Instrutek A/S,
Christiansholmsgade 75 6H 100 75 615 658
8700 Horseru;

EASTERN EUROPE
Amtest Assodate!ii Ud
Amtest House, 75-79 Guildford Street, 0932 568355 928855 0932 561919
Chertsey, Surrey KT16 9AS, England

EGYPT & MIDDLE EAST

Electronic Engineers Uaillon Office
PO Box 2891, 19A Aswn Street 269870 22782
Horriya, Heliapolis, Cairo

FINLAND
Profelec OY
PO Box 67, 00421 Helsinki 42 0 5664477 125225 PROFE SF 0 566 2998

FRANCE
M. B. Electronlque
606 Rue Foumy, Zide Bue, 139 568131 695414 139 565344
Post Box 31, 78530 Bue

WG1
Sales and

COUNTRY ,imd REPRESENTA1lWIE T@ieph©lnl@ felr;m fax

WEST GERMANY
WA VlETEK Eleictrnll1lks GmbH
Preisinger StraBe 34, 0 89 96 09 49-0 5 212 996 WVTK D 0 89 96 7170
D-8045 Ismani.,g

GREECE
Ameirk@n Tedmkal E!!iltelrJpir!ses SA
PO Box 3156
39, Agiou Konstantinou Streel:, 5240620 216046 ATE GR 5249995
Atheru; 10210. 5240740

HONGKONG
Eurntlhle1rm (JFair lE2JStt) U«l!
18/F., Gee Chang Hong Centre, 8140311 (Sales) 72449 EFELD HX 8735974
65 Wong Chm: Hang Road, Hong Kong 546391 (Service) 72449 EFELD HX 8700497

INDIA
Technk@H Trnulle JLmJrn
Deodahar Centre, Gyani Compound,
424 Ma:rol Marashi Road,
Andheri (East), 22 6362412 1179261 TTL .IN 9122 637 6719
Bombay 400 059
413, Pratap Chambers, Gurudwara Road,
Karol Bagh,
New Delhi - 110 005

][N![)IONJE§llA
C V, Sclt!mi«l!tt MU!Fa bn«l!(i]ill1lesft21
Delta Bldg., Block A, No. 30, 6221 3807844 46729 6221 3807847
JL Pranoto No 1-9,
Jakarta 10160.

IJREJLAN![)I
ETiectrrrnmk
]El)]JrllD
Unit 1, Pm:k, 01952326 01 952246
Sandyfonl fud, Est,
Dublin 18.

ISRAEJL
JDJIJ'11'-EL Tecl:nID1oiogfo§
PO JBox 21362, Office 60, 3 453157 342105 3 54414158
Pinkas S:t., 'fel-Aviv 151213,

lITAL\'(1)
Slistreil SJPA
Via Pellizza da Volpedo 59 021518 1893 334643 02 618 2440
20092 Cinisello JBalsruno, Milano

KTAJLY(2)
Sistrell SPA
Viale lErminio Spalla 41 06 5041367 625857 06 504 0067
00142 Roma

ITALY(3)
Sistreil SPA
Via Cintia Parco S. Paolo 35 0817679700 0817661361
80126 Napoli

WG2
 Sales and Service

COUNTRY and REPRESENTATIVE Telephone Telex Fax

JAPAN
G & G Japan lm:
No. 406, 12-16, 4-Chome, 3 8130971 2722884 !CHAIN J 3 8159216
Hongoh, Bunkyo-ku, Tokyo

KOREA
Sama Electronics Corprnratkm
CPO Box 9517, Seoul 2.271 2761 K 26375 SAMATR 2 271 2764

MALAYSIA
Schmidt Sdellltific SDN BE!D
13th Floor, Wisma Mirama, 603 242 7122 30035 603 248 5143
Jalan Wisma Putra, P. 0. Box 10592,
50718 Kuala Lumpur.

MOROCCO
Minhol SA
64 Rue El Mortada, 254945 24064 254969
Casablanca 02.

NETHERLANDS
Air Parts Intern:1.ti.onai BV
PO Box 255, 12 Kalkovenweg, 172043221 39564 1720 20651
2400 AG Alphen aim den Rijn

NEW ZEALAND
G. T. S, Engineering Udl
5 Porters Avenue, Eden Terrace, 9 392464 9 392968
PO Box 9613 Newmarket AUCKLAND

NORWAY
Morgensliiierne & Co,
Olaf Helsets vei l, 2289490 71719MOROFN 2 289494
P.O. box 15 - Bogerud
N-0621 Oslo 6

PORTUGAL
Decada SA
Rua Margarida, 14103420 15515 14101844
Palla. 11, Alges
1495-Lisbon.

SAUDI ARABIA
Electronic Eq1.dpment Marketing
PO Box 3750, 14771650 401120 1 4785140
Riyadh 11481,

SINGAPORE
Schmidt Scientific (PfE) Ud
2 Jalan Kilang Barat, 65 272 7233 23736 65 273 4750
Singapore 0513

SOUTH AFRICA
Altech Instruments (Pty) Ltd
PO Box 39451, Bramley 2018 11-444-6940 422033 11-444-7455

SPAIN
ESSA (Equl.pos y System1,u; SA)
C/Apolonio Morales 13-B, 1458 0150 42856 458 0298
E-28036 Madrid

WG3
COUNTR'\f ~midi IFIIEIPIRESIENTA1f"l'l!IE
SWEDEN
Femer E!ednillllik AB
· Jarfallavagen 186, +46 758 189 90 10312 FERNER S +46 758 179 90
S-175 40 Jrufalla

SWI1l'ZEllU..,AND
KoflittrnIDl Ellecitrm.ik AG
Plhly5kall Addre§§:
In der Lubeuen L (01) 736 4111 822196 + KOElI., CH (01) 734 2448
CH-8902 Urdorf
P,m,tall Addrnas:
P.O. Box CH-8010 Zurich

'JfAlIWAN
JEverg@ Coiiporntti@lll
7th Floor - 285, Section 3 2 7150283/4/5 2 7122466
Nan King East Road,
Taipei 10567

1lJN][']['E]Jl KlINGDOM
Datrnn Imtmme!l1lli§ lLM!
W ruvetek CaUlhraltfon JDRvfafoilll
Hurricane Way, Nonvich 0603 404824 975173 0603 483670
Nonvich, Nmfolk NR6 6IB, Engla..11d

\UNTJ!'lEllJi S'f ATES ofr' AMERJ!CA

lDatrrmn lli.TJ1sli:J:'l!illl!Ille!llil.s TW"X
c/o W21vetteRi JRJF ll"r©rll.!ltffi liililc. 787 3915 3413226 788 5999
Wavetek Cmi!lllllfi!l.!lililk21\tfofill Jmvi!sfolill
5808 Churchmm
Indianapolis, Indiana 46203

W ave\te[i E@socern Are:E! S:lllk,§

35 Pmefawn Road, Suite 209W, 454 8LIAO 454 8446
Melville, New York 11747

W avetelk W <B§tteK'lll! Aurea Salles TWX.

9045 Balboa Avenue, San Diego, 565 9315 335 2007 227 6221
California 92123

lDattrnlill lim11,tn.1ililllelilll:li Ud!

Wave~elk C:aUIJ:Jrratfo!lll JDlnvfakm
Hurricane Way, Norwich Airport, 0603 404824 975173 0603 483670
Nonvich, Norfolk NR6 6IB, England

WG4